KR20060077065A - System on chip device and method for manufacturing the same - Google Patents

Abstract

The present invention is to provide a system-on-chip device and a method of manufacturing the same that can prevent the deterioration of the logic transistor by forming a memory capacitor after the logic gate is formed, and to simplify the process, the system-on-chip device of the present invention is a semiconductor substrate, A device isolation insulating film formed in a predetermined region of the semiconductor substrate and having a predetermined depth, a lower electrode formed over a portion of the surface of the semiconductor substrate while being formed in a trench of the device isolation insulating film, a dielectric film on the lower electrode, and an upper portion on the dielectric film A capacitor having an electrode, a gate of a logic transistor formed on a selected surface of the semiconductor substrate with a gate insulating film interposed therebetween, a first doped region formed in the semiconductor substrate under the lower electrode, and formed in a semiconductor substrate on both sides of the logic gate; One of the first doping Station connected to the second doped region, and is formed in a semiconductor substrate of said logic gate the other includes the other of the second doped regions and electrically connected to the third doped region.

System-on-chip devices, SOCs, capacitors, trenches, logic gates, bottom electrodes

Description

System-on-chip device and method of manufacturing the same {SYSTEM ON CHIP DEVICE AND METHOD FOR MANUFACTURING THE SAME}             

1A is a diagram illustrating a structure of a system on chip according to a first example of the prior art;

1B illustrates a structure of a system on chip according to a second example of the prior art;

2 is a cross-sectional view illustrating a structure of a system on chip device according to a first embodiment of the present invention;

3A to 3E are cross-sectional views illustrating a method of manufacturing a system on chip device according to a first embodiment of the present invention;

4 is a cross-sectional view illustrating a structure of a system on chip device according to a second embodiment of the present invention;

5A to 5E are cross-sectional views illustrating a method of manufacturing a system-on-chip device according to a second embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

31 semiconductor substrate 32 device isolation insulating film

33: trench 34: lower electrode                 

35: capacitor dielectric film 36: gate insulating film

37: first doped region 38a: logic gate

38b: upper electrode 39: second doped region

40a: Gate spacer 40b: Capacitor spacer

41: third doped region 42: silicide

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly, to a System On a Chip (SOC) device integrating a DRAM and a logic circuit, and a manufacturing method thereof.

The increasing performance gap between DRAMs and CPUs requires new functional systems to merge logic circuits that drive DRAM arrays on a single chip. This approach has the advantages of more data lines, lower power devices, noise immunity, and smaller area than single DRAM or logic devices.

To take advantage of these advantages, many MDL products are currently being tried. That is, in order to implement a System On Chip (SOC) in which a logic device and a single DRAM array are merged into one chip, the logic device and the DRAM are processed at the same time by performing the same process on a single wafer, and operate according to their characteristics. MDL (Merged DRAM and Logic) devices are under development.                         

As a method for forming a memory capacitor of a single DRAM device, a cylindrical capacitor as shown in FIG. 1 is used.

1A is a diagram showing the structure of a system-on-chip device according to a first example of the prior art.

As shown in FIG. 1A, a device isolation insulating film 12 is formed on the semiconductor substrate 11, a gate 13 of a logic transistor is formed on the semiconductor substrate 11, and both side walls of the gate 13 are formed on the semiconductor substrate 11. The gate spacer 14 is formed.

In addition, an interlayer insulating layer 15 is formed on the entire surface including the gate 13, a storage node contact 16 penetrating through the interlayer insulating layer 15 is formed, and a lower portion of the memory capacitor connected to the storage node contact 16. The electrode 17 is formed.

The capacitor dielectric film 18 is formed on the lower electrode 17, and the upper electrode 19 is formed on the capacitor dielectric film 18.

However, the prior art as shown in FIG. 1A has a problem of degrading the logic device since the process of forming the memory capacitor after the process of forming the gate 13 of the MOSFET device is completed, and also over the gate 13 of the logic device. As the memory capacitor is formed, there is a problem of increasing the metal contact depth.

In addition, since at least three mask processes must be added to form a memory capacitor, the number of processes is long and production cost increases.

As described above, another method for implementing a system-on-chip device may use a MOS capacitor as shown in FIG. 2.                         

1B is a view showing the structure of a system-on-chip device according to a second example of the prior art.

As shown in FIG. 1B, a device isolation insulating film 22 is formed on the semiconductor substrate 21, and the gate insulating film 23 and the gate 24 of the logic transistor are stacked on the selected surface of the semiconductor substrate 21. . Here, gate spacers 25 are formed on both side walls of the gate 24.

Then, a doping region that becomes the lower electrode 26 of the MOS capacitor is formed under the surface of the semiconductor substrate 21, and the dielectric layer 27 and the upper electrode 28 are sequentially formed on the lower electrode 26.

In the semiconductor substrate 21 on both sides of the gate 24, doped regions 29a and 29b for source drain junction are formed.

However, the prior art as shown in FIG. 1B has a shorter period since the lower electrode 26 is very wide and has a relatively wide SN junction, leading to a disadvantage in that the loss of charge stored in the MOS capacitor is increased. There is a problem that refreshing should be performed.

The present invention has been proposed to solve the above problems of the prior art, and provides a system-on-chip device and a method for manufacturing the same, which can prevent the deterioration of the logic transistor by forming a memory capacitor after the logic gate is formed and simplify the process. Its purpose is to.

A system-on-chip device of the present invention for achieving the above object is formed on a semiconductor substrate, a device isolation insulating film formed in a predetermined region of the semiconductor substrate and having a trench of a predetermined depth, and formed in a trench of the device isolation insulating film, and partially on the surface of the semiconductor substrate. A capacitor having a lower electrode formed over, a capacitor having a dielectric film on the lower electrode and an upper electrode on the dielectric film, a gate of a logic transistor formed with a gate insulating film interposed on a selected surface of the semiconductor substrate, and formed in the semiconductor substrate under the lower electrode. A first doped region, a second doped region formed in the semiconductor substrate on both sides of the logic gate, and one of which is connected to the first doped region, and a second doped region formed in the semiconductor substrate on the other side of the logic gate; Comprising a third doped region electrically connected Gong.

In addition, the system-on-chip device of the present invention is formed on a semiconductor substrate, a device isolation insulating film formed in a predetermined region of the semiconductor substrate, having a trench having a predetermined depth, a sacrificial film formed on the surface of the trench, and a sacrificial film formed on the trench. A lower electrode formed over a portion of the surface of the semiconductor substrate, a capacitor having a dielectric film on the lower electrode and an upper electrode on the dielectric film, an epitaxial layer formed on the surface of the semiconductor substrate while filling between the lower electrode and the semiconductor substrate; A gate of a logic transistor formed on a selected surface of an epitaxial layer with a gate insulating film interposed therebetween, a first doped region formed in the epitaxial layer under the lower electrode and the semiconductor substrate, the epitaxial layers on both sides of the logic gate, and Is formed in the semiconductor substrate and any one of the first doped region And a second doped region to be connected, and a third doped region formed in the epitaxial layer and the semiconductor substrate on the other side of the logic gate and electrically connected to the other second doped region.

The method for manufacturing a system-on-chip device according to the present invention may include forming an isolation layer in a predetermined region of a semiconductor substrate, forming a trench by etching the isolation layer in a predetermined depth, and forming a trench on a surface of the trench. Forming a stack of a lower electrode of the capacitor and a dielectric film extending to a part of the substrate, forming a first doped region in the semiconductor substrate under the lower electrode while forming a gate insulating film on the surface of the semiconductor substrate, the gate Forming a gate of a logic transistor on an insulating film and simultaneously forming an upper electrode on the dielectric layer, and a second doping electrically connected to the first escape region in a semiconductor substrate between one side of the gate and the lower electrode; Forming a region.

Hereinafter, the most preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

2 is a cross-sectional view illustrating a structure of a system on chip device according to a first embodiment of the present invention.                     

As shown in FIG. 2, the system-on-chip device according to the first embodiment of the present invention is formed in a semiconductor substrate 31 and a predetermined region of the semiconductor substrate 31 and has a trench 33 having a predetermined depth. On the selected surface of the semiconductor substrate 31, a capacitor comprising an insulating film 32, a lower electrode 34 formed in the trench 33 of the device isolation insulating film 32, and formed over a part of the surface of the semiconductor substrate 31; The second doped region 39 formed on the gate (logic gate) 38a of the formed logic transistor, the semiconductor substrate 31 on both sides of the logic gate 38a, and the second doped region 39 on one side of the logic gate 38a. A third doped region 37 formed in the semiconductor substrate 31 and a third substrate formed in the semiconductor substrate 31 on the other side of the logic gate 38a so as to electrically connect the capacitors and electrically connected to the second escape region 39. And a doped region 41.

In FIG. 2, all of the first to third doped regions 37, 39, and 41 are doped with n-type impurities, and the first doped region 37 serves as an SN junction for connecting the lower electrode of the capacitor and the logic transistor. Do this. That is, the capacitor is composed of the lower electrode 34, the capacitor dielectric layer 35 and the upper electrode 38b, and for the connection between the lower electrode 34 and the second doped region 39 which is the source / drain junction of the logic transistor. The first doped region 37 is formed.

The lower electrode 34 constituting the capacitor is formed of a polysilicon film doped with n-type impurities, wherein the n-type impurities in the polysilicon film are subjected to a thermal process during formation of the gate insulating film 36. Diffuses into the first doped region 37.

The capacitor dielectric film 35 constituting the capacitor is formed of an oxide film, a nitride film, a ferroelectric film, or a combination thereof, and the upper electrode 38b is formed of a polysilicon film, a metal film (Ti, TiN, W, Pt) or These alloys are used.

A capacitor spacer 40b and a gate spacer 40a are formed on both side walls of the capacitor and both side walls of the logic gate 38a, and on one side of the logic gate 38a, the capacitor spacer 40b and the gate spacer 40a are formed. Is in contact with each other to cover the upper portion of the semiconductor substrate 31.

The silicide 42 is formed on an upper surface of the logic gate 38a, an upper surface of the upper electrode 38b, and an upper surface of the third doped region 41.

3A to 3E are cross-sectional views illustrating a method of manufacturing a system-on-chip device according to a first embodiment of the present invention.

As shown in FIG. 3A, an STI process is performed on the semiconductor substrate 31 to form an isolation layer 32.

Subsequently, after the well (not shown) process for forming the CMOSFET is performed, a portion of the device isolation insulating film 32 in the region where the memory capacitor is to be formed is patterned through a photomask and an etching process to form a trench 33 having a predetermined depth. ).

At this time, the depth of the bottom of the trench 33 is adjusted so as not to penetrate the device isolation insulating layer 32 to prevent the lower electrode of the capacitor formed in the subsequent trench 33 from being unnecessarily shorted with the semiconductor substrate.

Meanwhile, the device isolation insulating layer 32 is formed through a general STI process, but may be formed through a deep trench isolation (DTI) process.

After the trench 33 is formed, an ion implantation (Vt adjust ion implant) process for adjusting the threshold voltage of the logic transistor is performed, which improves the threshold voltage characteristic of the parasitic transistor whose gate is the lower electrode of the subsequent memory capacitor. Used for the purpose of field stop ion implantation.

The ion implantation process for adjusting the threshold voltage may proceed after the formation of the next capacitor dielectric film.

As shown in FIG. 3B, a polysilicon film doped with n-type impurities is deposited on the entire surface of the semiconductor substrate 31 including the trench 33 and then selectively patterned to form a lower electrode 34 of the memory capacitor.

Subsequently, a dielectric film is formed on the lower electrode 34, and then selectively patterned to leave the capacitor dielectric film 35 on the lower electrode 34. Here, the dielectric film used as the capacitor dielectric film 35 may be an oxide film, a nitride film, a ferroelectric film alone, or a combination thereof.

The lower electrode 34 is formed of a polysilicon film doped with n-type impurities, and the capacitor dielectric film 35 is formed of a dielectric film. Here, the n-type impurity doped in the polysilicon film is arsenic (As) or phosphorus (P).

The lower electrode 34 and the capacitor dielectric film 35 of the memory capacitor are formed on the inside of the trench 33 and on the surface of the device isolation film insulating film 32 providing the trench 33, in particular the lower electrode 34. One end of the substrate extends to the surface of the semiconductor substrate 31. This is to connect the source / drain junction of the subsequent logic transistor.

Meanwhile, before depositing the polysilicon film for forming the lower electrode 34, a pre-cleaning process is performed to remove the natural oxide film so that the lower electrode 34 and the semiconductor substrate 31 are not electrically shorted. Do it. At this time, the pre-cleaning process uses a hydrofluoric acid solution.

As described above, if the lower electrode 34 of the memory capacitor is formed along the surface profile of the trench 33, the capacitance of the memory capacitor may be increased. That is, the surface area of the lower electrode 34 formed along the surface profile of the trench 33 increases.

Although not shown, after forming the lower electrode 34, HSG, MPS, and the like, which are commonly known, may be further formed to maximize the surface area of the lower electrode 34.

As shown in FIG. 3C, a gate insulating film 36 is formed on the surface of the semiconductor substrate 31. At this time, since the process for forming the gate insulating film 36 involves a thermal process, it is possible to improve the electrical insulation characteristics of the capacitor dielectric film 35. In addition, an n-type impurity in the polysilicon film used as the lower electrode 34 is diffused toward the semiconductor substrate 31 by the thermal process involved in forming the gate insulating film 36 to form the first doped region 37. The first doped region 37 is an SN junction for connecting a portion of the lower electrode 34 to the source / drain junction of the logic transistor. That is, it serves as a storage node contact (SNC).

The gate insulating film 36 may also be formed of the capacitor dielectric film 35. In other words, the dielectric film remains on the semiconductor substrate during patterning after the deposition of the dielectric film, and the dielectric film is used as the gate insulating film.

Next, a logic gate conductive film of the logic transistor is deposited on the entire surface including the gate insulating layer 36 and then selectively patterned to simultaneously form the logic gate 38a and the upper electrode 38b of the memory capacitor.

In this case, the upper electrode 38b of the memory capacitor is formed on the capacitor dielectric layer 35, and one end thereof is not separated from the capacitor dielectric layer 35 so as not to be connected to the lower electrode 34 and the semiconductor substrate 31.

The conductive film used as the logic gate 38a uses a polysilicon film, a metal film (Ti, TiN, W, Pt), or an alloy thereof.

As shown in FIG. 3D, a lightly doped drain (LDD) ion implantation process is performed to form a source / drain extension (SDE) of the MOSFET to form a second doped region (1) in the semiconductor substrate 31. 39). At this time, the LDD ion implantation step is ion implantation of n-type impurities, the n-type impurities are arsenic or phosphorus.

As described above, the second doped region 39 formed through the LDD ion implantation is electrically connected to the first doped region 37 in the semiconductor substrate 31, and the first doped region 37 is formed of n-type impurities. Since it is formed by diffusion, the first doped region 37 and the second doped region 39 become doped regions of the same impurity.

As shown in FIG. 3E, a spacer insulating film is deposited on the entire surface, and then etched back to form a gate spacer 40a in contact with both side walls of the logic gate 38a. Here, gate spacers are formed on both sidewalls of the stacked structure of the lower electrode 34, the dielectric film 35, and the upper electrode 38b formed in a stacked structure at the time of forming the gate spacer 40a, which is called a capacitor spacer 40b. It will be abbreviated.                     

On the other hand, the gate spacer 40a and the capacitor spacer 40b may be in contact with one side of the logic gate 38a adjacent to the capacitor, whereby the semiconductor spacer 40a and the capacitor spacer 40b may be in contact with each other under the portion of the semiconductor gate 38a. The surface of the substrate 31 may be covered. Therefore, on the other side of the logic gate 38a, the gate insulating layer 36 is etched when the gate spacer 40a is formed to expose the surface of the semiconductor substrate 31.

Next, the source / drain ion implantation process is performed to form the third doped region 41. In this case, the third doped region 41 is formed in the semiconductor substrate 31 outside the gate spacer 40a formed on the other side of the logic gate 38a and is electrically connected to the second doped region 39.

Next, the silicide process is performed to form the silicide 42 on the upper surface of the logic gate 38a, the upper electrode 38b, and the upper surface of the third doped region 41.

4 is a cross-sectional view illustrating a structure of a system on chip device according to a second embodiment of the present invention.

As shown in FIG. 4, the system-on-chip device according to the second embodiment of the present invention is formed in a semiconductor substrate 31 and a predetermined region of the semiconductor substrate 51 and has a trench 53 having a predetermined depth. The insulating layer 52, the sacrificial oxide film 54 formed on the surface of the trench 53, and the lower electrode 55 formed over the portion of the surface of the semiconductor substrate 51 while being formed in the trench 53 on the sacrificial oxide film 54 are formed. A capacitor, an epitaxial layer 57 formed on the surface of the semiconductor substrate 51 while filling between the lower electrode 55 and the semiconductor substrate 51, a gate insulating film 38 formed on the epitaxial layer 57, The gate (logic gate 60a) of the logic transistor formed on the gate insulating film 58, the second doping region 61 formed in the semiconductor substrate 51 on both sides of the logic gate 60a, and the one side of the logic gate 60a 2 is formed in the semiconductor substrate 51 to electrically connect the doped region 61 and the capacitor. Claim is formed in the first doped region 59, the semiconductor substrate 51 of the logic gate (60a), the other side and a second flight area 61 and electrically third doped region (63) is connected to.

In FIG. 4, all of the first to third doped regions 59, 61, and 63 are doped with n-type impurities, and the first doped region 59 serves as an SN junction for connecting the lower electrode of the capacitor and the logic transistor. Do this. That is, the capacitor is composed of the lower electrode 55, the capacitor dielectric layer 56 and the upper electrode 60b, for the connection between the lower electrode 55 and the second doped region 61, which is the source / drain junction of the logic transistor. The first doped region 59 is formed. Here, an epitaxial layer 57 is formed in the gap between the lower electrode 55 and the semiconductor substrate 51 to connect the lower electrode 55 and the semiconductor substrate 51.

The lower electrode 55 constituting the capacitor is formed of a polysilicon film doped with n-type impurities, and the n-type impurities in the polysilicon film are subjected to a thermal process during formation of the gate insulating film 58. Diffuses into the first doped region 59.

The capacitor dielectric film 56 constituting the capacitor is formed of an oxide film, a nitride film, a ferroelectric film, or a combination thereof. The upper electrode 60b is formed of a polysilicon film, a metal film (Ti, TiN, W, Pt) or These alloys are used.

A capacitor spacer 62b and a gate spacer 62a are formed on both sidewalls of the capacitor and both sidewalls of the logic gate 60a, and on one side of the logic gate 60a, the capacitor spacer 62b and the gate spacer ( 62a is in contact with each other to cover the upper portion of the semiconductor substrate 51 and the epitaxial layer 57.

The silicide 64 is formed on an upper surface of the logic gate 60a, an upper surface of the upper electrode 60b, and an upper surface of the third doped region 63.

5A through 5E are cross-sectional views illustrating a method of manufacturing a system-on-chip device according to a second embodiment of the present invention.

As shown in FIG. 5A, an STI process is performed on the semiconductor substrate 51 to form an isolation layer 52.

Subsequently, after a well (not shown) process for forming a CMOSFET is performed, a portion of the device isolation insulating film 52 in the region where the memory capacitor is to be formed is patterned through a photomask and an etching process to form a trench 53 having a predetermined depth. ).

At this time, the depth of the bottom of the trench 53 is adjusted so as not to penetrate the device isolation insulating layer 52 to prevent the lower electrode of the capacitor formed in the subsequent trench 53 from being unnecessarily shorted with the semiconductor substrate.

Meanwhile, the device isolation insulating layer 52 is formed through a general STI process, but may be formed through a deep trench isolation (DTI) process.

After the trench 53 is formed, a Vt adjust ion implant process is performed to adjust the threshold voltage of the logic transistor, which improves the threshold voltage characteristics of the parasitic transistor gated by the lower electrode of the subsequent memory capacitor. Used for the purpose of field stop ion implantation.                     

The ion implantation process for adjusting the threshold voltage may proceed after the formation of the next capacitor dielectric film.

As shown in FIG. 5B, the sacrificial oxide layer 54 and the polysilicon layer doped with n-type impurities are sequentially deposited on the entire surface of the semiconductor substrate 51 including the trench 53, and then the polysilicon layer is selectively patterned to form a memory capacitor. The lower electrode 55 is formed. The sacrificial oxide film 54 is introduced to prevent etching loss of the semiconductor substrate 31 during the etching process for forming the lower electrode 55.

Subsequently, a dielectric film is formed on the lower electrode 55, and then selectively patterned to leave the capacitor dielectric film 56 on the lower electrode 55. Here, the dielectric film used as the capacitor dielectric film 56 may be an oxide film, a nitride film, a ferroelectric film alone, or a combination thereof.

The lower electrode 55 is formed of a polysilicon film doped with n-type impurities, and the capacitor dielectric film 56 is formed of a dielectric film. Here, the n-type impurity doped in the polysilicon film is arsenic (As) or phosphorus (P).

The lower electrode 55 and the capacitor dielectric film 56 of the memory capacitor are formed over the inside of the trench 53 and the surface of the device isolation film insulating film 52 providing the trench 53, in particular the lower electrode 55. One end of the substrate extends to the surface of the semiconductor substrate 51. This is to connect the source / drain junction of the subsequent logic transistor.

As described above, if the lower electrode 55 of the memory capacitor is formed along the surface profile of the trench 53, the capacitance of the memory capacitor may be increased. That is, the surface area of the lower electrode 55 formed along the surface profile of the trench 53 increases.

Although not shown, after forming the lower electrode 55, HSG, MPS, and the like, which are commonly known, may be further formed to maximize the surface area of the lower electrode 55.

As shown in FIG. 5C, the sacrificial oxide film 54 under the lower electrode 55 is removed by performing a pre-cleaning process before forming the gate insulating film. At this time, the pre-cleaning process is anisotropic wet etching, for example using a hydrofluoric acid solution.

As described above, after the sacrificial oxide film 54 is removed, a gap is generated between the lower electrode 55 and the semiconductor substrate 31.

In order to fill the gap, epitaxial layer 57 is formed by performing selective epitaxial growth (SEG).

As shown in FIG. 5D, a gate insulating film 58 is formed on the surface of the epitaxial layer 57. At this time, since the process for forming the gate insulating film 58 involves a thermal process, it is possible to improve the electrical insulating properties of the capacitor dielectric film 56. In addition, an n-type impurity in the polysilicon film used as the lower electrode 55 is diffused toward the epitaxial layer 57 and the semiconductor substrate 51 by the thermal process involved in forming the gate insulating film 58. 59 is formed. The first doped region 59 is an SN junction for connecting a portion of the lower electrode 55 and a source / drain junction of the logic transistor. That is, it serves as a storage node contact (SNC).                     

On the other hand, the gate insulating film 58 may also be formed of a capacitor dielectric film 56. In other words, the dielectric film remains on the semiconductor substrate during patterning after the deposition of the dielectric film, and the dielectric film is used as the gate insulating film.

Next, a logic gate conductive film of the logic transistor is deposited on the entire surface including the gate insulating layer 58 and then selectively patterned to simultaneously form the logic gate 60a and the upper electrode 60b of the memory capacitor.

In this case, the upper electrode 60b of the memory capacitor is formed on the capacitor dielectric layer 56, and one end thereof is not separated from the capacitor dielectric layer 56 so as not to be connected to the lower electrode 55 and the epitaxial layer 57. .

The conductive film used as the logic gate 60a may be a polysilicon film, a metal film (Ti, TiN, W, Pt), or an alloy thereof.

As shown in FIG. 5E, a lightly doped drain (LDD) ion implantation process is performed to form a source / drain extension (SDE) of the MOSFET to form a second doped region (i.e., a second doped region) in the semiconductor substrate 51. 61). At this time, the LDD ion implantation step is ion implantation of n-type impurities, the n-type impurities are arsenic or phosphorus.

As described above, the second doped region 61 formed through the LDD ion implantation is electrically connected to the first doped region 59 in the semiconductor substrate 51, and the first doped region 59 is formed of n-type impurities. Since it is formed by diffusion, the first doped region 59 and the second doped region 61 become doped regions of the same impurity.

Next, an insulating film for spacers is deposited on the entire surface, and then etched back to form a gate spacer 62a in contact with both side walls of the logic gate 60a. Here, gate spacers are formed on both sidewalls of the stacked structure of the lower electrode 55, the dielectric film 56, and the upper electrode 60b formed in a stacked structure at the time of forming the gate spacer 62a, which is called a capacitor spacer 62b. It will be abbreviated.

On the other hand, at one side of the logic gate 60a adjacent to the capacitor, the gate spacer 62a and the capacitor spacer 62b may contact each other, whereby the epi spacer below the portion where the gate spacer 62a and the capacitor spacer 62b contact each other. The surface of the tactic layer 51 may be covered. Therefore, on the other side of the logic gate 60a, the gate insulating layer 58 is etched when the gate spacer 62a is formed to expose the surface of the epitaxial layer 57.

Next, the source / drain ion implantation process is performed to form the third doped region 63. In this case, the third doped region 63 is formed in the semiconductor substrate 51 outside the gate spacer 62a formed on the other side of the logic gate 60a and is electrically connected to the second doped region 61.

Next, the silicide process is performed to form the silicide 64 on the top surface of the logic gate 60a, the top surface of the upper electrode 60b, and the top surface of the third doped region 63.

According to the above-described first and second embodiments, the present invention is reduced by two or more photomask processes, and the memory capacitor process is completed before the logic gate is formed, compared to the process of forming the cylindrical capacitor. Prevents deterioration of logic transistors.                     

Compared to the MOSYS 1T-RAM cell structure having the planar MOS capacitor, the memory cell density can be greatly improved by reducing the unit cell size by replacing the trench type three-dimensional capacitor.

In addition, it is possible to implement a smaller storage node contact, that is, a smaller area SN junction than a stacked capacitor, thereby ensuring better junction leakage characteristics.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

Since the present invention reduces the photomask process, not only can reduce the process period and cost, but also because the memory capacitor process is completed before the logic gate is formed, it is possible to prevent deterioration of the logic transistor by the additional thermal process, which is excellent in reliability. There is an effect that can implement a system-on-chip device.

In addition, since the present invention employs a trench type 3D memory capacitor, it is possible to improve the memory cell density and use it as a base technology for developing a large capacity DRAM (Logic DRAM).

In addition, since the present invention has a smaller SN junction area, it is possible to secure better junction leakage characteristics, that is, excellent refresh characteristics.

Claims (21)

Semiconductor substrates; A device isolation insulating film formed in a predetermined region of the semiconductor substrate and having a trench having a predetermined depth; A capacitor formed in the trench of the device isolation insulating film and having a lower electrode formed over a portion of the surface of the semiconductor substrate, a dielectric film on the lower electrode, and an upper electrode on the dielectric film; A gate of a logic transistor formed on the selected surface of the semiconductor substrate with a gate insulating film interposed therebetween; A first doped region formed in the semiconductor substrate under the lower electrode; A second doped region formed in the semiconductor substrate on both sides of the logic gate and one of which is connected to the first doped region; And A third doped region formed in the semiconductor substrate on the other side of the logic gate and electrically connected to another second doped region System-on-chip device comprising a. The method of claim 1, And one end of the lower electrode extends to a part of the surface of the semiconductor substrate, and the first doped region is in contact with one end of the lower electrode. The method of claim 1, And the upper electrode and the gate are made of the same material. The method of claim 1, And the first to third doped regions are doped with n-type impurities. The method of claim 1, And the dielectric layer and the gate insulating layer are made of the same material. Semiconductor substrates; A device isolation insulating film formed in a predetermined region of the semiconductor substrate and having a trench having a predetermined depth; A sacrificial film formed on the surface of the trench; A capacitor formed on the sacrificial layer above the trench and having a lower electrode formed over a portion of the surface of the semiconductor substrate, a dielectric film on the lower electrode, and an upper electrode on the dielectric film; An epitaxial layer formed on the surface of the semiconductor substrate while filling between the lower electrode and the semiconductor substrate; A gate of a logic transistor formed on the selected surface of the epitaxial layer with a gate insulating film interposed therebetween; A first doped region formed in the epitaxial layer and the semiconductor substrate under the lower electrode; A second doped region formed in the epitaxial layer and the semiconductor substrate on both sides of the logic gate, and one of which is connected to the first doped region; And A third doped region formed in the epitaxial layer and the semiconductor substrate on the other side of the logic gate and electrically connected to the other second doped region System-on-chip device comprising a. The method of claim 6, And one end of the lower electrode extends to a part of the surface of the semiconductor substrate, and the first doped region is in contact with one end of the lower electrode. The method of claim 6, And the upper electrode and the gate are made of the same material. The method of claim 6, And the first to third doped regions are doped with n-type impurities. The method of claim 6, And the dielectric layer and the gate insulating layer are made of the same material. Forming an isolation film in a predetermined region of the semiconductor substrate; Etching the device isolation layer to a predetermined depth to form a trench; Forming a stack of a dielectric layer and a lower electrode of a capacitor that extends to a part of the surface of the semiconductor substrate on the surface of the trench; Forming a first doped region in the semiconductor substrate under the lower electrode while forming a gate insulating film on the surface of the semiconductor substrate; Forming an upper electrode on the dielectric layer while simultaneously forming a gate of a logic transistor on the gate insulating layer; And Forming a second doped region electrically connected to the first doped region in a semiconductor substrate between one side of the gate and the lower electrode; Method for manufacturing a system-on-chip device comprising a. The method of claim 11, And the lower electrode is formed of a polysilicon film doped with n-type impurities. The method of claim 12, And the first doped region is a doped region of n-type impurities formed by diffusion of n-type impurities doped into the polysilicon layer when the gate insulating layer is formed. The method of claim 11, And the dielectric film and the gate insulating film are formed of the same material. The method of claim 14, The dielectric film and the gate insulating film, A method for manufacturing a system-on-chip device, which is formed by an oxide film, a nitride film, a ferroelectric film, or a combination thereof. Forming an isolation film in a predetermined region of the semiconductor substrate; Etching the device isolation layer to a predetermined depth to form a trench; Forming a sacrificial oxide film on the entire surface including the trench; Forming a stack of a dielectric layer and a lower electrode of a capacitor formed on the sacrificial oxide film and extending to a part surface of the semiconductor substrate while being formed in the trench; Selectively removing the sacrificial oxide film between the lower electrode and the semiconductor substrate; Forming an epitaxial layer filling the semiconductor substrate between the lower electrode and the semiconductor substrate; Forming a first doped region in the epitaxial layer under the lower electrode and the semiconductor substrate while forming a gate insulating film on the surface of the epitaxial layer; Forming an upper electrode on the dielectric layer while simultaneously forming a gate of a logic transistor on the gate insulating layer; And Forming an epitaxial layer between one side of the gate and the lower electrode and a second doped region electrically connected to the first doped region in a semiconductor substrate Method for manufacturing a system-on-chip device comprising a. The method of claim 16, And the lower electrode is formed of a polysilicon film doped with n-type impurities. The method of claim 17, And the first doped region is a doped region of n-type impurities formed by diffusion of n-type impurities doped into the polysilicon layer when the gate insulating layer is formed. The method of claim 16, And the dielectric film and the gate insulating film are formed of the same material. The method of claim 19, The dielectric film and the gate insulating film, A method for manufacturing a system-on-chip device, which is formed by an oxide film, a nitride film, a ferroelectric film, or a combination thereof. The method of claim 16, Selectively removing the sacrificial oxide film, A method for manufacturing a system-on-chip device, characterized in that it proceeds by anisotropic wet etching.

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