TWI803217B - Memory device having word lines with reduced leakage - Google Patents

Abstract

The present application provides a memory device having several word lines (WL) with reduced leakage and a manufacturing method of the memory device. The memory device includes a semiconductor substrate defined with an active area and including a recess extending into the semiconductor substrate; and a word line disposed within the recess, wherein the word line includes an insulating layer disposed within the recess, a conductive layer surrounded by the insulating layer, and a conductive member enclosed by the conductive layer, and the insulating layer includes a lining portion conformal to the recess and a protruding portion disposed above the conductive layer. A method of manufacturing the memory device is also disclosed.

Description

Memory element with wordlines for reduced leakage

This application claims priority to US Patent Application Nos. 17/552,882 and 17/552,736 (ie, the priority date is "December 16, 2021"), the contents of which are incorporated herein by reference in their entirety.

The disclosure relates to a memory device and a manufacturing method thereof, in particular to a memory device having word lines with reduced leakage and a manufacturing method thereof.

Dynamic Random Access Memory (DRAM) is a semiconductor configuration used to store data bits in individual capacitors within an integrated circuit (IC). DRAMs are typically formed as trench capacitive DRAM cells. An advanced approach to fabricating buried gate electrodes involves building the gates of transistors and wordlines in trenches that include active areas (AA) of shallow trench isolation (STI) structures.

Over the past few decades, as semiconductor manufacturing technology has continued to improve, the size of electronic components has shrunk accordingly. When the size of a unit transistor is reduced to a length of several nanometers, current leakage may occur. And the leakage current may cause the performance of the unit transistor to be greatly degraded. Accordingly, it is desirable to develop improvements that address related manufacturing challenges.

The above "prior art" description is only to provide background technology, and does not admit that the above "prior art" description discloses the subject of this disclosure, and does not constitute the prior art of this disclosure, and Any description of the "prior art" above should not be taken as part of this case.

An embodiment of the disclosure provides a memory device. The memory element includes a semiconductor substrate, which defines an active area and includes a groove extending into the semiconductor substrate; and a word line arranged in the groove, wherein the word line includes an An insulating layer in the groove, a conductive layer surrounded by the insulating layer, and a conductive member surrounded by the conductive layer, and the insulating layer includes a liner portion conformal to the groove and disposed on the conductive layer a protruding part above.

In some embodiments, a top surface of the liner portion and a top surface of the protruding portion are exposed through the semiconductor substrate.

In some embodiments, the protrusion contacts a top surface of the conductive layer.

In some embodiments, the protruding portion is disposed over the conductive member.

In some embodiments, the liner portion and the protruding portion comprise a same material.

In some embodiments, the liner portion and the protruding portion are integrally formed.

In some embodiments, the insulating layer includes oxide.

In some embodiments, the conductive layer includes titanium nitride (TiN).

In some embodiments, the conductive member includes tungsten (W).

In some embodiments, the word line includes a work function member disposed over the conductive layer and the conduction member, and a gate insulation member disposed over the work function member.

In some embodiments, the work function member and the gate insulating member are surrounded by the insulating layer.

In some embodiments, the work function member and the gate insulation member are in contact with the protruding portion.

In some embodiments, a total width of the conductive layer and the conductive member is substantially equal to a total width of the protruding portion and the work function member.

In some embodiments, a total width of the conductive layer and the conductive member is substantially equal to a total width of the protruding portion and the gate insulating member.

In some embodiments, the work function component includes polysilicon.

In some embodiments, the gate insulating member includes nitride.

Another embodiment of the disclosure provides a memory device. The memory element includes a semiconductor substrate defining an active area and including a first groove extending into the semiconductor substrate; and a word line disposed in the first groove, wherein the word line includes a first insulating layer disposed in the first groove, a first conductive layer surrounded by the first insulating layer, and a first conductive member surrounded by the first conductive layer, and the first insulating layer at least partially disposed on the first conductive layer.

In some embodiments, the first insulating layer is in contact with a top surface of the first conductive layer.

In some embodiments, a width of the first insulating layer above the first conductive layer is substantially greater than a width of the first conductive layer and the first insulating layer around the first conductive member.

In some embodiments, the memory device further includes an isolation structure adjacent to the word line and extending into the semiconductor substrate, a second conductive layer surrounded by the isolation structure, and surrounded by the second conductive layer A second conductive member.

In some embodiments, a width of the isolation structure above the second conductive layer The width is substantially greater than a width of the isolation structure surrounding the second conductive layer and the second conductive member.

In some embodiments, the second conductive layer includes titanium nitride (TiN).

In some embodiments, the second conductive member includes tungsten (W).

In some embodiments, the first conductive layer and the second conductive layer include a same material.

In some embodiments, the first conductive member and the second conductive member comprise a same material.

Another embodiment of the disclosure provides a method for manufacturing a memory device. The preparation method includes the following steps: providing a semiconductor substrate, which defines an active region and includes an isolation layer surrounding the active region; forming a first groove extending into the semiconductor substrate and passing through the active region; A first liner portion of a first insulating layer conformal to the first recess; conformally disposing a first conductive material to the first liner portion; forming a first conductive layer surrounded by the first conductive material member; a second conductive material is disposed over the first conductive member to form a first conductive layer surrounding the first conductive member; and the first conductive layer is formed on the first conductive layer and the first conductive member A first protruding portion of the insulating layer.

In some embodiments, the formation of the first liner portion is performed before the formation of the first protruding portion.

In some embodiments, the manufacturing method further includes removing a portion of the first conductive material disposed on the first conductive member after the second conductive material is disposed.

In some embodiments, forming the first protruding portion includes disposing an insulating material over the semiconductor substrate, the first liner portion, the first conductive layer, and the first conductive member.

In some embodiments, the insulating material is deposited by atomic layer deposition (ALD).

In some embodiments, forming the first protruding portion includes removing a portion of the insulating material disposed over the semiconductor substrate and the first liner portion.

In some embodiments, the portion of the insulating material is removed by anisotropic etching.

In some embodiments, the manufacturing method further includes forming a second groove extending to the spacer to form a second liner portion of an isolation structure; forming a second liner portion surrounded by the second liner portion. a conductive layer; forming a second conductive member surrounded by the second conductive layer; and forming a second protruding portion of the isolation structure on the second conductive layer and the second conductive member.

In some embodiments, the first protruding portion and the second protruding portion are formed simultaneously.

In some embodiments, the manufacturing method further includes forming a first work function member over the first conductive layer and surrounded by the first protruding portion; and forming a first gate insulating member over the first work function member. member and is surrounded by the first protruding portion.

In conclusion, since the insulating layer surrounding the word line of the work function member has a greater thickness than the insulating layer surrounding the conductive member under the work function member, gate induced drain leakage (GIDL) can be suppressed. In addition, the insulating layer surrounding the conductive member has a smaller thickness, so that the operation control of the word line can be improved. Therefore, the performance of the memory device and the manufacturing process of the memory device are improved.

The technical features and advantages of the present disclosure have been broadly summarized above, so that the following detailed description of the present disclosure can be better understood. The subject matter of the scope of patent application constituting this disclosure Other technical features and advantages will be described below. Those skilled in the art of the present disclosure should understand that the concepts and specific embodiments disclosed below can be easily used to modify or design other structures or processes to achieve the same purpose as the present disclosure. Those with ordinary knowledge in the technical field to which the disclosure belongs should also understand that such equivalent constructions cannot depart from the spirit and scope of the disclosure defined by the appended claims.

100: memory components

101:Semiconductor substrate

101a: Active area

101b: first surface

101c: Second Surface

102: Isolation structure

102a: second liner part

102b: Second protrusion

102c: top surface

102d: top surface

102e: isolation layer

103: Groove

103a: groove (first groove)

103b: second groove

104: The first insulating layer

104a: first lining part

104b: first protrusion

104c: top surface

104d: top surface

105: the first conductive layer

105a: top surface

105b: first conductive material

105c: fifth conductive material

106: the second conductive layer

106a: top surface

106b: second conductive material

106c: The sixth conductive material

107: first conductive member

107a: third conductive material

108: second conductive member

108a: fourth conductive material

111: The first work function component

111a: First work function material

112: Second work function component

112a: First work function material

113: the first gate insulating member

114: second gate insulating member

120: character line

124: insulating material

125: Conductive material

200: memory components

A-A': line

B-B': line

S300: Preparation method

S301: step

S302: step

S303: step

S304: step

S305: step

S306: step

S307: step

W1: total width

W2: total width

W3: width

W4: width

W5: width

W6: width

The disclosure content of the present application can be understood more comprehensively when referring to the embodiments and the patent scope of the application for combined consideration of the drawings, and the same reference numerals in the drawings refer to the same components.

FIG. 1 is a cross-sectional side view illustrating a memory device according to some embodiments of the present disclosure.

FIG. 2 is a cross-sectional side view illustrating a memory device according to another embodiment of the present disclosure.

FIG. 3 is a flowchart illustrating a method for fabricating a memory device according to some embodiments of the present disclosure.

4-20 are cross-sectional views illustrating intermediate stages in the formation of memory devices according to some embodiments of the present disclosure.

The following disclosure provides many different embodiments, or examples, for implementing different features of the presented subject matter. To simplify the present disclosure, specific examples of components and arrangements are described below. Of course, these are examples only and are not meant to be limiting. For example, in the description that follows, the formation of a first feature on a second feature may include an embodiment where the first and second features are in direct contact, or may include an embodiment where an additional feature is formed between the first and second features For example, such that the first and second features may not be in direct contact.

In addition, the present disclosure may repeat reference numerals and/or letters in various embodiments. This repetition is for clarity and does not in itself determine the relationship between the various embodiments and/or arrangements discussed.

In addition, spatially relative terms, such as "below", "under", "under", "upper", "above", "above", etc., may be used herein to describe an element or feature as compared to that in the drawings for ease of description. relationship to another element or feature shown. Spatially relative terms are intended to encompass different orientations of elements in use or operation, as well as the orientation depicted in the figures. The element may be otherwise oriented (rotated 90 degrees or otherwise) and the spatially relative descriptors used herein interpreted accordingly.

FIG. 1 is a cross-sectional side view illustrating a memory device 100 according to some embodiments of the present disclosure. In some embodiments, the memory device 100 includes some unit cells arranged in rows and columns.

In some embodiments, the memory device 100 includes a semiconductor substrate 101 . In some embodiments, the semiconductor substrate 101 includes semiconductor materials such as silicon, germanium, gallium, arsenic, or combinations thereof. In some embodiments, the semiconductor substrate 101 includes bulk semiconductor material. In some embodiments, the semiconductor substrate 101 is a semiconductor wafer (eg, a silicon wafer) or a semiconductor-on-insulator (SOI) wafer (eg, a silicon-on-insulator wafer) . In some embodiments, the semiconductor substrate 101 is a silicon substrate. In some embodiments, the semiconductor substrate 101 includes lightly doped single crystal silicon. In some embodiments, the semiconductor substrate 101 is a p-type substrate.

In some embodiments, the semiconductor substrate 101 includes a plurality of active areas (active areas, AA) 101a. The active region 101 a is a doped region in the semiconductor substrate 101 . In some embodiments, the active region 101 a extends horizontally above or below a top surface of the semiconductor substrate 101 . In some embodiments, each active region 101a includes a same type of dopant. In some embodiments, each active region 101a includes a different type of dopant than the type of dopant included in the other active regions 101a. In some embodiments, each active region 101a has a same conductivity type type. In some embodiments, the active region 101a includes an N-type dopant.

In some embodiments, the semiconductor substrate 101 includes a first surface 101b and a second surface 101c opposite to the first surface 101b. In some embodiments, the first surface 101b is a front surface of the semiconductor substrate 101 , wherein electronic components or components are subsequently formed on the first surface 101b and configured to be electrically connected to external circuits. In some embodiments, the second surface 101c is a back surface of the semiconductor substrate 101 where there are no electronic components or components.

In some embodiments, the semiconductor substrate 101 includes a groove 103 a extending to the semiconductor substrate 101 . In some embodiments, the groove 103 a extends from the first surface 101 b to the second surface 101 c of the semiconductor substrate 101 . In some embodiments, the groove 103 a tapers gradually from the first surface 101 b to the second surface 101 c of the semiconductor substrate 101 . In some embodiments, a depth of the groove 103a is substantially greater than a depth of the active region 101a.

In some embodiments, the memory device 100 includes a word line 120 disposed in the groove 103a. In some embodiments, the word line 120 includes a first insulating layer 104 , a first conductive layer 105 and a first conductive member 107 . In some embodiments, the first insulating layer 104 conforms to and is disposed in the groove 103a. In some embodiments, the first conductive layer 105 is surrounded by the first insulating layer 104 . In some embodiments, the first conductive member 107 is surrounded by the first conductive layer 105 .

In some embodiments, the first insulating layer 104 is disposed along the entire sidewall of the groove 103a. In some embodiments, the first insulating layer 104 includes a dielectric material, such as oxide. In some embodiments, the fabrication technology of the first insulating layer 104 is an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, etc., or a combination thereof. In some embodiments, the first insulating layer 104 includes an insulating material having a low dielectric constant (low-k).

In some embodiments, the first insulating layer 104 includes a conformal The first liner portion 104 a and the first protruding portion 104 b disposed on the first conductive layer 105 . In some embodiments, the first liner portion 104a is disposed along the entire sidewall of the groove 103a. In some embodiments, the first liner portion 104a is coupled with the first protruding portion 104b. In some embodiments, the first protruding portion 104b protrudes from the first liner portion 104a.

In some embodiments, the thickness of the first protruding portion 104b is in the range of about 2 microns to about 3 microns. In some embodiments, the first protruding portion 104b includes a low-K dielectric material. In some embodiments, the first liner portion 104a is in the range of approximately 4 microns to 6 microns. In some embodiments, a thickness of the first liner portion 104a is substantially greater than a thickness of the first protruding portion 104b.

In some embodiments, a top surface 104c of the first liner portion 104a and a top surface 104d of the first protruding portion 104b are exposed through the semiconductor substrate 101 . In some embodiments, the first liner portion 104a and the first protruding portion 104b comprise a same material or a different material. In some embodiments, the first liner portion 104a and the first protruding portion 104b are integrally formed.

In some embodiments, the first conductive layer 105 is disposed in the groove 103 a and surrounded by the first insulating layer 104 . In some embodiments, the first conductive layer 105 is surrounded by the first liner portion 104a and disposed under the first protruding portion 104b. In some embodiments, the top surface 105a of the first conductive layer 105 is in contact with the first protruding portion 104b. In some embodiments, the top surface 105a of the first conductive layer 105 is substantially lower than the top surface 104c of the first liner portion 104a and the top surface 104d of the first protruding portion 104b. In some embodiments, the first conductive layer 105 includes a conductive material, such as titanium nitride (TiN).

In some embodiments, the first conductive member 107 is disposed within the first conductive layer 105 . The first conductive member 107 is surrounded by the first liner portion 104a. In some embodiments, The first conductive member 107 is disposed under the active region 101 a of the semiconductor substrate 101 . In some embodiments, the first protruding portion 104b is disposed on the first conductive member 107 . In some embodiments, the first conductive member 107 includes a conductive material, such as tungsten (W).

In some embodiments, the word line 120 further includes a first work function member 111 disposed above the first conductive layer 105 and the first conductive member 107 , and a first gate insulating member disposed above the first work function member 111 Member 113. In some embodiments, the first work function member 111 and the first gate insulating member 113 are surrounded by the first insulating layer 104 . In some embodiments, the first work function member 111 and the first gate insulating member 113 are surrounded by and in contact with the first protruding portion 104b. In some embodiments, the first work function component 111 is in contact with the top surface 105 a of the first conductive layer 105 .

In some embodiments, the total width W1 of the first conductive layer 105 and the first conductive member 107 is substantially equal to the total width W2 of the first protruding portion 104 b and the first work function member 111 . In some embodiments, the total width W1 is substantially equal to the total width W2 of the first protruding portion 104 b and the first gate insulating member 113 . In some embodiments, the first work function component 111 includes polysilicon or polycrystalline silicon. In some embodiments, the first work function component 111 has a low work function. In some embodiments, the first work function component 111 has dual work functions, including metal and polysilicon. In some embodiments, the first work function component 111 is used as a gate electrode.

In some embodiments, the first gate insulating member 113 includes a dielectric material, such as nitride. In some embodiments, the first gate insulating member 113 serves as a gate dielectric. In some embodiments, a top surface of the first gate insulating member 113 is substantially coplanar with the top surface 104c of the first liner portion 104a and the top surface 104d of the first protruding portion 104b.

In some embodiments, the memory device 100 further includes adjacent word lines 120 isolation structure 102 . In some embodiments, the isolation structure 102 extends into the semiconductor substrate 101 from the first surface 101b to the second surface 101c. In some embodiments, the isolation structure 102 is a shallow trench isolation (STI). In some embodiments, the isolation structure 102 defines a boundary of the active region 101a.

In some embodiments, the isolation structure 102 includes a second liner portion 102a and a second protrusion portion 102b protruding laterally from the second liner portion 102a. In some embodiments, the thickness of the second protruding portion 102b is in the range of about 2 microns to about 3 microns. In some embodiments, the second liner portion 102a and the second protrusion portion 102b comprise a same material or a different material. In some embodiments, the second liner portion 102a and the second protrusion portion 102b are integrally formed.

In some embodiments, the fabrication technology of the isolation structure 102 is an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, etc., or a combination thereof. In some embodiments, the isolation structure 102 and the first insulating layer 104 include a same material or a different material. In some embodiments, a width of the isolation structure 102 is substantially greater than a width of the word line 120 . In some embodiments, a depth of the isolation structure 102 is substantially greater than a depth of the word line 120 .

In some embodiments, the second conductive layer 106 and the second conductive member 108 are surrounded by the second liner portion 102 a of the isolation structure 102 . In some embodiments, the second conductive member 108 is surrounded by the second conductive layer 106 . In some embodiments, the second conductive layer 106 and the second conductive member 108 are disposed under the second protruding portion 102b. In some embodiments, the second protruding portion 102b is in contact with the second conductive layer 106 .

In some embodiments, the second conductive layer 106 includes a conductive material, such as titanium nitride (TiN). In some embodiments, the second conductive member 108 includes a conductive material, such as tungsten (W). In some embodiments, the first conductive layer 105 and the second conductive layer 106 comprise the same material or a different material. In some embodiments, the first conductive member 107 and the second conductive member 108 include a same material or a different material.

In some embodiments, a second work function member 112 is disposed over the second conductive layer 106 and the second conductive member 108 , and a second gate insulating member 114 is disposed over the second work function member 112 . In some embodiments, the second work function member 112 and the second gate insulating member 114 are surrounded by the isolation structure 102 . In some embodiments, the second work function member 112 and the second gate insulating member 114 are surrounded by and in contact with the second protruding portion 102b. In some embodiments, the second work function component 112 is in contact with the top surface 106 a of the second conductive layer 106 .

In some embodiments, the second work function component 112 includes polysilicon or polysilicon. In some embodiments, the second work function component 112 has a low work function. In some embodiments, the second work function component 112 has a dual work function, including metal and polysilicon. In some embodiments, the second gate insulating member 114 includes a dielectric material, such as nitride.

In some embodiments, the first work function component 111 and the second work function component 112 comprise a same material or a different material. In some embodiments, the first gate insulating member 113 and the second gate insulating member 114 include a same material or a different material. In some embodiments, a top surface of the second gate insulating member 114 is substantially coplanar with the top surface 102c of the second liner portion 102a and the top surface 102d of the second protruding portion 102b.

Since the upper part of the first insulating layer 104 (surrounding the word line 120 of the first work function member 111) and the lower part of the first insulating layer 104 (surrounding the first conductive layer 105 and the first conductive member below the first work function member 111 107 ) has a larger thickness than that, and thus can suppress gate-induced drain leakage (GIDL). In addition, the first insulating layer 104 surrounding the first conductive layer 105 and the first conductive member 107 has a smaller thickness, and thus operation control over the word line 120 may be improved. Therefore, the performance of the memory device 100 can be improved. good.

FIG. 2 is a cross-sectional side view illustrating a memory device 200 according to some embodiments of the present disclosure. The memory device 200 is similar to the memory device 100 except that there is no interface between the first insulating layer 104 and the isolation structure 102 in FIG. 2 . In other words, the first liner portion 104 a and the first protruding portion 104 b shown in FIG. 1 are integrally formed to become the first insulating layer 104 and the isolation structure 102 shown in FIG. 2 , respectively. In some embodiments, the first insulating layer 104 is at least partially disposed over the first conductive layer 105 .

In some embodiments, the width W3 of the first insulating layer 104 over the first conductive layer 105 is substantially greater than the width W4 of the first insulating layer 104 around the first conductive layer 105 and the first conductive member 107 . In some embodiments, the width W5 of the isolation structure 102 above the second conductive layer 106 is substantially greater than the width W6 of the isolation structure 102 around the second conductive layer 106 and the second conductive member 108 .

3 is a flow chart illustrating the method S300 for manufacturing the memory device 100 or 200 of some embodiments of the present disclosure, and FIGS. 4 to 20 are cross-sectional views illustrating intermediate stages of forming the memory device 100 or 200 of some embodiments of the present disclosure.

The stages illustrated in FIGS. 4 to 20 are also illustrated in the flowchart of FIG. 3 . In the following discussion, the fabrication stages illustrated in FIGS. 4-20 are discussed with reference to the process steps of FIG. 3 . The preparation method S300 includes some operations, and the description and illustration are not intended to limit the sequence of operations. The preparation method S300 includes some steps (S301, S302, S303, S304, S305, S306 and S307).

Referring to FIGS. 4 and 5 , a semiconductor substrate 101 is provided according to step S301 in FIG. 3 . FIG. 4 is a cross-sectional top view illustrating the semiconductor substrate 101 , and FIG. 5 is a cross-sectional view illustrating the semiconductor substrate 101 taken along line AA' in FIG. 4 . In some embodiments, the semiconductor substrate 101 is determined defined to have an active region 101a and include an isolation layer 102e surrounding the active region 101a. In some embodiments, the isolation layer 102e extends from the first surface 101b to the second surface 101c of the semiconductor substrate 101 . In some embodiments, the isolation layer 102e includes a dielectric material, such as oxide or the like.

Referring to FIGS. 6 and 7 , according to step S302 in FIG. 3 , a first groove 103 a extending to the semiconductor substrate 101 is formed. FIG. 6 is a top cross-sectional view illustrating the semiconductor substrate 101 , and FIG. 7 is a cross-sectional view illustrating the semiconductor substrate 101 taken along line BB' in FIG. 6 . In some embodiments, some trenches 103 are formed on the first surface 101 b of the semiconductor substrate 101 . The trench 103 extends through the active region 101 a or the isolation layer 102 e (as shown in FIGS. 4 and 5 ).

In some embodiments, the formation of the trench 103 includes the formation of the first groove 103a and the formation of the second groove 103b. In some embodiments, the formation of the first groove 103a and the formation of the second groove 103b are performed separately or simultaneously. In some embodiments, the formation of the first groove 103 a includes removing some portions of the semiconductor substrate 101 . In some embodiments, the formation of the second groove 103b includes removing some portions of the isolation layer 102e.

In some embodiments, the first groove 103a extends through the active region 101a, and the second groove 103b extends through the isolation layer 102e. In some embodiments, the first groove 103 a and the second groove 103 b extend from the first surface 101 b to the second surface 101 c of the semiconductor substrate 101 . In some embodiments, the second liner portion 102a is formed after the second groove 103b is formed.

Referring to FIG. 8, according to step S303 in FIG. 3, the first liner portion 104a of the first insulating layer 104 conformal to the first groove 103a is formed. In some embodiments, the first liner portion 104a is disposed within the first groove 103a. In some embodiments, the first liner portion 104a is formed by deposition, oxidation, or any other suitable process. In some embodiments, the first liner portion 104a includes an oxide.

Referring to FIGS. 9 and 10 , according to step S304 in FIG. 3 , a first conductive material 105b conformal to the first liner portion 104a is provided. In some embodiments, as shown in FIG. 9, a conductive material 125 is disposed above the semiconductor substrate 101 and surrounded by the first liner portion 104a and the second liner portion 102a, and then some portions of the conductive material 125 are removed to form The first conductive material 105b and the second conductive material 106b are shown in FIG. 10 .

In some embodiments, the first conductive material 105b and the second conductive material 106b are disposed separately or simultaneously by deposition or any other suitable process. In some embodiments, the first conductive material 105b and the second conductive material 106b include titanium nitride (TiN). In some embodiments, the first conductive material 105b and the second conductive material 106b conform to the first liner portion 104a and the second liner portion 102a, respectively.

11 and 12, according to step S305 in FIG. 3, the first conductive member 107 surrounded by the first conductive material 105b is formed. The first conductive member 107 is disposed in the first groove 103a and surrounded by the first liner portion 104a and the first conductive material 105b. In some embodiments, the first conductive member 107 is formed by disposing a third conductive material 107a surrounded by the first conductive material 105b, as shown in FIG. The conductive member 107 is shown in FIG. 12 .

In some embodiments, the third conductive material 107a is provided by deposition or any other suitable process. In some embodiments, the portion of the third conductive material 107a is removed by etching or any other suitable process. In some embodiments, the third conductive material 107a includes tungsten (W).

In some embodiments, a second conductive member 108 surrounded by a second conductive material 106b is also formed. The second conductive member 108 is disposed in the second groove 103b and surrounded by the second liner portion 102a and the second conductive material 106b. In some embodiments, the second conductive member 108 It is formed by disposing a fourth conductive material 108a surrounded by a second conductive material 106b, as shown in FIG. 11 , and then removing a part of the fourth conductive material 108a to become a second conductive member 108, as shown in FIG. 12 .

In some embodiments, the fourth conductive material 108a is provided by deposition or any other suitable process. In some embodiments, the portion of the fourth conductive material 108a is removed by etching or any other suitable process. In some embodiments, the fourth conductive material 108a includes tungsten (W). In some embodiments, the formation of the first conductive member 107 and the formation of the second conductive member 108 are performed separately or simultaneously.

13 and 14, according to step S306 in FIG. In some embodiments, the fifth conductive material 105c is disposed on the first conductive member 107 by deposition or any other suitable process. In some embodiments, the fifth conductive material 105c and the first conductive material 105b are the same material. In some embodiments, the fifth conductive material 105c includes titanium nitride (TiN).

In some embodiments, after disposing the fifth conductive material 105c as shown in FIG. 13 , a portion of the first conductive material 105b is removed to form the first conductive layer 105 as shown in FIG. 14 . In some embodiments, the portion of the first conductive material 105b is removed by etching, cleaning, or any other suitable process.

In some embodiments, the sixth conductive material 106c is disposed on the second conductive member 108 by deposition or any other suitable process. In some embodiments, the sixth conductive material 106c and the second conductive material 106b are the same material. In some embodiments, the sixth conductive material 106c includes titanium nitride (TiN). In some embodiments, the first conductive material 105b, the fifth conductive material 105c, the second conductive material 106b, and the sixth conductive material 106c are the same material. In some embodiments, the disposing of the fifth conductive material 105c and the disposing of the sixth conductive material 106c are performed separately or simultaneously.

In some embodiments, after disposing the sixth conductive material 106c as shown in FIG. 13 , a portion of the second conductive material 106b is removed to form the second conductive layer 106 as shown in FIG. 14 . In some embodiments, the portion of the second conductive material 106b is removed by etching, cleaning, or any other suitable process. In some embodiments, the removal of the portion of the first conductive material 105b and the removal of the portion of the second conductive material 106b are performed separately or simultaneously.

15 and 16, according to step S307 in FIG. 3, the first protruding portion 104b of the first insulating layer 104 over the first conductive layer 105 and the first conductive member 107 is formed. In some embodiments, forming the first protruding portion 104b includes disposing an insulating material 124 over the semiconductor substrate 101 , the first liner portion 104a , the first conductive layer 105 and the first conductive member 107 . In some embodiments, insulating material 124 is deposited by atomic layer deposition (ALD) or any other suitable process.

In some embodiments, after disposing the insulating material 124 as shown in FIG. 15 , a portion of the insulating material 124 disposed over the semiconductor substrate 101 and the first liner portion 104 a is removed to form the first protruding portion 104 b. In some embodiments, the portion of insulating material 124 is removed by anisotropic etching, planarization, or any other suitable process. The first protruding portion 104b is disposed on the first conductive layer 105 and on the first conductive member 107 .

In some embodiments, a second protruding portion 102 b of the isolation structure 102 over the second conductive layer 106 and the second conductive member 108 is also formed. In some embodiments, forming the second protruding portion 102b includes disposing an insulating material 124 over the semiconductor substrate 101, the second liner portion 102a, the second conductive layer 106, and the second conductive member 108, as shown in FIG. 15 , A portion of the insulating material 124 disposed over the semiconductor substrate 101 and the second liner portion 102a is then removed. points to form the second protruding portion 102b, as shown in FIG. 16 . The second protruding portion 102b is disposed on the second conductive layer 106 and above the second conductive member 108 . In some embodiments, the forming of the first protruding portion 104b and the forming of the second protruding portion 102b are performed separately or simultaneously.

Referring to FIGS. 17 and 18 , a first work function member 111 is formed over the first conductive layer 105 and surrounded by the first protruding portion 104 b. In some embodiments, as shown in FIG. 17, the first work function member 111 is formed by disposing a first work function material 111a surrounded by the first protruding portion 104b, and then removing a part of the first work function material 111a to form The first work function component 111 shown in FIG. 18 . In some embodiments, the first work function material 111a is provided by deposition, CVD, or any other suitable process. In some embodiments, the portion of the first work function material 111a is removed by etching or any other suitable process.

In some embodiments, the second work function member 112 is formed by disposing a second work function material 112a surrounded by the second protruding portion 102b, as shown in FIG. 17, and then removing a portion of the second work function material 112a to A second work function component 112 is formed, as shown in FIG. 18 . In some embodiments, the second work function material 112a is deposited by deposition, CVD, or any other suitable process. In some embodiments, the portion of the second work function material 112a is removed by etching or any other suitable process.

In some embodiments, the disposition of the first work function material 111a and the disposition of the second work function material 112a are performed separately or simultaneously. In some embodiments, the first work function material 111a and the second work function material 112a are the same material. In some embodiments, the first work function material 111a and the second work function material 112a include polysilicon.

Referring to FIG. 19 , a first gate insulating member 113 is formed over the first work function member 111 and surrounded by the first protruding portion 104b. In some embodiments, the formation of the first gate insulating member 113 includes disposing a gate insulating material by deposition or any other suitable process. material. In some embodiments, the second gate insulating member 114 is formed over the second work function member 112 and surrounded by the second protruding portion 102b. In some embodiments, the formation of the first gate insulating member 113 and the formation of the second gate insulating member 114 are performed separately or simultaneously. In some embodiments, the memory device 100 of FIG. 1 is formed as shown in FIG. 19 . In some embodiments, the memory device 200 of FIG. 2 is formed as shown in FIG. 20 .

An embodiment of the present disclosure provides a memory device. The memory element includes a semiconductor substrate, which defines an active area and includes a groove extending into the semiconductor substrate; and a word line arranged in the groove, wherein the word line includes an An insulating layer in the groove, a conductive layer surrounded by the insulating layer, and a conductive member surrounded by the conductive layer, and the insulating layer includes a liner portion conformal to the groove and disposed on the conductive layer a protruding part above.

Another embodiment of the present disclosure provides a memory device. The memory element includes a semiconductor substrate defining an active area and including a first groove extending into the semiconductor substrate; and a word line disposed in the first groove, wherein the word line includes a first insulating layer disposed in the first groove, a first conductive layer surrounded by the first insulating layer, and a first conductive member surrounded by the first conductive layer, and the first insulating layer at least partially disposed on the first conductive layer.

Another embodiment of the present disclosure provides a method for manufacturing a memory device. The preparation method includes the following steps: providing a semiconductor substrate, which defines an active region and includes an isolation layer surrounding the active region; forming a first groove extending into the semiconductor substrate and passing through the active region; A first liner portion of a first insulating layer conformal to the first recess; conformally disposing a first conductive material to the first liner portion; forming a first conductive layer surrounded by the first conductive material member; a second conductive material is disposed above the first conductive member, forming a first conductive layer surrounding the first conductive member; and forming a first protruding portion of the first insulating layer on the first conductive layer and the first conductive member.

In conclusion, since the insulating layer surrounding the word line of the work function member has a greater thickness than the insulating layer surrounding the conductive member under the work function member, gate induced drain leakage (GIDL) can be suppressed. In addition, the insulating layer surrounding the conductive member has a smaller thickness, so that the operation control of the word line can be improved. Therefore, the performance of the memory device and the manufacturing process of the memory device are improved. Although the present disclosure and its advantages have been described in detail, it should be understood that other changes, substitutions and substitutions can be made hereto without departing from the spirit and scope of the present disclosure as defined by the patent claims disclosed. For example, many of the processes described above can be performed in different ways and replaced by other processes or combinations thereof.

Furthermore, the scope of the disclosure is not limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. Those skilled in the art can understand from the disclosure content of this disclosure that they can use existing or future developed processes, machinery, manufacturing, A composition of matter, means, method, or step. Accordingly, such processes, machinery, manufacture, material composition, means, methods, or steps are included in the scope of the patent disclosure of this disclosure.

100: memory components

101:Semiconductor substrate

101a: Active area

101b: first surface

101c: Second Surface

102: Isolation structure

102a: second liner part

102b: Second protrusion

102c: top surface

102d: top surface

103a: groove (first groove)

104: The first insulating layer

104a: first lining part

104b: first protrusion

104c: top surface

104d: top surface

105: the first conductive layer

105a: top surface

106: the second conductive layer

106a: top surface

107: first conductive member

108: second conductive member

111: The first work function component

112: Second work function component

113: the first gate insulating member

114: second gate insulating member

120: character line

W1: total width

W2: total width

Claims (39)

A memory element, comprising: a semiconductor substrate, which defines an active area and includes a groove extending into the semiconductor substrate; and a word line, arranged in the groove; wherein the word line includes an An insulating layer within the groove, a conductive layer surrounded by the insulating layer, and a conductive member surrounded by the conductive layer, and the insulating layer includes a liner portion conformal to the groove and disposed on the A protruding portion above a conductive layer. The memory device as claimed in claim 1, wherein a top surface of the liner portion and a top surface of the protruding portion are exposed through the semiconductor substrate. The memory device as claimed in claim 1, wherein the protruding portion is in contact with a top surface of the conductive layer. The memory device as claimed in claim 1, wherein the protruding portion is disposed on the conductive member. The memory device of claim 1, wherein the liner portion and the protrusion portion are integrally formed, and the liner portion and the protrusion portion comprise a same material. The memory device as claimed in claim 1, wherein the insulating layer comprises oxide. The memory element as claimed in claim 1, wherein the conductive layer includes titanium nitride (TiN) or the conductive member includes tungsten (W). The memory device as claimed in claim 1, wherein the word line includes a work function member disposed above the conductive layer and the conduction member, and a gate insulating member disposed above the work function member. The memory element as claimed in claim 8, wherein the work function member and the gate insulating member are surrounded by the insulating layer. The memory element as claimed in claim 8, wherein the work function member and the gate insulating member are in contact with the protruding portion. The memory device as claimed in claim 8, wherein a total width of the conductive layer and the conductive member is substantially equal to a total width of the protruding portion and the work function member. The memory device as claimed in claim 8, wherein a total width of the conductive layer and the conductive member is substantially equal to a total width of the protruding portion and the gate insulating member. The memory device as claimed in claim 8, wherein the work function component comprises polysilicon, and the gate insulating component comprises nitride. A memory element, comprising: a semiconductor substrate defining an active area and including a first groove extending into the semiconductor substrate; and a word line disposed in the first groove; wherein the word The line includes a first insulating layer disposed in the first groove, a first conductive layer surrounded by the first insulating layer, and a first conductive member surrounded by the first conductive layer, and the first The insulating layer is at least partially disposed on the first conductive layer; wherein the first insulating layer is in contact with a top surface of the first conductive layer. The memory element as claimed in claim 14, wherein a width of the first insulating layer above the first conductive layer is substantially greater than that of the first conductive layer and the first insulating layer around the first conductive member a width. The memory device as claimed in claim 14, further comprising an isolation structure adjacent to the word line and extending into the semiconductor substrate, a second conductive layer surrounded by the isolation structure, and a second conductive layer formed by the second conductive layer. A second conductive member surrounded by layers. The memory device as claimed in claim 16, wherein a width of the isolation structure above the second conductive layer is substantially larger than a width of the isolation structure surrounding the second conductive layer and the second conductive member. The memory device as claimed in claim 16, wherein the second conductive layer comprises titanium nitride (TiN) or tungsten (W). The memory device of claim 16, wherein the first conductive layer and the second conductive layer comprise a same material. A method for manufacturing a memory element, comprising: providing a semiconductor substrate, which defines an active region and includes an isolation layer surrounding the active region; forming a first groove extending into the semiconductor substrate and passing through the active region forming a first liner portion of a first insulating layer conformal to the first recess; conformally disposing a first conductive material to the first liner portion; A first conductive member; a second conductive material is disposed above the first conductive member to form a first conductive layer surrounding the first conductive member; and on the first conductive layer and the first conductive member A first protruding portion of the first insulating layer is formed. The manufacturing method as claimed in claim 20, wherein the forming of the first lining portion is performed before the forming of the first protruding portion. The manufacturing method as claimed in claim 20 further includes removing a part of the first conductive material disposed on the first conductive member after the second conductive material is disposed. The manufacturing method as claimed in claim 20, wherein forming the first protruding portion includes disposing an insulating material over the semiconductor substrate, the first liner portion, the first conductive layer, and the first conductive member. The method of claim 23, wherein the insulating material is deposited by atomic layer deposition (ALD). The manufacturing method as claimed in claim 23, wherein the forming of the first protruding portion includes removing a portion of the insulating material disposed over the semiconductor substrate and the first pad portion. The manufacturing method as claimed in claim 25, wherein the portion of the insulating material is removed by anisotropic etching. The manufacturing method as claimed in claim 20, further comprising: forming a second groove extending into the isolation layer to form a second liner portion of an isolation structure; forming a portion surrounded by the second liner a second conductive layer; forming a second conductive member surrounded by the second conductive layer; and forming a second protruding portion of the isolation structure on the second conductive layer and the second conductive member. The preparation method as claimed in item 27, wherein the first protruding part and the second protruding part points are formed simultaneously. The manufacturing method according to claim 20, further comprising: forming a first work function member above the first conductive layer and surrounded by the first protruding portion; and forming a first work function member above the first work function member The gate insulating member is surrounded by the first protruding portion. The manufacturing method as claimed in claim 20, wherein the first insulating layer comprises oxide. The method of claim 20, wherein the first conductive layer comprises titanium nitride (TiN). The manufacturing method as claimed in claim 20, wherein the first conductive member comprises tungsten (W). The manufacturing method according to claim 20, wherein a word line includes a first work function member disposed above the first conductive layer and the first conductive member, and a work function member disposed above the first work function member A first gate insulating member. The manufacturing method as claimed in claim 33, wherein the first work function member and the first gate insulating member are surrounded by the first insulating layer. The manufacturing method as claimed in claim 33, wherein the first work function member and the first gate insulating member are in contact with the first protruding portion. The manufacturing method as claimed in claim 33, wherein a total width of the first conductive layer and the first conductive member is substantially equal to a total width of the first protruding portion and the first work function member. The manufacturing method as claimed in claim 33, wherein a total width of the first conductive layer and the first conductive member is substantially equal to a total width of the first protruding portion and the first gate insulating member. The manufacturing method as claimed in claim 33, wherein the first work function component comprises polysilicon. The manufacturing method as claimed in claim 33, wherein the first gate insulating member comprises nitride.

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