TWI833234B - Memory device having word line - Google Patents

Abstract

The present application provides a memory device having a word line with an improved adhesion between a work function member and a conductive layer. The memory device includes a semiconductor substrate defined with an active area and including a recess extending into the semiconductor substrate, and a word line disposed within the recess, wherein the word line includes a first insulating layer disposed within and conformal to the recess, a conductive layer surrounded by the first insulating layer, a conductive member enclosed by the conductive layer, and a second insulating layer disposed over the conductive layer and conformal to the first insulating layer.

Description

Memory device with word lines

This application claims priority to U.S. Patent Application Nos. 17/578,666 and 17/578,918 (i.e., the earliest priority date is "January 19, 2022"), the contents of which are incorporated herein by reference in their entirety.

The present disclosure relates to a memory device. Especially regarding a memory device.

Dynamic random access memory (DRAM) is a semiconductor device used to store multiple bits of data in individual capacitors within an integrated circuit (IC). DRAM is typically formed as trench capacitor DRAM cells. An advanced method of fabricating a buried gate electrode includes constructing a gate electrode of a transistor and a word line in a trench in an active area (AA) that includes shallow trench isolation (AA). STI) structure.

Over the past few decades, as semiconductor manufacturing technology has continued to improve, the size of electronic components has also decreased. As one dimension of a cell transistor decreases to a length of several nanometers, shrinkage may occur during heating. Shrinkage may lead to a decrease in adhesion between components of different materials, thereby significantly reducing the performance of these unit transistors. Therefore, it is desirable to develop improvements to address related manufacturing challenges.

An embodiment of the present disclosure provides a memory device. The memory device includes a semiconductor substrate defining an active region and having a recess extending into the semiconductor substrate; and a word line disposed in the recess; wherein the word line includes a first isolation layer, A conductive layer, a conductive component and a second isolation layer, the first isolation layer is disposed in the recess and conforms to the recess, the conductive layer is surrounded by the first isolation layer, the conductive component is surrounded by the conductive layer Surrounded by the second isolation layer, the second isolation layer is disposed on the conductive layer and conforms to the first isolation layer.

In some embodiments, the second isolation layer contacts the conductive layer.

In some embodiments, the second isolation layer is disposed on the conductive component and the conductive layer.

In some embodiments, the first isolation layer and the second isolation layer include oxide.

In some embodiments, a thickness of the first isolation layer is substantially greater than or equal to a thickness of the second isolation layer.

In some embodiments, the second isolation layer contacts an upper surface of the conductive layer.

In some embodiments, the second isolation layer is at least partially surrounded by the active region.

In some embodiments, the conductive layer includes titanium nitride (TiN).

In some embodiments, the conductive component includes tungsten (W).

In some embodiments, the word line includes a work function component surrounded by the second isolation layer and a gate isolation component disposed on the work function component.

In some embodiments, an upper surface of the work function component is substantially coplanar with an upper surface of the second isolation layer.

In some embodiments, the gate isolation component is disposed on the second isolation layer.

In some embodiments, the gate isolation component contacts the second isolation layer and the work function component.

In some embodiments, the work function component and the gate isolation component are surrounded by the first isolation layer.

In some embodiments, a width of the gate isolation component is substantially greater than or equal to a total width of the second isolation layer and the work function component.

In some embodiments, the work function component includes polysilicon and the gate isolation component includes nitride.

Another embodiment of the present disclosure provides a memory device. The memory device includes a semiconductor substrate defining an active region and including a recess extending into the semiconductor substrate; and a word line disposed in the recess; wherein the word line includes a first isolation layer , a conductive layer, a conductive component, a second isolation layer, a work function component and a third isolation layer, the first isolation layer is disposed in the recess and conforms to the recess, the conductive layer is formed by the first Surrounded by an isolation layer, the conductive layer is surrounded by the conductive layer, the second isolation layer is disposed on the conductive layer and conforms to the first isolation layer, the work function component is surrounded by the second isolation layer, the A third isolation layer is surrounded by the second isolation layer and is disposed on the work function component.

In some embodiments, the work function component is surrounded by the second isolation layer and the third isolation layer.

In some embodiments, the third isolation layer is conformally disposed on an upper surface of the work function component.

In some embodiments, a thickness of the second isolation layer is substantially equal to a thickness of the third isolation layer.

In some embodiments, the second isolation layer and the third isolation layer are integrally formed.

In some embodiments, the second isolation layer and the third isolation layer include oxide.

In some embodiments, the second isolation layer and the third isolation layer include the same material.

In some embodiments, the first isolation layer is completely covered by the conductive layer and the second isolation layer.

In some embodiments, the word line includes a gate isolation component surrounded by the second isolation layer and disposed on the third isolation layer and the work function component.

Another embodiment of the present disclosure provides a method of manufacturing a memory device. The preparation method includes providing a semiconductor substrate that defines an active region and includes an insulating structure surrounding the active region; forming a recess to extend into the semiconductor substrate and across the active region; forming a first An isolation layer conforms to the recess; a first conductive material is provided to conform to the first isolation layer; a conductive component is formed to be surrounded by the first conductive material; a second conductive material is disposed on the conductive component and removing a portion of the first conductive material on the second conductive material to form a conductive layer surrounding the conductive component; and forming a second isolation layer on the conductive layer and conforming to the first isolation layer layer.

In some embodiments, the formation of the second isolation layer is performed after forming the conductive layer and forming the conductive component.

In some embodiments, forming the second isolation layer includes providing an isolation material by atomic layer deposition (ALD).

In some embodiments, forming the second isolation layer includes removing a portion of the isolation material by anisotropic etching.

In some embodiments, an upper surface of the second isolation layer is substantially lower than an upper surface of the first isolation layer and an upper surface of the semiconductor substrate.

In some embodiments, an upper surface of the second isolation layer is substantially coplanar with an upper surface of the first isolation layer and an upper surface of the semiconductor substrate.

In some embodiments, the preparation method further includes forming a work function component on the conductive layer, wherein the work function component is surrounded by the second isolation layer.

In some embodiments, an upper surface of the work function component is substantially coplanar with an upper surface of the second isolation layer.

In some embodiments, an upper surface of the work function component is substantially lower than an upper surface of the second isolation layer.

In some embodiments, the preparation method further includes forming a third isolation layer on the work function component, wherein the third isolation layer is surrounded by the second isolation layer.

In summary, because an isolation layer is disposed between a work function component and a conductive layer in a word line, the adhesion between the work function component and the conductive layer is increased or improved. Therefore, shrinkage or disappearance of the work function component after a heat treatment can be prevented. Improve an overall performance of the memory device and the manufacturing process of the memory device.

The technical features and advantages of the present disclosure have been summarized rather broadly above so that the detailed description of the present disclosure below may be better understood. Other technical features and advantages that constitute the subject matter of the patentable scope of the present disclosure will be described below. It should be understood by those of ordinary skill in the art that the concepts and specific embodiments disclosed below can be easily used to modify or design other structures or processes to achieve the same purposes of the present disclosure. Those with ordinary knowledge in the technical field to which the present disclosure belongs should also understand that such equivalent constructions cannot depart from the spirit and scope of the present disclosure as defined in the appended patent application scope.

Specific examples of components and configurations are described below to simplify embodiments of the present disclosure. Of course, these embodiments are only for illustration and are not intended to limit the scope of the present disclosure. For example, in the description, the first component is formed on the second component, which may include an embodiment in which the first and second components are in direct contact, or may include an additional component formed between the first and second components. An embodiment such that the first and second components are not in direct contact. In addition, embodiments of the present disclosure may repeat reference numbers and/or letters in many examples. These repetitions are for simplicity and clarity and do not in themselves represent a specific relationship between the various embodiments and/or configurations discussed unless otherwise specified herein.

Additionally, this disclosure may repeat element numbers and/or letters in various examples. This repetition is for simplicity and clarity and does not by itself dictate the relationship between the various embodiments and/or configurations discussed.

In addition, for ease of explanation, spaces such as "beneath", "below", "lower", "above", "upper", etc. may be used in this article. Relative terms are used to describe the relationship of one element or feature shown in the figures to another (other) element or feature. These spatially relative terms are intended to encompass different orientations of the elements in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

FIG. 1 is a schematic cross-sectional side view illustrating a memory device 100 according to some embodiments of the present disclosure. In some embodiments, the memory device 100 includes a plurality of unit cells arranged in rows and columns.

In some embodiments, memory device 100 includes a semiconductor substrate 101 . In some embodiments, semiconductor substrate 101 includes a semiconductor material such as silicon, germanium, gallium arsenide, or combinations thereof. In some embodiments, semiconductor substrate 101 includes bulk semiconductor material. In some embodiments, the semiconductor substrate 101 is a semiconductor wafer (eg, a silicon wafer) or a semiconductor-on-insulator (SOI) wafer (eg, a silicon-on-insulator wafer). In some embodiments, the semiconductor substrate 101 is a silicon substrate. In some embodiments, semiconductor substrate 101 includes lightly doped single crystal silicon. In some embodiments, the semiconductor substrate 101 is a p-type substrate.

In some embodiments, the semiconductor substrate 101 includes a plurality of active areas (AA) 101a. The active area 101a is a doped area in the semiconductor substrate 101. In some embodiments, the active region 101a extends horizontally above or below one of the upper surfaces 101b of the semiconductor substrate 101. In some embodiments, each active region 101a includes a dopant of the same type. In some embodiments, each active region 101a includes a different type of dopant than the type of dopant contained in other active regions 101a. In some embodiments, each active region 101a has the same conductivity type. In some embodiments, active region 101a includes N-type dopants.

In some embodiments, the semiconductor substrate 101 includes an upper surface 101b and a lower surface 101c, and the lower surface 101c is opposite to the upper surface 101b. In some embodiments, the upper surface 101b is a front side of the semiconductor substrate 101, wherein a plurality of electronic devices or components are sequentially formed on the upper surface 101b and configured to be electrically connected to an external circuit. In some embodiments, lower surface 101c is a back side of semiconductor substrate 101 and is free of electronic devices or components.

In some embodiments, the semiconductor substrate 101 includes a recess 101d extending into the semiconductor substrate 101 . In some embodiments, recess 101d extends from upper surface 101b of semiconductor substrate 101 toward lower surface 101c of semiconductor substrate 101. In some embodiments, depression 101 d tapers from upper surface 101 b of semiconductor substrate 101 toward lower surface 101 c of semiconductor substrate 101 . In some embodiments, recess 101d has a depth that is substantially greater than a depth of active region 101a.

In some embodiments, the memory device 100 includes a word line 103 disposed within the recess 101d. In some embodiments, the word line 103 includes a first isolation layer 103a, a conductive layer 103b, a conductive component 103c and a second isolation layer 103d. In some embodiments, the first isolation layer 103a is disposed conformally to and within the recess 101d. In some embodiments, conductive layer 103b is surrounded by first isolation layer 103a. In some embodiments, conductive component 103c is surrounded by conductive layer 103b. In some embodiments, the second isolation layer 103d is disposed on the conductive layer 103b and conforms to the first isolation layer 103a.

In some embodiments, the first isolation layer 103a is disposed along an entire side wall of the recess 101d. In some embodiments, first isolation layer 103a includes a dielectric material, such as an oxide. In some embodiments, the first isolation layer 103a includes an isolation material, such as silicon oxide, silicon nitride, silicon oxynitride, the like, or combinations thereof. In some embodiments, the first isolation layer 103a includes a dielectric material with a low dielectric constant (low k).

In some embodiments, the conductive layer 103b is disposed within the recess 101d, wherein the conductive layer 103b is surrounded by the first isolation layer 103a. The electrostatic layer 103b is conformal to a portion of the first isolation layer 103a. In some embodiments, conductive layer 103b includes a conductive material, such as titanium nitride (TiN).

In some embodiments, conductive component 103c is disposed within conductive layer 103b. The conductive component 103c is surrounded by the first isolation layer 103a and the conductive layer 103b. In some embodiments, conductive component 103c is disposed under active region 101a of semiconductor substrate 101. In some embodiments, a portion of conductive layer 103b is disposed on conductive component 103c. In some embodiments, conductive component 103c includes a conductive material, such as tungsten (W).

In some embodiments, the second isolation layer 103d is disposed on the conductive layer 103b, wherein the second isolation layer 103d is surrounded by the first isolation layer 103a. The second isolation layer 103d is disposed on the conductive component 103c and the conductive layer 103b. In some embodiments, second isolation layer 103d contacts conductive layer 103b. In some embodiments, the second isolation layer 103d is conformal to a portion of the first isolation layer 103a.

In some embodiments, the second isolation layer 103d contacts an upper surface 103g of the conductive layer 103b. In some embodiments, the second isolation layer 103d is at least partially surrounded by the active region 101a. In some embodiments, an upper surface 103i of the second isolation layer 103d is substantially lower than the upper surface 101b of the semiconductor substrate 101 and an upper surface 103h of the first isolation layer 103a.

In some embodiments, the second isolation layer 103d includes a dielectric material, such as an oxide. In some embodiments, the second isolation layer 103d includes an isolation material, such as silicon oxide, silicon nitride, silicon oxynitride, the like, or combinations thereof. In some embodiments, the first isolation layer 103a and the second isolation layer 103d include the same material or different materials. In some embodiments, a thickness of the first isolation layer 103a is substantially greater than or equal to a thickness of the second isolation layer 103d. In some embodiments, the thickness of the second isolation layer 103d ranges from about 1 nm to about 3 nm. In some embodiments, the thickness of the second isolation layer 103d is approximately 1.5 nm.

In some embodiments, the word line 103 further includes a work function component 103e and a gate isolation component 103f. The work function component 103e is disposed on the conductive layer 103b and the conductive component 103c. The gate isolation component 103f is disposed on the work function component. 103e on. In some embodiments, the work function component 103e and the gate isolation component 103f are surrounded by the first isolation layer 103a. In some embodiments, work function component 103e is surrounded by second isolation layer 103d.

In some embodiments, an upper surface 103j of the work function component 103e is substantially coplanar with the upper surface 103i of the second isolation layer 103d. In some embodiments, the work function component 103e includes polysilicon or polycrystalline silicon. In some embodiments, work function component 103e has a low work function. In some embodiments, work function component 103e has a dual work function and includes metal and polysilicon. In some embodiments, the work function component 103e acts as a gate electrode.

In some embodiments, the gate isolation component 103f is disposed on the second isolation layer 103d and the work function component 103e. In some embodiments, the gate isolation component 103f contacts the second isolation layer 103d and the work function component 103e. In some embodiments, the gate isolation component 103f contacts the upper surface 103j of the work function component 103e and the upper surface 103i of the second isolation layer 103d. In some embodiments, the work function component 103e and the gate isolation component 103f are surrounded by the first isolation layer 103a. In some embodiments, the gate isolation layer 103f is disposed on the upper surface 101b of the semiconductor substrate 101.

In some embodiments, a width W1 of the gate isolation layer 103f is substantially greater than or equal to a total width W2 of the second isolation layer 103d and the work function component 103e. In some embodiments, the total width W2 is the sum of twice the thickness of the second isolation layer 103d plus the thickness of one of the work function components 103e. In some embodiments, gate isolation component 103f includes a dielectric material, such as nitride. In some embodiments, gate isolation layer 103f acts as a gate dielectric.

In some embodiments, the memory device 100 further includes an insulating structure 102 disposed adjacent the word line 103 . In some embodiments, insulating structure 102 extends into semiconductor substrate 101 from upper surface 101b toward lower surface 101c. In some embodiments, the isolation structure 102 is a shallow trench isolation (STI). In some embodiments, insulating structure 102 defines a boundary of active region 101a. In some embodiments, the insulating structure 102 includes an isolation material such as silicon oxide, silicon nitride, silicon oxynitride, the like, or combinations thereof. In some embodiments, the insulation structure 102 has a depth that is substantially greater than a depth of the word lines 103 .

In some embodiments, the memory device 100 further includes a mask layer 104 disposed on the upper surface 101 b of the semiconductor substrate 101 and on the insulating structure 102 . In some embodiments, mask layer 104 is disposed on first isolation layer 103a. In some embodiments, mask layer 104 contacts upper surface 103h of first isolation layer 103a. In some embodiments, mask layer 104 is disposed between gate isolation component 103f and semiconductor substrate 101, and between gate isolation component 103f and insulating structure 102. In some embodiments, mask layer 104 includes a dielectric material such as nitride or the like.

Because the second isolation layer 103d is disposed between the work function component 103e and the conductive layer 103b, the adhesion between the work function component 103e and the conductive layer 103b is increased or improved. Therefore, shrinkage or disappearance of the work function component 1203e after a heat treatment can be prevented. The overall performance of the memory device 100 can be improved.

FIG. 2 is a schematic cross-sectional side view illustrating a memory device 200 according to other embodiments of the present disclosure. The memory device 200 is similar to the memory device 100 of FIG. 1 except that there is a third isolation layer 103k on the work function component 103e such that the work function component 103e is surrounded by the second isolation layer 103d and the third isolation layer 103k. In some embodiments, the first isolation layer 103a is completely covered by the conductive layer 103b and the second isolation layer 103d. In some embodiments, the gate isolation component 103f is surrounded by the second isolation layer 103d and is disposed on the third isolation layer 103k and the work function component 103e.

In some embodiments, the third isolation layer 103k is surrounded by the second isolation layer 103d. In some embodiments, the third isolation layer 103k is disposed conformally to the upper surface 103j of the work function component 103e. In some embodiments, an upper surface 103m of the third isolation layer 103k is substantially lower than the upper surface 103i of the second isolation layer 103d, the upper surface 103h of the first isolation layer 103a, and the upper surface 101b of the semiconductor substrate 101.

In some embodiments, a thickness of the second isolation layer 103d is substantially equal to a thickness of the third isolation layer 103k. In some embodiments, the second isolation layer 103d and the third isolation layer 103k are integrally formed. In some embodiments, the third isolation layer 103k includes oxide. In some embodiments, the second isolation layer 103d and the third isolation layer 103k include the same material.

FIG. 3 is a schematic cross-sectional side view illustrating a memory device 300 according to other embodiments of the present disclosure. The memory device 300 is similar to the memory device 200 of FIG. 2 except that the third isolation layer 103k of the memory device 200 of FIG. 2 is omitted. In some embodiments, gate isolation component 103f contacts work function component 103e. The second isolation layer 103d surrounds the work function component 103e and the gate isolation component 103f.

FIG. 4 is a schematic cross-sectional side view illustrating a memory device 400 according to other embodiments of the present disclosure. The memory device 400 is similar to the memory device 200 of FIG. 2 , except that the second isolation layer 103 d is also disposed on the upper surface 101 b of the semiconductor substrate 101 and on the insulating structure 102 . In some embodiments, the second isolation layer 103d is disposed on the mask layer 104. In some embodiments, the upper surface 103i of the second isolation layer 103d is on the upper surface 103h of the first isolation layer 103a and on the upper surface 101b of the semiconductor substrate 101.

FIG. 5 is a schematic cross-sectional side view illustrating a memory device 500 according to other embodiments of the present disclosure. Memory device 500 is similar to memory device 100 of Figure 1, except that second isolation layer 103d is disposed under work function component 103e. The second isolation layer 103d is between the work function component 103e and the conductive layer 103b. In some embodiments, the second isolation layer 103d is surrounded by the work function component 103e, the conductive layer 103b, and the first isolation layer 103a. In some embodiments, the upper surface 103i of the second isolation layer 103d fully contacts the work function component 103e. In some embodiments, upper surface 103i is substantially lower than upper surface 103j of work function component 103e.

FIG. 6 is a schematic flowchart illustrating the manufacturing method S600 of the memory device 100, 200, 300, 400 or 500 according to some embodiments of the present disclosure. 7 to 37 are schematic cross-sectional views illustrating various intermediate stages in the formation of the memory device 100, 200, 300, 400 or 500 according to some embodiments of the present disclosure.

The stages shown in FIGS. 7 to 37 are also exemplarily described in the flowchart in FIG. 6 . In the following discussion, the various manufacturing stages shown in FIGS. 7 through 37 are discussed with reference to the various processing steps shown in FIG. 6 . The preparation method 6300 includes some steps, and their description and illustration are not considered to limit the order of the steps. The preparation method S600 includes some steps (S601, S602, S603, S604, S605, S606, S607).

Referring to FIG. 7 , according to step S601 of FIG. 6 , a semiconductor substrate 101 is provided. In some embodiments, the semiconductor substrate 101 defines an active region 101a and includes an insulating structure 102 surrounding the active region 101a. In some embodiments, the insulating structure 102 extends from the upper surface 101b of the semiconductor substrate 101 toward the lower surface 101c.

Referring to FIG. 8 , according to step S602 of FIG. 6 , a recess 101d is formed to extend into the semiconductor substrate 101 . In some embodiments, recess 101d extends across active region 101a. In some embodiments, the formation of recess 101d includes removing portions of semiconductor substrate 101. In some embodiments, recess 101d extends from upper surface 101b of semiconductor substrate 101 toward lower surface 101c.

Referring to FIG. 9 , according to step S603 of FIG. 6 , a first isolation layer 103 a conforming to the recess 101 d is formed. In some embodiments, the manufacturing technology of the first isolation layer 103a includes deposition, oxidation or any other suitable process. In some embodiments, the upper surface 103h of the first isolation layer 103a is substantially coplanar with the upper surface 101b of the semiconductor substrate 101.

Please refer to FIG. 10. According to step S604 of FIG. 6, a first conductive material 105 is disposed conformally to the first isolation layer 103a. In some embodiments, the manufacturing technique of the first conductive material 105 includes deposition or any other suitable process. In some embodiments, first conductive material 105 includes titanium nitride (TiN).

Referring to FIG. 11, according to step S605 of FIG. 6, a conductive component 103c surrounded by the first conductive material 105 is formed. In some embodiments, the fabrication technique of the conductive component 103c includes disposing a second conductive material surrounded by the first conductive material 105, and then removing a portion of the second conductive material to form the conductive component 103c. In some embodiments, the second conductive material is provided by deposition or any other suitable process. In some embodiments, the portion of the second conductive material is removed by etching or any other suitable process. In some embodiments, the second conductive material includes tungsten (W).

Please refer to Figures 12 and 13. According to step S606 of Figure 6, a third conductive material 106 is disposed on the conductive component 103c, and a portion of the first conductive material 105 on the third conductive material 106 is removed to form a conductive Layer 103b. In some embodiments, conductive layer 103b surrounds conductive component 103c. In some embodiments, the third conductive material 106 is disposed on the conductive component 103c by deposition or any other suitable process. In some embodiments, the first conductive material 105 and the third conductive material 106 are the same material. In some embodiments, third conductive material 106 includes titanium nitride. In some embodiments, after disposing the third conductive material 106 as shown in Figure 12, a portion of the first conductive material 105 is removed to form the conductive layer 103b as shown in Figure 13. In some embodiments, the portion of first conductive material 105 is removed by etching, cleaning, or any other suitable process.

Referring to FIGS. 14 and 15 , according to step S607 of FIG. 6 , a second isolation layer 103d is formed on the conductive layer 103b and conforms to the first isolation layer 103a. In some embodiments, the formation of the second isolation layer 103d includes disposing a first isolation layer 107 on the semiconductor substrate 101, the insulating structure 102, the conductive layer 103b and the first isolation layer 103a. In some embodiments, the first isolation layer 107 is provided by atomic layer deposition (ALD) or any other suitable process.

In some embodiments, after disposing the first isolation material 107 as shown in FIG. 14 , a portion of the first isolation material 107 on the semiconductor substrate 101 , the insulating structure 102 and the first isolation layer 103 a is removed to form a structure as shown in FIG. The second isolation layer 103d shown in 15. In some embodiments, this portion of first isolation material 107 is removed by anisotropic etching, planarization, or any other suitable process. In some embodiments, an upper surface 103i of the second isolation layer 103d is substantially lower than the upper surface 103h of the first isolation layer 103a and the upper surface 101b of the semiconductor substrate 101. In some embodiments, the formation of the second isolation layer 103d is performed after the conductive layer 103b is formed and the conductive component 103c is formed.

Referring to FIGS. 16 and 17 , a work function component 103e is formed on the conductive layer 103b and is surrounded by the second isolation layer 103d. In some embodiments, the fabrication technique of the work function component 103e includes disposing a work function material 108 to be surrounded by the second isolation layer 103d and the first isolation layer 103a as shown in FIG. 16, and then removing the work function material 108. part to form a work function component 103e as shown in FIG. 17 . In some embodiments, work function material 108 is provided by deposition, CVD, or any other suitable process. In some embodiments, this portion of work function material 108 is removed by etching or any other suitable process. In some embodiments, work function material 108 includes polycrystalline silicon. In some embodiments, an upper surface 103j of the work function component 103e is substantially coplanar with the upper surface 103i of the second isolation layer 103d.

Referring to FIG. 18, a mask layer 104 is formed on the semiconductor substrate 101, the insulating structure 102 and the first isolation layer 103a. In some embodiments, mask layer 104 contacts upper surface 103h of first isolation layer 103a. In some embodiments, the fabrication technique of the mask layer 104 includes providing a mask material, such as nitride.

Referring to FIG. 19 , a gate isolation component 103f is formed on the work function component 103e, the second isolation layer 103d and the mask layer 104. In some embodiments, the formation of gate isolation layer 103f includes providing a gate isolation material by deposition or any other suitable process. In some embodiments, the memory device 100 of FIG. 1 is formed as shown in FIG. 19 .

In some embodiments, after disposing the first isolation material 107 as shown in FIG. 14 , the fabrication technique of the memory device 200 of FIG. 2 may include the following steps. After disposing the first isolation material 107 as shown in FIG. 14 , a portion of the first isolation material 107 disposed on the semiconductor substrate 101 , the insulating structure 102 and the first isolation layer 103 a is removed to form the first isolation layer 107 as shown in FIG. 20 . Second isolation layer 103d. In some embodiments, the portion of first isolation material 107 is removed by anisotropic etching, planarization, or any other suitable process. In some embodiments, the upper surface 103i of the second isolation layer 103d is substantially coplanar with the upper surface 103h of the first isolation layer 103a and the upper surface 101b of the semiconductor substrate 101.

In some embodiments, after the second isolation layer 103d is formed, the work function component as shown in FIGS. 21 and 22 is formed in a method similar to one of the steps described above and described in FIGS. 16 and 17 103. In some embodiments, the upper surface 103j of the work function component 103e is substantially lower than the upper surface 103i of the second isolation layer 103d.

In some embodiments, after forming the work function component 103e as shown in Figure 22, a third isolation layer 103k is formed on the work function component 103e, wherein as shown in Figure 23, the third isolation layer 103k is separated by the second isolation layer 103k. surrounded by layer 103d. In some embodiments, forming the third isolation layer 103k includes disposing a second isolation material on the work function component 103e. In some embodiments, the second isolation material is provided by ALD or any other suitable process. In some embodiments, an upper surface 103m of the third isolation layer 103k is substantially lower than the upper surface 103i of the second isolation layer 103d. In some embodiments, the first isolation material 107 and the second isolation material include the same material. In some embodiments, the second isolation layer 103d and the third isolation layer 103k are integrally formed.

In some embodiments, after forming the third isolation layer 103m, the mask layer 104 and the gate isolation component 103f are formed in a manner similar to the steps described above and in FIGS. 18 and 19 . In some embodiments, the memory device 20 of FIG. 2 is formed as shown in FIG. 24 .

In some embodiments, after forming the second isolation layer 103d as shown in FIG. 22, the fabrication technology of the memory device 300 in FIG. 3 may include the following steps. After the second isolation layer 103d as shown in FIG. 22 is formed, the mask layer 104 is disposed on the first isolation layer 103a and the second isolation layer 103d as shown in FIG. 25. In some embodiments, mask layer 104 is provided in a manner similar to the steps described above and depicted in FIG. 18 . After the mask layer 104 is provided, the gate isolation component 103f is formed in a manner similar to the steps described above and depicted in FIG. 19 . In some embodiments, the memory device 300 of FIG. 3 is formed as shown in FIG. 26 .

In some embodiments, after forming the conductive layer 103b as shown in FIG. 13, the fabrication technology of the memory device 400 in FIG. 4 may include the following steps. After forming the conductive layer 103b as shown in FIG. 13, the mask layer 104 is disposed on the first isolation layer 103a, the semiconductor substrate 101 and the insulating structure 102 as shown in FIG. 27. In some embodiments, mask layer 104 is provided in a manner similar to the steps described above and depicted in FIG. 18 .

In some embodiments, after the mask layer 104 is provided, the first isolation material 107 is disposed on the mask layer 104 and the conductive layer 103b, and conforms to the first isolation layer 103a as shown in FIG. 28 . In some embodiments, the first isolation material 107 is provided in a manner similar to the steps described above and illustrated in FIG. 14 . In some embodiments, the second isolation layer 103d is formed as shown in FIG. 28 .

In some embodiments, after forming the second isolation layer 103d, the work function material 108 is configured as shown in Figure 29. In some embodiments, the work function material 108 is provided in a manner similar to the steps shown above and described in FIG. 16 . In some embodiments, after the work function material 108 is provided, a portion of the work function material 108 is removed to form the work function component 103e as shown in FIG. 30 . In some embodiments, the portion of the work function material 108 is removed in a manner similar to the steps described above and depicted in FIG. 17 .

In some embodiments, after the work function component 103e is formed, a third isolation layer 103k is disposed on the work function component 103e as shown in FIG. 31 . In some embodiments, the first isolation layer 103k is provided in a manner similar to the steps described above and depicted in FIG. 23 . In some embodiments, after forming the third isolation layer 103k, the gate isolation component 103f is formed on the second isolation layer 103d and the third isolation layer 103k as shown in FIG. 32 . In some embodiments, gate isolation component 103f is formed in a manner similar to the steps described above and depicted in FIG. 19 . In some embodiments, the memory device 400 of FIG. 4 is formed as shown in FIG. 32 .

In some embodiments, after forming the conductive layer 103b as shown in FIG. 13, the fabrication technology of the memory device 500 in FIG. 5 may include the following steps. In some embodiments, after forming the conductive layer 103b as shown in FIG. 13, a second isolation layer 103d is formed on the conductive layer 103b as shown in FIG. 33. In some embodiments, the second isolation layer 103d is formed in a method similar to the steps described above and described in FIGS. 14 and 15 .

In some embodiments, after the second isolation layer 103d is formed, the work function component 103e is formed as shown in FIG. 35. In some embodiments, the function component 103e is formed in a manner similar to the steps described above and described in FIGS. 16 and 17 . In some embodiments, the upper surface 103i of the second isolation layer 103d is substantially lower than the upper surface 103j of the work function component 103e.

In some embodiments, after the work function component 103e is formed, the mask layer 104 and the gate isolation component 103f are formed as shown in FIG. 36 and FIG. 37 respectively. In some embodiments, the mask layer 104 and the gate isolation component 103f are formed in a manner similar to the steps described above and described in FIGS. 18 and 19 . In some embodiments, the memory device 500 of FIG. 5 is formed as shown in FIG. 37 .

An embodiment of the present disclosure provides a memory device. The memory device includes a semiconductor substrate defining an active region and having a recess extending into the semiconductor substrate; and a word line disposed in the recess; wherein the word line includes a first isolation layer, A conductive layer, a conductive component and a second isolation layer, the first isolation layer is disposed in the recess and conforms to the recess, the conductive layer is surrounded by the first isolation layer, the conductive component is surrounded by the conductive layer Surrounded by the second isolation layer, the second isolation layer is disposed on the conductive layer and conforms to the first isolation layer.

Another embodiment of the present disclosure provides a memory device. The memory device includes a semiconductor substrate defining an active region and including a recess extending into the semiconductor substrate; and a word line disposed in the recess; wherein the word line includes a first isolation layer , a conductive layer, a conductive component, a second isolation layer, a work function component and a third isolation layer, the first isolation layer is disposed in the recess and conforms to the recess, the conductive layer is formed by the first Surrounded by an isolation layer, the conductive layer is surrounded by the conductive layer, the second isolation layer is disposed on the conductive layer and conforms to the first isolation layer, the work function component is surrounded by the second isolation layer, the A third isolation layer is surrounded by the second isolation layer and is disposed on the work function component.

Another embodiment of the present disclosure provides a method of manufacturing a memory device. The preparation method includes providing a semiconductor substrate that defines an active region and includes an insulating structure surrounding the active region; forming a recess to extend into the semiconductor substrate and across the active region; forming a first An isolation layer conforms to the recess; a first conductive material is provided to conform to the first isolation layer; a conductive component is formed to be surrounded by the first conductive material; a second conductive material is disposed on the conductive component and removing a portion of the first conductive material on the second conductive material to form a conductive layer surrounding the conductive component; and forming a second isolation layer on the conductive layer and conforming to the first isolation layer layer.

In summary, because an isolation layer is disposed between a work function component and a conductive layer in a word line, the adhesion between the work function component and the conductive layer is increased or improved. Therefore, shrinkage or disappearance of the work function component after a heat treatment can be prevented. Improve an overall performance of the memory device and the manufacturing process of the memory device.

Although the disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and substitutions can be made without departing from the spirit and scope of the disclosure as defined by the claimed claims. For example, many of the processes described above may be implemented in different ways and replaced with other processes or combinations thereof.

Furthermore, the scope of the present application is not limited to the specific embodiments of the process, machinery, manufacture, material compositions, means, methods and steps described in the specification. Those skilled in the art can understand from the disclosure content of this disclosure that existing or future developed processes, machinery, manufacturing, etc. that have the same functions or achieve substantially the same results as the corresponding embodiments described herein can be used according to the present disclosure. A material composition, means, method, or step. Accordingly, such processes, machines, manufacturing, material compositions, means, methods, or steps are included in the patent scope of this application.

100:Memory components 101:Semiconductor substrate 101a: Active area 101b: Upper surface 101c: Lower surface 101d: depression 102:Insulation structure 103: character line 103a: First isolation layer 103b: Conductive layer 103c: Conductive components 103d: Second isolation layer 103e: Work function component 103f: Gate isolation component 103g: upper surface 103h: Upper surface 103i: Upper surface 103j: Upper surface 103k: The third isolation layer 103m: upper surface 104:Mask layer 105: First conductive material 106:Third conductive material 107:First isolation material 108: Work function materials 200:Memory components 300:Memory component 400:Memory component 500:Memory component S600:Preparation method S601: Step S602: Step S603: Step S604: Step S605: Step S606: Step S607: Step W1: Width W2: Width

When the drawings are considered together with the embodiments and patent scope of the application, the disclosure content of this application can be more fully understood. It is understood that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion. FIG. 1 is a schematic cross-sectional side view illustrating a memory device according to some embodiments of the present disclosure. FIG. 2 is a schematic cross-sectional side view illustrating a memory device according to other embodiments of the present disclosure. FIG. 3 is a schematic cross-sectional side view illustrating a memory device according to other embodiments of the present disclosure. 4 is a schematic cross-sectional side view illustrating a memory device according to other embodiments of the present disclosure. FIG. 5 is a schematic cross-sectional side view illustrating a memory device according to other embodiments of the present disclosure. FIG. 6 is a schematic flowchart illustrating a method of manufacturing a memory device according to some embodiments of the present disclosure. 7 to 37 are schematic cross-sectional views illustrating various intermediate stages in the formation of memory devices according to some embodiments of the present disclosure.

100:Memory components

101:Semiconductor substrate

101a: Active area

101b: Upper surface

101c: Lower surface

101d: depression

102:Insulation structure

103: character line

103a: First isolation layer

103b: Conductive layer

103c: Conductive components

103d: Second isolation layer

103e: Work function component

103f: Gate isolation component

103g: upper surface

103h: Upper surface

103i: Upper surface

103j: Upper surface

104:Mask layer

W1: Width

W2: Width

Claims (18)

A memory device includes: a semiconductor substrate defining an active region and having a recess extending into the semiconductor substrate; and a word line disposed in the recess; wherein the word line includes a first isolation layer, a conductive layer, a conductive component and a second isolation layer, the first isolation layer is disposed in the recess and is conformal to the recess, the conductive layer is surrounded by the first isolation layer, the conductive component is surrounded by the Surrounded by a conductive layer, the second isolation layer is disposed on the conductive layer and conforms to the first isolation layer, wherein the word line has a work function component and a gate isolation component, and the work function component is Surrounded by two isolation layers, the gate isolation component is disposed on the work function component, and wherein the work function component and the gate isolation component are surrounded by the first isolation layer, the work function component includes polysilicon, the gate Isolation components include nitride. The memory device of claim 1, wherein the second isolation layer contacts the conductive layer. The memory device of claim 1, wherein the second isolation layer is disposed on the conductive component and the conductive layer. The memory device of claim 1, wherein a thickness of the first isolation layer is greater than or equal to a thickness of the second isolation layer. The memory device of claim 1, wherein the second isolation layer contacts an upper surface of the conductive layer. The memory device of claim 1, wherein the second isolation layer is at least partially surrounded by the active area. The memory device of claim 1, wherein the conductive layer includes titanium nitride or tungsten. The memory device of claim 1, wherein an upper surface of the work function component is coplanar with an upper surface of the second isolation layer. The memory device of claim 1, wherein the gate isolation component is disposed on the second isolation layer and contacts the second isolation layer and the work function component. The memory device of claim 1, wherein a width of the gate isolation component is greater than or equal to a total width of the second isolation layer and the work function component. A memory element includes: a semiconductor substrate defining an active region and including a recess extending into the semiconductor substrate; and a word line disposed in the recess; wherein the word line includes a first an isolation layer, a conductive layer, a conductive component, a first two isolation layers, a work function component, a gate isolation component and a third isolation layer, the first isolation layer is disposed in the recess and conforms to the recess, the conductive layer is surrounded by the first isolation layer, The conductive layer is surrounded by the conductive layer, the second isolation layer is disposed on the conductive layer and conforms to the first isolation layer, the work function component is surrounded by the second isolation layer, and the third isolation layer is The second isolation layer surrounds and is disposed on the work function component, the gate isolation component is disposed on the work function component, wherein the work function component and the gate isolation component are surrounded by the first isolation layer, The work function component includes polysilicon and the gate isolation component includes nitride. The memory device of claim 11, wherein the work function component is surrounded by the second isolation layer and the third isolation layer. The memory device of claim 11, wherein the third isolation layer is conformally disposed on an upper surface of the work function component. The memory device of claim 11, wherein a thickness of the second isolation layer is equal to a thickness of the third isolation layer. The memory device of claim 11, wherein the second isolation layer and the third isolation layer are integrally formed. The memory device of claim 11, wherein the second isolation layer and the third isolation layer include oxide. The memory device of claim 11, wherein the first isolation layer is completely covered by the conductive layer and the second isolation layer. The memory device of claim 11, wherein the gate isolation component is surrounded by the second isolation layer and is disposed on the third isolation layer and the work function component.