US20160013191A1 - Capacitor and method of manufacturing the same - Google Patents
Capacitor and method of manufacturing the same Download PDFInfo
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- US20160013191A1 US20160013191A1 US14/860,703 US201514860703A US2016013191A1 US 20160013191 A1 US20160013191 A1 US 20160013191A1 US 201514860703 A US201514860703 A US 201514860703A US 2016013191 A1 US2016013191 A1 US 2016013191A1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
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- H01L27/10805—
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02043—Cleaning before device manufacture, i.e. Begin-Of-Line process
- H01L21/02046—Dry cleaning only
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02043—Cleaning before device manufacture, i.e. Begin-Of-Line process
- H01L21/02052—Wet cleaning only
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Semiconductor Memories (AREA)
Abstract
A capacitor includes a substrate, a multilayer over the substrate, a plurality of container-shaped storage node structures on the semiconductor substrate and surrounded by the multilayer, the storage node structure has a sidewall extending upwardly from the base to the top, where the sidewall includes an upper segment and a lower segment thinner than the upper segment, a capacitor dielectric material along a surface of each storage node structure, and a capacitor electrode material over the capacitor dielectric material.
Description
- This application is a continuation of U.S. application Ser. No. 14/249,340 filed Apr. 9, 2014.
- 1. Field of the Invention
- The present invention relates generally to a method of manufacturing semiconductor devices and, more specifically, to a method of manufacturing a capacitor with variable bottom cell plate (BCP) sidewall thickness.
- 2. Description of the Prior Art
- Capacitors continue to have increasing aspect ratios in higher generation integrated circuitry fabrication. For example, dynamic random access memory (DRAM) capacitors now have elevations of from 1 to 3 microns, and widths of less than or equal to about 0.1 micron.
- A common type of capacitor is a so-called container device. A storage electrode of such device is shaped as a container. Dielectric material and another capacitor electrode may be formed within the container and/or along an outer edge of the container, which can form a capacitor having high capacitance and a small footprint.
- Container-shaped storage nodes are becoming increasingly taller and narrower (i.e., are being formed with higher aspect ratios) in an effort to achieve desired levels of capacitance while decreasing the amount of semiconductor real estate consumed by individual capacitors. Unfortunately, high aspect ratio container-shaped storage nodes can be structurally weak, and subject to toppling, twisting and/or breaking from an underlying base.
- Exemplary methodology being developed to avoiding toppling of high aspect ratio containers is so-called lattice methodology. In such methodology, a lattice is provided to hold container-shaped electrodes from toppling, while leaving outer surfaces of the container-shaped electrodes exposed for utilization as capacitive surfaces of capacitors. During lattice methodology, container-shaped electrodes are formed in openings in a supporting material (such as, for example, borophosphosilicate glass (BPSG)), and then the supporting material is removed with an isotropic etch.
- Unfortunately, conventional lattice methodology alone is not enough to prevent toppling, twisting and breaking of container-shaped storage nodes formed with increasingly high aspect ratios. Furthermore, in order to meet cell capacitance requirements for advanced DRAM technologies, larger and improved capacitance is always required. Accordingly, it is desired to develop new storage node structures, and new methods for forming storage node structures.
- It is therefore one objective of the present invention to provide a novel capacitor structure with variable bottom cell plate (BCP) sidewall thickness to increase the capacitance as well as the dual lattice structures to increase the aspect ratio of the capacitor structure and further avoid the toppling issue. A method of manufacturing this capacitor structure without complicated process steps is also provided in the present invention to demonstrate the manufacture of the capacitor structure.
- One object of the present invention is to provide a capacitor having a substrate; a multilayer over the substrate, wherein the multilayer includes an isolation layer on the substrate, a stack material layer on the isolation layer, an upper lattice layer on top of the stack material layer, and at least one lower lattice layer in the stack material layer; a plurality of container-shaped storage node structures on the semiconductor substrate and surrounded by the multilayer, the storage node structure having a base, a sidewall extending upwardly from the base to the top of the storage node structure, wherein the sidewall includes an upper segment and a lower segment thinner than the upper segment; a capacitor dielectric material along a surface of each storage node structure; and a capacitor electrode material over the capacitor dielectric material, with the capacitor electrode material being capacitively coupled to the storage node structure through the capacitor dielectric material.
- Another object of the present invention is to provide a method of manufacturing a capacitor, which include the steps of providing a substrate with a multilayer formed thereon, wherein the multilayer includes an isolation layer on the substrate, a stack material layer on the isolation layer, an upper lattice layer on the stack material layer, and at least one lower lattice layer in the stack material layer; forming a recess in the multilayer; conformally forming a storage layer on the surface of the multilayer and the recess; filling up the recess with a photoresist; removing the storage layer on the upper lattice layer; partially removing the photoresist in said recess and exposing a portion of the storage layer; laterally thinning the exposed storage layer above the photoresist; removing the photoresist; forming a capacitor dielectric material along the surface of the storage layer; and forming a capacitor electrode material over the capacitor dielectric material.
- These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
- The accompanying drawings are included to provide a further understanding of the embodiments, and are incorporated in and constitute apart of this specification. The drawings illustrate some of the embodiments and, together with the description, serve to explain their principles. In the drawings:
-
FIGS. 1-7 are cross-sectional views schematically depicting a process flow for manufacturing a single-sided capacitor structure in accordance with one embodiment of present invention. -
FIGS. 8-10 are cross-sectional views schematically depicting a process flow for manufacturing a double-sided capacitor structure in accordance with another embodiment of present invention. - It should be noted that all the figures are diagrammatic. Relative dimensions and proportions of parts of the drawings have been shown exaggerated or reduced in size, for the sake of clarity and convenience in the drawings. The same reference signs are generally used to refer to corresponding or similar features in modified and different embodiments.
- In the following detailed description of the present invention, reference is made to the accompanying drawings which form a part hereof and is shown by way of illustration and specific embodiments in which the invention may be practiced. These embodiments are described in sufficient details to enable those skilled in the art to practice the invention. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the present invention. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims.
- Please refer to
FIGS. 1-7 , which are cross-sectional views schematically depicting a process flow for manufacturing a capacitor in accordance with one embodiment of the present invention. First, as shown inFIG. 1 , asemiconductor substrate 12 is provided to serve as a base for forming devices, components, or circuits. Thesubstrate 12 may comprise, consist essentially of, or consist of monocrystalline silicon, and may be referred to as a semiconductor substrate, or as a portion of a semiconductor substrate. The terms “semiconductive substrate,” “semiconductor construction” and “semiconductor substrate” mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials), and semiconductive material regions (either alone or in assemblies comprising other materials). The term “substrate” refers to any supporting structure, including, but not limited to, the semiconductive substrates described above. Although thesubstrate 12 in this embodiment is shown to be homogenous, the substrate may comprise numerous materials in some embodiments. For instance, thesubstrate 12 may correspond to a semiconductor substrate containing one or more materials associated with integrated circuit fabrication. In such embodiments, such materials may correspond to one or more of refractory metal materials, barrier materials, diffusion materials, insulator materials, etc. - Refer again to
FIG. 1 ,isolation layers 14 are formed over thesubstrate 12 with source/drain implant regions 16 are shown to be between theisolation layers 14. Theisolation layers 14 may correspond to shallow trench isolation regions in thesubstrate 12, and may be filled with any suitable electrically insulative composition or combination of electrically insulative compositions. For instance, in some embodiments theisolation layers 16 may be filled with one or more of silicon dioxide, silicon nitride and silicon oxynitride. The source/drain implant region 16 may comprise any suitable dopant or combination of dopants, and in some embodiments may correspond to an n-type doped region of semiconductor material ofsubstrate 12. For instance, thesubstrate 12 may comprise monocrystalline silicon, and source/drain implant region 16 may correspond to a region of thesubstrate 12 that is conductively doped with one or both of phosphorus and arsenic. Alternatively, the source/drain implant region 16 may be formed of metal such as tungsten (W) or layers such as TiN/W. The source/drain implant region 16 is one example of an electrical node that may be electrically connected with the base of a storage node. Detailed description will be provided in the following embodiment. - A
multilayer 20 is formed over thesubstrate 12 and covers theisolation layers 14 and theimplant region 16. Themultilayer 20 includes a lowerstack material layer 22 and an upperstack material layer 24 on theisolation layers 16 and theimplant region 16 with alower lattice layer 26 sandwiched therebetween. Anupper lattice layer 28 is formed on the top surface of the upperstack material layer 24. The height of the sum of the lowerstack material layer 22 and thelower lattice layer 26 is about 8000 Å (d1), the height of the sum of the upperstack material layer 24 and theupper lattice layer 28 is about 7000 Å (d2), and the total stack height of themultilayer 20 may be about range of 15000 Å to 20000 Å. - The
stack material layers lattice layer lower lattice layer 26 is provided in the stack material layer. In other embodiment, there may be two or more lower lattice layers disposed in the stack material layer. - Refer again to
FIG. 1 , a plurality ofrecesses 30 are formed in themultilayer 20 for accommodating the storage node structure to be manufactured. Therecess 30 extends through the entire thickness of themultilayer 30 and exposes the source/drain implant region 16 thereunder. In the shown embodiment, the source/drain implant region 16 is configured to be electrically connected with the storage node. Thus, an electricallyconductive layer 32 is required to be pre-formed over theimplant region 16 to improve electrical coupling between the base of storage node and the conductively-dopedimplant region 16. For instance, theconductive layer 32 may be a metal silicide (e.g., titanium silicide, tungsten silicide, etc.) layer formed by silicide process. Alternatively, if the source/drain implant region 16 is formed of metal (ex. W) or metal layers (ex. TiN/W), the electricallyconductive layer 32 may be omitted. - In the present invention, the design of dual (or multiple) lattice layers may improve the conventional lattice methodology and provide enough support to prevent the capacitor electrodes from toppling. Furthermore, better aspect ratio of the capacitor recess may be obtained to further increase the capacitance in this kind of multi-lattices stack structure.
- As shown in
FIG. 2 , after providing themultilayer 20 and therecesses 30, astorage layer 34 is conformally formed on the surface of themultilayer 20 and therecesses 30. Asmaller recess 36 is defined in eachformer recess 30. In this embodiment, thestorage layer 34 will be used to form the storage node structure with variable thickness. Thestorage layer 34 may be made of any suitable electrically conductive composition or combination of compositions, such as titanium nitride (TiN). - As shown in
FIG. 3 , after forming thestorage layer 34, aphotoresist 38 is formed on themultilayer 20. In this embodiment, thephotoresist 38 includes anouter portion 38 a covering theentire multilayer 20 and aninner portion 38 b filling up therecess 36. Theinner portion 38 b of thephotoresist 38 may prevent the slurry particle or residue being entrapped in therecesses 36 in the following planarization process. Please note that thephotoresist 38 may be replaced with other material such as oxide (ex. spin-on dielectric, SOD). - As shown in
FIG. 4 , after covering and filling with thephotoresist 38, a chemical mechanical polishing (CMP) process is performed to remove theouter portion 38 a of thephotoresist 38 and a portion of thestorage layer 34 on theupper lattice layer 28, thus thestorage layer 34 may be transformed to a container-shapedstorage node structure 40 embedded in themultilayer 20. Thestorage node structure 40 includes abase 40 a along the bottom which is electrically connected with the source/drain implant region 16 (through the silicide 32) thereunder, and twosidewalls 40 b extending upwardly from the base 40 a. The top surface of thestorage node structure 40 is coplanar with the top surface of theupper lattice layer 28. Although there appear to be twoseparate sidewalls 40 b along the cross-section of the view ofFIG. 4 ,such sidewalls 40 b may be a part of a single sidewall structure when considered in three dimensions, such as a single circular cylinder when viewed from above. - The
sidewalls 40 b in the cross-sectional view ofFIG. 4 have a substantially constant thickness from the bottoms of the sidewalls to the tops of the sidewalls. The term “substantially constant thickness” means that the thickness is uniform to within tolerances imposed by the fabrication process utilized to form thestorage node structure 40. In some embodiments, the thickness of the sidewalls 40 b of thestorage node structure 40 may be within a range of from about 40 Å, to about 100 Å, and may be, for example, about 70 Å. In some embodiments, the thickness may vary from the top of the sidewalls to the bottom of the sidewalls, with the upper portion of the sidewall being thicker than the lower portion of the sidewall due to difficulties associated with the uniform deposition of thestorage layer 34 within a high aspect ratio opening during formation of thestorage node structure 40. - In the shown embodiment, source/
drain implant region 16 is electrically connected to thestorage node structure 40. In some embodiments, thestorage node structure 40 is ultimately incorporated into a capacitor, and such capacitor is ultimately connected to a transistor to form a DRAM unit cell. Thus,implant region 16 may connect to a transistor gate that gatedly couples source/drain implant region 16 to another source/drain implant region (not shown). The transistor gate may be part of an access line (i.e., a word line), and the other source/drain region may be connected to a digit line. Accordingly, thestorage node structure 40 may be uniquely addressed through the combination of the digit line and the access line. The shownstorage node structure 40 may be one of a large plurality of storage node structures that are subjected to identical processing during fabrication of a DRAM array. - As shown in
FIG. 5 , after the CMP process, a descum process is performed to partially removed theinner portion 38 b from therecess 36. The descum process may be optimized to control theinner portion 38 b recessing inside the container-shapedstorage node structure 40. In this embodiment, theinner portion 38 b is partially removed such that thesidewall 40 b of thestorage node structure 40 above thelower lattice layer 26 is exposed and may be subject to a following thinning process. Detailed description will be provided in the following embodiment. - As shown in
FIG. 6 , after a portion ofsidewall 40 b of thestorage node structure 40 is exposed, a post-descum wet clean process is performed to laterally etch and thin the exposedstorage node structure 40 above theinner portion 38 b, while the unexposedstorage node structure 40 protected by theinner portion 38 b is intact. After the thinning process, thesidewall 40 b of thestorage node structure 40 may be divided into two distinct segments, wherein one is theupper segment 40 c with small thickness, the other is thelower segment 40 d with larger thickness. The boundary of theupper segment 40 c and thelower segment 40 d may be above or below thelattice layer 26 depending on the cap requirement. The wet clean process may use chemical with HF concentration ranging from 2000:1 HF to 10:1 HF followed by a standard APM clean process with APM concentration ranging from 0.5:1.0 APM to 0.02:0.025 APM. An etch process may be considered to be “selective” for a first material relative to a second material if the etch removes the first material at a faster rate than the second material, which can include but is not limited to, etches which are 100% selective for the first material relative to the second material. It may be desirable to utilize an etchant that removes thestorage node structure 40 relatively slowly in order to have stringent control over the removing amount removed during the thinning process. Accordingly, it may be desirable to have the active components of the etchant be relatively dilute in the etchant and/or to utilize relatively cold etchant, such as cold APM. - In this embodiment, the reduced thickness of the
upper segment 40 c of thestorage node structure 40 may be less than or equal to one-half of the original thickness of thelower segment 40 d. For instance, the thickness of thelower segment 40 d may be 40 Å, while the reduced thickness of theupper segment 40 c may be thinned to 20 Å. - As shown in
FIG. 7 , after thinning thestorage node structure 40, the remaininginner portion 38 b in thestorage node structure 40 may be completely removed to expose the whole recess. Acapacitor dielectric material 42 is formed conformally along the inner surfaces of the modifiedstorage node structure 40 and the surface of theupper lattice layer 28, including theupper segment 40 c andlower segment 40 d, and subsequently a capacitor electrode material 44 (which may also be referred to as cell plate material) is formed along thecapacitor dielectric material 42. Thecapacitor electrode material 44 fills up the recess formed in theupper segment 40 c and thelower segment 40 d of the modifiedstorage node structure 40 and covers the entire surface of theupper lattice layer 28. Theportion 44 a ofcapacitor electrode material 44 on theupper lattice layer 28 may serve as a top electrode of the capacitor. Thecapacitor electrode material 44 is capacitively connected to the modifiedstorage node structure 40 through thecapacitor dielectric material 42. In this embodiment, thecapacitor dielectric material 42 may comprise any suitable composition or combination of compositions, such as one or both of silicon nitride and silicon dioxide. Thecapacitor electrode material 44 may comprise any suitable composition or combination of compositions, such as one or more of various metals (for instance, titanium, tungsten, etc.), metal-containing compositions (for instance, metal nitride, metal silicide, etc.) and conductively-doped semiconductor materials (for instance, conductively-doped silicon, conductively-doped germanium, etc.). The capacitor dielectric material and capacitor electrode material may be formed utilizing any suitable methods, including, for example, one or more of atomic layer deposition (ALD), chemical vapor deposition (CVD), and physical vapor deposition (PVD). - The embodiment of
FIG. 7 shows modified (partially thinned)storage node structure 40 incorporated into a capacitor comprising such storage node in combination withcapacitor dielectric material 42 andcapacitor electrode material 44. The capacitor may be utilized in combination with a transistor (which may correspond to the circuit in the substrate 12) to form a DRAM unit cell, and such unit cell may be representative of a large number of unit cells simultaneously formed and incorporated into a DRAM array. Additionally, a CMP process may be performed to remove theportion 44 a ofcapacitor electrode material 44 on theupper lattice layer 28 if the top electrode is unnecessary. - Please note that the capacitor structure shown in
FIG. 7 is single-sided. In other embodiment, it may also be double-sided design. Please refer toFIGS. 8-10 , which are cross-sectional views schematically depicting a process flow for manufacturing a double-sided capacitor structure in accordance with another embodiment of present invention. First, as shown inFIG. 8 , before removing theinner portion 38 b of the photoresist, a wet etching process may be performed to remove themultilayer 20 around the modifiedstorage node structure 40. As shown inFIG. 9 , the remaininginner portion 38 b in thestorage node structure 40 may be completely removed to expose the whole recess after themultilayer 20 is removed, thus both sidewalls of thestorage node structure 40 are exposed. - Subsequently, similar to the process shown in
FIG. 7 , acapacitor dielectric material 42 is conformally formed along the inner and outer surfaces of the modifiedstorage node structure 40, including theupper segment 40 c andlower segment 40 d, and subsequently a capacitor electrode material 44 (which may also be referred to as cell plate material) is formed along thecapacitor dielectric material 42. Thecapacitor electrode material 44 fills up the recesses formed in and between the modifiedstorage node structures 40 and covers the entire surface of theupper lattice layer 28. Thecapacitor electrode material 44 is capacitively connected to the modifiedstorage node structure 40 through thecapacitor dielectric material 42 from both sidewalls of protruding upper andlower segment - According to the above-mentioned method, a novel capacitor structure is also provided in the present invention. As shown in
FIG. 7 , the capacitor structure comprises asubstrate 12; amultilayer 20 over thesubstrate 12, wherein themultilayer 20 includes anisolation layer 14 on thesubstrate 12, at least onestack material layer 22/24 on theisolation layer 14, anupper lattice layer 28 on top of thestack material layer 24, and at least onelower lattice layer 26 in thestack material layer 22/24; a plurality of container-shapedstorage node structures 40 on thesemiconductor substrate 12 and surrounded by themultilayer 20, thestorage node structure 40 having a base, a sidewall extending upwardly from the base to the top of the storage node structure, wherein the sidewall includes anupper segment 40 c and alower segment 40 d thinner than theupper segment 40 c; acapacitor dielectric material 42 along a surface of eachstorage node structure 40; and acapacitor electrode material 44 over thecapacitor dielectric material 42, with the capacitor electrode material being capacitively coupled to the storage node structure through the capacitor dielectric material. - One essential feature of the present invention is that the storage node structure has a variable thickness. The scheme of variable thickness may increase the effective capacitor area and capacitance of the storage node structure without compromising the margin for the toppling issue. Furthermore, the design of dual or multiple lattice layers may provide enough support to prevent the capacitor electrodes from toppling issue and obtain better aspect ratio for the embedded type capacitor.
- Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
Claims (10)
1. A capacitor, comprising:
a substrate;
a multilayer over said substrate, wherein said multilayer comprises an isolation layer on said substrate, a stack material layer on said isolation layer, an upper lattice layer on top of said stack material layer, and at least one lower lattice layer in said stack material layer;
a plurality of container-shaped storage node structures on said semiconductor substrate and surrounded by said multilayer, said storage node structure having a base, a sidewall extending upwardly from said base to the top of said storage node structure, wherein said sidewall comprises an upper segment and a lower segment thinner than said upper segment;
a capacitor dielectric material along a surface of each said storage node structure; and
a capacitor electrode material over said capacitor dielectric material, with the capacitor electrode material being capacitively coupled to said storage node structure through said capacitor dielectric material.
2. The capacitor according to claim 1 , further comprising an implant region under each said storage node structure.
3. The capacitor according to claim 1 , wherein said at least one lower lattice layer is located between said upper segment and said lower segment.
4. The capacitor according to claim 1 , wherein the top surface of said storage node structure is coplanar with the top surface of said upper lattice layer.
5. The capacitor according to claim 1 , wherein the material of said upper lattice layer, said at least one lower lattice layer and said isolation layer comprises silicon nitride.
6. The capacitor according to claim 1 , wherein the material of said storage node structure comprises titanium nitride.
7. The capacitor according to claim 1 , wherein the material of said stack material layer comprises poly-silicon.
8. The capacitor according to claim 1 , wherein the height of said storage node structure is within a range from 15,000 Å to 20,000 Å.
9. The capacitor according to claim 1 , wherein the thickness of said upper segment is less than or equal to one-half of the thickness of said lower segment.
10. The capacitor according to claim 1 , wherein the thickness of said upper segment is less than 40 Å.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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US14/860,703 US20160013191A1 (en) | 2014-04-09 | 2015-09-21 | Capacitor and method of manufacturing the same |
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Application Number | Priority Date | Filing Date | Title |
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US14/249,340 US9230966B2 (en) | 2014-04-09 | 2014-04-09 | Capacitor and method of manufacturing the same |
US14/860,703 US20160013191A1 (en) | 2014-04-09 | 2015-09-21 | Capacitor and method of manufacturing the same |
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US14/249,340 Continuation US9230966B2 (en) | 2014-04-09 | 2014-04-09 | Capacitor and method of manufacturing the same |
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US14/249,340 Active US9230966B2 (en) | 2014-04-09 | 2014-04-09 | Capacitor and method of manufacturing the same |
US14/860,703 Abandoned US20160013191A1 (en) | 2014-04-09 | 2015-09-21 | Capacitor and method of manufacturing the same |
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US14/249,340 Active US9230966B2 (en) | 2014-04-09 | 2014-04-09 | Capacitor and method of manufacturing the same |
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CN (1) | CN104979163A (en) |
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Cited By (3)
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US10312241B1 (en) * | 2018-04-27 | 2019-06-04 | Micron Technology, Inc. | Integrated memory and integrated assemblies |
US20220045069A1 (en) * | 2020-08-06 | 2022-02-10 | Micron Technology, Inc. | Source/drain integration in a three-node access device for vertical three dimensional (3d) memory |
US11929280B2 (en) | 2020-09-22 | 2024-03-12 | Changxin Memory Technologies, Inc. | Contact window structure and method for forming contact window structure |
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US10020360B1 (en) * | 2017-01-06 | 2018-07-10 | Micron Technology, Inc. | Integrated memory |
CN107393909B (en) * | 2017-07-25 | 2018-11-16 | 长鑫存储技术有限公司 | Double sided capacitor and its manufacturing method |
US10290422B1 (en) * | 2017-11-16 | 2019-05-14 | Micron Technology, Inc. | Capacitors and integrated assemblies which include capacitors |
US11011523B2 (en) * | 2019-01-28 | 2021-05-18 | Micron Technology, Inc. | Column formation using sacrificial material |
US11049864B2 (en) * | 2019-05-17 | 2021-06-29 | Micron Technology, Inc. | Apparatuses including capacitor structures, and related memory devices, electronic systems, and methods |
US11264389B2 (en) * | 2020-06-03 | 2022-03-01 | Nanya Technology Corporation | Stack capacitor structure and method for forming the same |
US11688611B2 (en) * | 2020-07-20 | 2023-06-27 | Nanya Technology Corporation | Method for manufacturing a capacitor |
CN114256417A (en) * | 2020-09-22 | 2022-03-29 | 长鑫存储技术有限公司 | Capacitor structure and forming method thereof |
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Also Published As
Publication number | Publication date |
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TWI553885B (en) | 2016-10-11 |
US9230966B2 (en) | 2016-01-05 |
TW201539769A (en) | 2015-10-16 |
US20150294971A1 (en) | 2015-10-15 |
CN104979163A (en) | 2015-10-14 |
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