KR20050045715A - Method for manufacturing semiconductor device having recess channel mos transistor - Google Patents

Abstract

A semiconductor device having a recess channel MOS transistor is disclosed. Impurities are implanted into the semiconductor substrate to form the source / drain. A recess channel gate structure is formed in which a gate extends below the semiconductor substrate surface. An insulating layer filling the recess channel gate structure is formed. The insulating layer between the recess channel gate structures and the substrate surface exposed under the insulating layer are etched to form a recessed contact hole in the substrate. The substrate exposed under the recessed contact hole is etched isotropically to extend the exposed portion of the substrate. Subsequently, a contact is formed by filling a conductive material in the extended contact hole. Thus, the area of the contact interface can be increased to reduce the source / drain contact resistance.

Description

TECHNICAL FIELD A manufacturing method of a semiconductor device having a recess channel MOS transistor.

The present invention relates to a method of manufacturing a semiconductor memory device, and more particularly, to a method of manufacturing a memory device including a recess channel transistor.

As semiconductor devices are highly integrated, the gate length of the gate electrode of the MOS transistor is greatly reduced, and the spacing between the neighboring gate electrodes is also greatly reduced.

Transistors with traditional planar gates also reduce the channel length of the transistor as the gate length decreases. As the channel length of the transistor becomes smaller, the influence of the source and the drain on the electric field and potential in the channel region becomes remarkable, and the problems such as an increase in leakage current of the junction and a punch through of the source / drain are further exacerbated. In addition, as the width of the active region decreases, the width of the channel decreases, resulting in a narrow width effect, in which a threshold voltage increases.

In addition, the contact size electrically connected to the source / drain of the transistor becomes very narrow, so that the source / drain contact resistance becomes very large or the contact may be more likely to fail. Moreover, in recent years, since contact holes are formed in a self-aligned manner to form a contact connected to the source / drain, a spacer is provided on the side of the gate, and the contact interface size connected to the source / drain is further reduced.

 As an example of a method for reducing the contact resistance, a method of forming an undercut region by etching a substrate anisotropically after etching a source / drain node is disclosed in Korean Patent Application No. 2000-37231. However, the documents disclosed above are limited to planar gate structures. When the planar gate structure is adopted, the junction depth of the source / drain is very limited due to short channel effects and bulk leakage current. In particular, in semiconductor devices, the source / drain junction has become very thin in recent years. As described above, when a source / drain having a very thin junction depth is formed, there is a high possibility that the lower portion of the undercut region penetrates to the lower portion of the source / drain.

In addition, when forming a contact to be connected to a subsequent source / drain, impurities of the heavily doped polysilicon filled in the contact hole diffuse to the channel region, causing a defect in the semiconductor device. Therefore, it is not easy to apply the above process in practice.

Accordingly, an object of the present invention is to provide a method of manufacturing a semiconductor device including a cell transistor in which source / drain contact resistance is reduced and short channel effects are minimized.

The present invention to achieve the above object,

Implanting impurities into the semiconductor substrate for source / drain and channel formation;

Forming a recess channel gate structure in which a gate extends below the semiconductor substrate surface;

Forming an insulating layer filling the recess channel gate structure;

Etching the insulating layer between the recess channel gate structures and the substrate surface exposed under the insulating layer to form a contact hole in which the substrate is recessed;

Isotropically etching the substrate exposed under the recessed contact hole to expand the exposed portion of the substrate; And

And forming a contact by filling a conductive material in the extended contact hole.

As described above, the short channel effect may be minimized by providing the recess channel gate. In addition, the contact resistance can be reduced by forming an extended contact with the source / drain region.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1A to 1I are cross-sectional views illustrating a method of forming a cell transistor of a DRAM device according to an embodiment of the present invention.

Referring to FIG. 1A, a trench trench isolation process may be performed on an upper portion of a semiconductor substrate 100 to distinguish between an active region and a field region 100a.

A buffer oxide film 101 is formed on the substrate 100 to a thin thickness of about 100 microseconds. Next, an impurity ion implantation process for channel formation is performed, and an impurity 105 for forming a source / drain is implanted in consideration of a trench depth to be subsequently formed. The impurities 105 are implanted with Group 3 or 5 impurities, depending on the type of transistor to be formed. The junction depth of the impurities is formed to be 700 kPa or more. As in this embodiment, in a transistor having a recessed channel, the channel length is sufficiently long so that the short channel effect between the source and the drain is not taken into consideration, so that the impurities do not necessarily have a very thin junction depth as in the prior art. Therefore, the ion implantation may be performed to have a predetermined junction depth in consideration of the source / drain resistance and the impurity concentration of the transistor to be formed.

Referring to FIG. 1B, a first photoresist pattern 102 for defining a region where a recess gate is to be formed in the substrate 100 is formed. Subsequently, the substrate 100 is selectively etched using the first photoresist pattern 102 as a mask to form a gate trench 109. The gate trench 109 is formed to be limited to the active region. As the gate trench is formed, source / drain regions 106 are formed on both sides of the gate trench.

Referring to FIG. 1C, the first photoresist pattern 102 is removed by performing a conventional ashing strip process. Subsequently, the substrate 100 exposed by Chemical Dry Etch is selectively isotropically etched to remove the portion of the substrate not covered by the field oxide layer and not etched, and at the same time, the bottom edge portion of the gate trench 110. Rounding

Subsequently, although not shown, a thermal oxide film is formed to cure the damage generated when the gate trench 110 is etched.

Next, the thermal oxide film and the lower buffer oxide film 101 are simultaneously removed by a wet etching process.

Referring to FIG. 1D, a gate insulating layer 114 is formed on the side surface, the bottom surface of the gate trench 110, and the top surface of the substrate 100. The gate insulating layer 114 is preferably formed by oxidizing a silicon substrate. Therefore, it is not formed on the field region 100a.

Subsequently, the conductive layer 140 is formed to a predetermined thickness on the surface of the substrate 100 while filling the inside of the gate trench 110 in which the gate insulating layer 114 is formed. The conductive layer 140 includes a polysilicon layer 125 doped with impurities. Alternatively, the conductive film 140 may include a multilayer film including a metal film or a metal silicide film 135 stacked on the polysilicon film 125. Preferably, as shown, while filling the gate trench 110, the polysilicon film 125 is deposited on the substrate 100 by a predetermined thickness, and the metal silicide film (on the polysilicon film 125) is deposited. 135). This has the advantage that the step coverage property is very excellent in the polysilicon layer 125, and the gate resistance may be reduced by forming the metal silicide layer 135 on the polysilicon layer 125.

Subsequently, a hard mask film 150 is formed on the conductive film 140 as silicon nitride.

Referring to FIG. 1E, a second photoresist pattern 152 for patterning a gate electrode is formed on the hard mask layer 150. The second photoresist pattern 152 has a line type for masking a portion where the gate trench 110 is formed. In addition, the line width of the second photoresist pattern 152 should be larger than the line width of the gate trench 110.

Subsequently, the hard mask layer 150 is etched using the second photoresist pattern 152 as an etch mask to form a hard mask pattern 150a. Subsequently, the second photoresist pattern 152 is stripped. Thereafter, the conductive layer 140 is etched to expose the surface of the substrate 100 using the hard mask pattern 150a as an etch mask to form a polysilicon pattern 125a and a metal silicide pattern 135a. The pattern 140a is formed.

The process forms a recess channel gate structure 160 having a line shape extending in a direction perpendicular to the bottom of the trench and protruding from the substrate surface while filling the inside of the gate trench 110.

Referring to FIG. 1F, a thermal oxide layer (not shown) is formed to cure damage generated while the recess channel gate structure 160 is formed.

Subsequently, a silicon nitride film is deposited on the gate structure 160 and the substrate 100. In addition, the silicon nitride layer is etched anisotropically to form a spacer 162 on the side of the gate structure 160.

A semiconductor device employing a recess channel transistor according to an embodiment of the present invention is generally manufactured by a process having a design rule of 70 nm or less. In this case, the spacing between the exposed substrates between the gate structures is very narrow, less than 350 microns.

Referring to FIG. 1G, an interlayer insulating layer 164 is formed to fill the gate structure 160. The interlayer insulating layer 164 is formed of a silicon oxide layer using a process capable of buried without gaps between the narrow gaps between the gate structures 160.

Subsequently, a predetermined portion of the interlayer insulating layer 164 is etched to expose a surface of the substrate 100 corresponding to the source / drain 106, and the surface of the substrate 100 is further etched to a predetermined thickness to self-align contact. The hole 166 is formed. In detail, the self-aligned contact hole 166 is formed by over-etching the interlayer insulating layer 164 to partially recess the surface of the substrate 100.

Referring to FIG. 1H, a portion of the surface of the substrate 100 exposed under the self-aligned contact hole 166 is isotropically etched to extend a portion where the substrate 100 is exposed (166a). The isotropic etching of the substrate 100 may be performed by a chemical dry etching method.

When the self-aligned contact hole 166 in which a portion of the substrate is recessed is etched isotropically as described above, the exposed substrate portion is further extended in the vertical and horizontal directions. At this time, the area of the substrate exposed on the bottom surface of the extended contact hole 166a is an area where the contact to be formed by the subsequent process and the source / drain 106 contact. Therefore, even if the substrate spacing between the gate structures is very narrow, by extending the bottom of the contact hole 166a as described above, the area in which the source / drain 106 is contacted can be greatly increased.

At this time, the etching process conditions should be adjusted so that the bottom of the extended contact hole 166a does not extend further below the bottom of the source / drain 106 junction. That is, the bottom of the extended contact hole 166a should be formed higher than the bottom of the junction of the source / drain 106.

In addition, the extended contact hole 166a should be formed to be spaced apart from the gate structure 160 formed below the substrate surface by a predetermined distance.

After the formation of the extended contact hole 166a, an impurity implantation process for forming the source / drain 106 may be performed once more.

Referring to FIG. 1I, a conductive material is buried in the extended contact hole 166a and the conductive material is planarized to form a source / drain contact 170. The conductive material is deposited using a material and a process having excellent step coverage properties so that the conductive material can be sufficiently filled to the extended hole area under the substrate. The conductive material includes polysilicon.

By this process, the area of the source / drain contact interface is greatly increased. Therefore, problems such as an increase in resistance of the source / drain contacts or a source / drain contact open due to the source / drain contact interface area may be minimized. In addition, since the area in the horizontal direction is not required to increase the contact area of the source / drain contact, the design rule of the semiconductor device may be further reduced.

As described above, according to the present invention, the short channel effect can be minimized by forming the gate electrode of the MOS transistor to have a recess channel. In addition, the effect of raising the threshold voltage of the transistor and reducing the leakage current can be expected.

The interface of the contact connecting the source / drain of the transistor penetrates into the source / drain, and the area of the interface extends in the vertical and horizontal directions. Therefore, there is an effect that the contact resistance is greatly reduced.

Moreover, contact formation with an extended interface is very advantageous when employing a MOS transistor with the recess channel since the source / drain does not require very thin junction depths.

As described above, although described with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified without departing from the spirit and scope of the invention described in the claims below. And can be changed.

1A to 1I are cross-sectional views illustrating a method of forming a cell transistor of a DRAM device according to an embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

100: semiconductor substrate 100a: field region

102: first photoresist pattern 106: source / drain

110: gate trench 114: gate insulating film

140: conductive film 150: hard mast film

160 recess channel gate structure 162 spacer

164: interlayer insulating film 166a: extended contact hole

170: contact

Claims (7)

Implanting impurities to form sources / drains and channels in the semiconductor substrate; Forming a recess channel gate structure in which a gate extends below the semiconductor substrate surface; Forming an insulating layer filling the recess channel gate structure; Etching the insulating layer between the recess channel gate structures and the substrate surface exposed under the insulating layer to form a contact hole in which the substrate is recessed; Isotropically etching the substrate exposed under the recessed contact hole to expand the exposed portion of the substrate; And And embedding a conductive material in the extended contact hole to form a contact. The method of manufacturing a semiconductor device according to claim 1, wherein the impurity is implanted so that the junction depth of the impurity is 700 kPa or more. The method of claim 1, wherein the bottom of the extended contact hole is formed higher than the bottom of the junction of the impurity. The method of claim 1, wherein the extended contact hole is spaced apart from a gate formed under the surface of the substrate. The method of claim 1, wherein the isotropic etching of the substrate is performed by chemical dry etching. The method of claim 1, wherein the recess channel gate structure, Forming a trench below the substrate surface; Forming a gate oxide layer on the inner wall and the bottom of the trench; Forming a conductive film on a surface of the substrate while filling the trench; Forming a hard mask film on the conductive film; And Etching a predetermined portion of the hard mask layer and the conductive layer to form a recess channel gate electrode which extends in a direction perpendicular to the bottom of the trench and protrudes from the surface of the substrate while filling the inside of the trench; The manufacturing method of the semiconductor device characterized by the above-mentioned. The method of claim 1, further comprising forming a nitride spacer on a side of the recess channel gate structure.