KR20040037416A - Method for forming a self align contact and method for forming a MOS transistor having pad electrode using the same - Google Patents

Abstract

A self-aligned contact forming method and a method of forming a morph transistor including a pad electrode using the same are disclosed. On the silicon substrate, conductive structures including a conductive film pattern and a first nitride film pattern are formed on the uppermost layer. A first interlayer insulating film is formed to fill the space between the conductive structures. A second nitride film pattern having a width wider than that of the conductive film pattern is formed on the conductive film pattern. A second interlayer insulating film is formed on the second nitride film pattern and the first interlayer insulating film. A contact hole is formed to partially expose the substrate between the conductive structures. The doped silicon is grown by the selective epitaxial growth method in the vertical direction from the exposed substrate. Subsequently, the contact hole is filled with a conductive material to form a self-aligned contact. Therefore, the contact area is increased to reduce the contact resistance.

Description

Method for forming a self align contact and method for forming a MOS transistor having pad electrode using the same}

The present invention relates to a method of forming a self-aligned contact and a method of forming a MOS transistor including a pad electrode using the same. More particularly, the present invention relates to a method of forming a self-aligned contact having a reduced contact resistance, and a method of forming a MOS transistor including a pad electrode using the same.

As semiconductor devices become more integrated and faster, the formation of fine patterns is required, and not only the width of the wiring but also the space between the wiring and the wiring is significantly reduced. In particular, the formation of a contact connecting the isolated device regions formed in the semiconductor substrate with the use of a highly conductive thin film should be performed while securing the alignment margin, device isolation margin, and the like. To occupy. Thus, in a memory device such as a dynamic random access memory (DRAM), the contact serves as a major factor in determining the size of a memory cell.

Recently, semiconductor process technology of 0.25 μm or less has been rapidly developed, and it is difficult to form a contact having a fine size using a conventional contact forming method. Accordingly, a method of forming a contact by a self-aligned method in order to reduce the cell area when a design rule such as a memory cell has no margin and a pattern of the same shape is repeated has been developed.

Self-aligned contact technology is a method of forming a contact using a step of the surrounding structure, there is an advantage that does not require an alignment margin. A self-aligned contact process, which is currently used most, is to form a contact hole using a selectivity between an oxide film and a nitride film for an anisotropic etching process. Specifically, a nitride film spacer is formed on the sidewall of the structure formed adjacent to the position where the contact hole is to be formed, and an oxide film is formed to bury structures including the nitride film spacer. Subsequently, by etching the oxide film under a condition having a selectivity with respect to the nitride film spacer, a contact hole is formed between the nitride film spacers.

In the case of forming the contact hole by the above method, the thicker the thickness of the nitride spacer formed on the sidewall of the structure in the horizontal direction, the smaller the area of the contact portion is. By reducing the area of the contact portion, the contact resistance is increased and, in severe cases, an operation failure of the semiconductor device occurs. However, when the thickness of the nitride film spacer is reduced to increase the area of the contact portion, all of the nitride film spacers are etched during the contact hole forming process, thereby generating a bridge between the conductive material and the structure filled in the contact hole. Therefore, there is a limit in reducing the thickness of the nitride film spacer. In addition, as the design rules of the semiconductor are continuously reduced, the area of the bottom of the contact hole is further reduced, and the increase in contact resistance is more seriously generated.

As an example for minimizing the increase in the contact resistance, an epitaxial layer is formed on both sides of a gate electrode, impurity ions are implanted into the epitaxial layer, and the epitaxial layer is grown into polycrystalline silicon. This is disclosed in Korean Patent Laid-Open No. 2002-992848. According to this method, since the polycrystalline silicon must be grown to bury the gate electrode, the process time becomes very long. In addition, since the bonding structure becomes unstable at the interface region of the film grown in each epitaxial layer, there is a problem that a defect occurs in the polycrystalline silicon film.

Accordingly, a first object of the present invention is to provide a method for forming a self-aligned contact hole in which contact resistance is reduced.

It is a second object of the present invention to provide a method of forming a transistor including a pad electrode having a reduced contact resistance.

1A to 1H are cross-sectional views illustrating a method of forming a self-aligned contact according to a first embodiment of the present invention.

2A to 2M are cross-sectional views illustrating a semiconductor device including a pad electrode according to a second embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

100, 200: silicon substrate 104, 206: first nitride film pattern

106: conductive structure 208: gate structure

108, 210: etch stop film 216: oxide spacer

110, 224: first interlayer insulating film 114, 228: expanded opening

116 and 230: second nitride film pattern 118 and 232: second interlayer insulating film

122, 236: extended self-aligned contact hole 124, 240: doped silicon film

126: self-aligned contact 242: pad electrode

In order to achieve the first object described above, the present invention forms conductive structures including a conductive film pattern on a silicon substrate and a first nitride film pattern formed on an uppermost layer. An etch stop layer is formed on the surface of the conductive structures and the upper surface of the substrate. The etch stop layer is exposed on the upper surface, thereby forming a first interlayer insulating layer to fill the space between the conductive structures. A portion of the exposed etch stop layer and the first nitride layer pattern are partially etched, and a portion of the first interlayer insulating layer adjacent to the side surface of the first nitride layer pattern is etched to sequentially open an opening having a width wider than that of the conductive layer pattern. Form. The inside of the opening is filled with a nitride film to form a second nitride film pattern having a width wider than that of the conductive film pattern. A second interlayer insulating film is formed on the second nitride film pattern and the first interlayer insulating film. Selectively contacting the second interlayer insulating layer and the first interlayer insulating layer formed between the second nitride layer patterns, sequentially etching the etch stop layer, and partially contacting the substrate between the conductive structures Form. The doped silicon is grown by the selective epitaxial growth method in the vertical direction from the exposed substrate. Subsequently, a self-aligned contact is formed by filling a contact hole in which the doped silicon is formed with a conductive material.

In order to achieve the above-described second object, the present invention forms gate structures in which a gate oxide layer pattern, a conductive layer pattern, and a first nitride layer pattern are stacked on a silicon substrate. An etch stop layer is formed on the surface of the conductive structures and the upper surface of the substrate. A low concentration of impurity ions are implanted into the entire surface of the substrate on which the etch stop layer is formed to form a low concentration source and drain region under the substrate between the conductive structures. An oxide spacer is formed on side surfaces of the gate structure in which the etch stop layer is formed. A low concentration of impurity ions are further implanted into the substrate on which the oxide film spacer is formed to form a high concentration source and drain region under the substrate between the oxide film spacers. The oxide spacer is removed. The etch stop layer is exposed on the upper surface to form a first interlayer insulating layer to fill the space between the conductive structures. Etching a portion of the exposed etch stop layer and the first nitride layer pattern and sequentially etching a portion of the first interlayer insulating layer adjacent to the side surface of the first nitride layer pattern to form an opening having a width wider than that of the conductive layer pattern. do. The inside of the opening is filled with a nitride film to form a second nitride film pattern having a width wider than that of the conductive film pattern. A second interlayer insulating film is formed on the second nitride film pattern and the first interlayer insulating film. Selectively contacting the second interlayer insulating layer and the first interlayer insulating layer formed between the second nitride layer patterns, sequentially etching the etch stop layer, and partially contacting the substrate between the conductive structures Form. The doped silicon is grown by the selective epitaxial growth method in the vertical direction from the exposed substrate. Subsequently, the contact hole in which the doped silicon is formed is filled with a conductive material to form a MOS transistor including a pad electrode.

Since the self-aligned contact and the pad electrode are formed in contact with the polysilicon grown in the vertical direction, the area of the contact portion is increased. As a result, contact resistance may be reduced to minimize defects of the semiconductor device including the self-aligned contact and the pad electrode.

Hereinafter, the self-aligned contact forming method of the present invention will be described in more detail.

1A to 1H are cross-sectional views illustrating a method of forming a self-aligned contact according to a first embodiment of the present invention.

Referring to FIG. 1A, conductive structures 106 including conductive layer patterns 102 and a first nitride layer pattern 104 are formed on an uppermost layer are formed on the silicon substrate 100. The conductive structure 106 includes a gate electrode or a line for signal transmission. Subsequently, an etch stop layer 108 is formed on the surface of the conductive structure 106 and the upper surface of the substrate.

Referring to FIG. 1B, an insulating material is formed to bury a space between the conductive structures 106 on which the etch stop film 108 is formed, and then the insulating material is exposed so that the etch stop film 108 is exposed to an upper surface thereof. The first interlayer insulating layer 110 may be formed to fill the space between the conductive structures 106. The first interlayer insulating layer 110 is formed of a silicon nitride layer and a silicon oxide layer having an etching selectivity under a predetermined etching condition.

Referring to FIG. 1C, the exposed etch stop layer 108 is etched, and the first nitride layer pattern is sequentially left on the conductive layer pattern 102 while leaving the first nitride layer pattern 104a by a predetermined thickness. Etch 104a. The etch stop layer 108 and the first nitride layer pattern 104a are wet etched using H ₂ PO ₄ solution. When the above process is performed, an opening 112 is formed in the portion where the first nitride film pattern 104a is formed, since the step is reduced compared to the periphery.

Referring to FIG. 1D, the first interlayer insulating layer 110 exposed on the surface of the substrate including the opening 112 is isotropically etched by a predetermined thickness to have a width wider than the width of the conductive layer pattern 102. An expanded opening 114 having a diameter. At this time, the first nitride film pattern 104a remaining on the conductive film pattern is hardly etched to prevent the conductive film pattern 102 from being damaged by the etching process.

Referring to FIG. 1E, a silicon nitride is buried in the expanded opening 114 and etched back to form a second nitride film having a width wider than that of the conductive film pattern 102 on the conductive film pattern 102. Patterns 116 are formed. In this case, the second nitride film patterns 116 are kept at a predetermined interval from each other, and the first interlayer insulating film 110 is formed between the second nitride film patterns 116.

Referring to FIG. 1F, a second interlayer insulating layer 118 is formed on the second nitride layer pattern 116 and the first interlayer insulating layer 110. Subsequently, the second interlayer insulating layer 118 and the first interlayer insulating layer 110 positioned between the second nitride layer patterns 116 are selectively etched, and the etch stop layer 108 is sequentially etched, thereby The self-aligned contact hole 120 partially exposing the substrate between the conductive film patterns 102 is formed.

Referring to FIG. 1G, the first and second interlayer insulating films 118 and 110 exposed on the surface of the resultant are isotropically etched by a predetermined thickness to extend the size of the self-aligned contact hole 122 in the horizontal direction. . Next, the doped silicon film 124 is grown in a vertical direction from the silicon substrate exposed to the bottom surface of the extended self-aligned contact hole 122 by a selective epitaxial growth method.

Referring to FIG. 1H, polysilicon is buried in the self-aligned contact hole 122 where the doped silicon layer 124 is formed and etched back to form a self-aligned contact 126.

The contact is not in contact with the surface of the substrate but in contact with the side and top surfaces of the silicon film formed in a vertical direction from the surface of the substrate. As a result, the contact area is greatly increased compared to the conventional contact with the substrate surface, and the contact resistance is greatly reduced.

2A to 2M are cross-sectional views illustrating a semiconductor device including a pad electrode according to a second embodiment of the present invention.

Referring to FIG. 2A, a silicon substrate 200 provided to form a semiconductor device may include a cell region in which cells as one memory element is formed, and a core and a ferry in which peripheral circuits for operating the cells are formed. and transistors having different operating characteristics for each substrate region.

An active device isolation process is performed on the silicon substrate 200 to form the active and field 200a. Subsequently, an ion doping process for adjusting the threshold voltage of the transistor is performed. A gate structure 208 having a structure in which the gate insulating layer pattern 202, the conductive layer pattern 204, and the first nitride layer pattern 206 are stacked is formed on the substrate 200 on which the process is performed. The length of the gate structure 208 may be formed differently in each region. In general, the length l1 of the gate structure 208 formed in the cell region is smaller than the length l2 of the gate structure 208 formed in the ferry region. This is because the ferry region has a lower integration degree than the cell region in which the elements are repeatedly formed, and the voltage applied to the formed elements is higher.

Referring to FIG. 2B, an etch stop layer 210 is formed on the entire surface of the gate structure 208 and the substrate 200. The etch stop layer 210 is formed of a silicon nitride layer, for example, a Si ₃ N ₄ layer. At this time, the etch stop layer 210 is preferably formed to a thin thickness of about 100 to 300Å.

Subsequently, a low concentration of impurities are implanted 211 under the surface of the substrate between the gate structures 208 to form low concentration source and drain regions 212a and 214a.

Referring to FIG. 2C, a silicon oxide film is formed on a surface of the etch stop layer 210, and the silicon oxide film is anisotropically etched to form an oxide spacer 216 on a side surface of the gate structure including the etch stop layer 210. ). In this case, the anisotropic etching process is performed under a condition having an etching selectivity with the etching stop film 210 so that the previously formed etching stop film 210 is not consumed. The remaining etch stop layer 210 may prevent damage to the substrate surface during the subsequent impurity implantation process. The oxide spacer 216 is formed to define a region in which impurities are implanted in a subsequent impurity implantation process.

That is, when the oxide spacer 216 is thick, the area of the substrate between the oxide spacers 216 is reduced to reduce the impurity implantation region, and conversely, when the oxide spacer 216 is thin, between the oxide spacers 216 is thin. The area of the substrate becomes relatively large, and the impurity implantation region also increases. Therefore, the thickness of the oxide spacer 216 is determined in consideration of operating characteristics of the cell transistor to be formed, for example, a threshold voltage and a drain saturation current.

Subsequently, a first photoresist pattern 218 is formed on the core / ferry region of the substrate to mask the core / ferry region, and a low concentration of impurity ions are selectively implanted into the cell region 219 to provide LDD. Source and drain regions 212 of the structure are formed.

Referring to FIG. 2D, the oxide spacer 216a is isotropically etched by a predetermined thickness so that the thickness of the oxide spacer 216a becomes thinner. As the thickness of the oxide spacer 216a is thinner, more regions in which impurities are implanted in a subsequent process are increased, so that source and drain regions of high concentration are increased by the isotropic etching.

As described above, when the source and drain regions of high concentration are increased, the drain saturation current Ids is increased to improve the operating characteristics of the transistor. However, in the cell region, a short channel phenomenon occurs because the gate electrode has a shorter length than the core / ferry region. Thus, the source and drain regions of the high concentration cannot be increased in the same manner as the core / ferry region.

Subsequently, a second photoresist pattern 220 is formed on the cell region of the substrate to selectively mask the cell region, and selectively implant a low concentration of impurity ions only into the core / ferry region to form an LDD structure. Source and drain regions 214 are formed.

The process may be performed by selectively masking the cell region first, followed by an isotropic etching process and an impurity implantation process.

Referring to FIG. 2E, the oxide spacers 216a remaining on both sidewalls of the gate structure 208 are completely removed by an isotropic etching process. In this case, the oxide spacer 216a is etched with the etch stop layer 210 with an etching selectivity. When the oxide spacer 216a is removed, the gap between the gate structures 208 and the etch stop layer 210 is widened by about twice the thickness of the oxide spacer 216a. Therefore, in the subsequent step, the first interlayer insulating film can be buried without voids.

Referring to FIG. 2F, silicon oxide is deposited between the gate structures 208. Subsequently, the silicon oxide is chemically polished to expose the surface of the etch stop layer 210 formed on the gate structure 208 to form a first interlayer insulating layer 224. The chemical mechanical polishing process is performed using a slurry having a selectivity to the nitride film so that the polishing rate of the nitride film is very slow compared to the oxide film.

Referring to FIG. 2G, the exposed etch stop layer 210 is etched and the first nitride layer pattern is sequentially left on the conductive layer pattern 204 by a predetermined thickness. 206a is etched to form openings 226. In this case, the first interlayer insulating layer 224 formed of the silicon oxide is performed using a wet etchant having a selectivity with respect to the silicon oxide layer so that the first interlayer insulating layer 224 is hardly etched. The etchant includes, for example, a H ₂ PO ₄ solution.

Referring to FIG. 2H, the exposed first interlayer insulating layer 224 is selectively isotropically etched by a predetermined thickness to form an opening 228 extending in the horizontal direction. At this time, the first nitride film pattern 206a remains on the bottom surface of the extended opening 228, and the first nitride film pattern 206a is hardly consumed by the isotropic etching. When the width of the openings 228 is extended by the isotropic etching, the gap between the openings 228 is reduced. As the spacing between the openings 228 is reduced, the size of the self-aligned contact holes formed in subsequent processes is also reduced. Therefore, the amount of the first interlayer insulating layer 224 to be etched in the process is determined in consideration of the contact resistance with the source / drain and the gap between the contact and the gate structure 208.

Referring to FIG. 2I, silicon nitride is buried in the extended opening 228 and etched back so that the silicon nitride remains only in the extended opening 228, so that the conductive layer pattern 204 is electrically conductive. A second nitride film pattern 230 having a wider width than that of the film pattern 204 is formed. The etch back process includes an anisotropic dry etching or chemical mechanical polishing process. The second nitride film pattern 230 serves as an etch mask when forming a subsequent self-aligned contact hole.

Referring to FIG. 2J, a second interlayer insulating layer 232 is formed on upper surfaces of the second nitride layer pattern 230 and the first interlayer insulating layer 224.

A photoresist pattern (not shown) is formed on the second interlayer insulating layer 232 to include an upper portion between the second nitride layer patterns 230 in an open area. Subsequently, the second interlayer insulating film 232 and the first interlayer insulating film 224 formed between the second nitride film pattern 230 are selectively etched under conditions having a selectivity with respect to the nitride film, and the etch stop is sequentially performed. The film 210 is etched to form a self-aligned contact hole 234 exposing top surfaces of the source and drain regions 212.

Referring to FIG. 2K, the first and second interlayer insulating layers 224 and 232 exposed to the surface of the resultant are isotropically etched by a predetermined thickness to form a self-aligned contact hole 236 extending in the horizontal direction. . In this case, an isotropic etching process is performed while having a predetermined margin so that the extended self-aligned contact hole 236 and the conductive layer pattern 204 do not directly contact each other. By extending the self-aligned contact hole 236, the resistance of the pad electrode in contact with the source and drain regions 212 may be reduced.

Referring to FIG. 2L, silicon doped with impurities in a direction perpendicular to the source and drain regions 212 exposed at the bottom of the extended self-aligned contact hole 236 is selectively epitaxially grown.

Specifically, a portion of the etch stop layer 210 remains at the edge portion of the bottom of the extended self-aligned contact hole 236, and the silicon substrate is exposed at the center portion. Accordingly, the doped silicon is selectively epitaxially grown using the exposed silicon substrate as a seed. When silicon is grown by the epitaxial growth method, the silicon film 240 doped only in the vertical direction is formed from the exposed silicon substrate.

Referring to FIG. 2M, polysilicon is deposited to bury the self-aligned contact hole 236 having the doped silicon layer 240 formed on the bottom thereof. Subsequently, the polysilicon is etched back so that the polysilicon is filled only in the self-aligned contact hole 236 to form pad electrodes 242 electrically connected to the source / drain regions 212.

In this case, the pad electrode 242 is not in contact with the surface of the substrate but in contact with the side and top surfaces of the doped silicon layer 240 formed in a vertical direction from the surface of the substrate. Therefore, the contact area of the pad electrode 242 is greatly increased as compared with the conventional contact with the surface of the substrate and electrically connected to the source / drain region 212. As a result, a contact resistance between the pad electrode 242 and the source and drain regions 212 may be greatly reduced, thereby minimizing a malfunction of the transistor.

In the drawing and description of the second embodiment, the pad electrode is formed only in the cell region, but may be formed in the core / ferry region in the same manner. However, since the core / ferry region has a larger pattern size and a lower integration density than the cell region, the pad electrode forming process by the self-aligning method is more useful for a transistor formed in a cell region having a small size and high integration patterns. Can be applied.

As described above, according to the present invention, the contact resistance between the pad electrode and the source and drain regions is greatly reduced, thereby minimizing the malfunction of the transistor. In addition, since the first interlayer insulating layer may be formed without the voids between the gate structures, process defects caused by the voids may be prevented.

As described above, although described with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified without departing from the spirit and scope of the invention described in the claims below. And can be changed.

Claims (12)

i) forming conductive structures on the silicon substrate, the conductive structures including a conductive film pattern and a first nitride film pattern formed on an uppermost layer; ii) forming an etch stop film made of a nitride film on the surface of the conductive structure and the upper surface of the substrate; iii) forming a first interlayer insulating layer to fill the space between the conductive structures while the etch stop layer is exposed on the top surface; iv) a portion of the exposed etch stop layer and the first nitride layer pattern are etched, and a portion of the first interlayer insulating layer adjacent to the side surface of the first nitride layer pattern is sequentially etched to form a width wider than the width of the conductive layer pattern. Forming an opening having; v) filling the inside of the opening with a nitride film to form a second nitride film pattern having a width wider than that of the conductive film pattern; vi) forming a second interlayer insulating film on the second nitride film pattern and the first interlayer insulating film; vii) A contact selectively etching the second interlayer insulating film and the first interlayer insulating film formed between the second nitride film patterns, and sequentially etching the etch stop layer to partially expose the substrate between the conductive structures. Forming a hole; viii) growing doped silicon by selective epitaxial growth in a vertical direction from the exposed substrate; And ix) A method of forming a self-aligned contact, the method comprising: filling a contact hole in which the doped silicon is formed with a conductive material. According to claim 1, wherein step iv), Etching the etch stop layer, and sequentially etching the first nitride layer pattern while leaving the first nitride layer pattern on the conductive layer pattern by a predetermined thickness; And isotropically etching the first interlayer insulating film exposed to the portion where the first nitride film pattern is etched by a predetermined thickness. The method of claim 2, wherein the etching of the first nitride layer pattern is performed by a wet etching method using a H ₂ PO ₄ solution. The method of claim 1, further comprising, after performing step vii), expanding the contact hole by isotropically etching the first and second interlayer insulating layers exposed to the surface by a predetermined thickness. How to form an align contact. The method of claim 1, wherein the conductive structure comprises a gate electrode or a signal transmission line. i) forming gate structures on which the gate oxide layer pattern, the conductive layer pattern, and the first nitride layer pattern are stacked on the silicon substrate; ii) forming an etch stop film made of a nitride film on the surface of the conductive structures and the upper surface of the substrate; iii) implanting low concentration of impurity ions into the entire surface of the substrate on which the etch stop layer is formed, thereby forming a low concentration source and drain region under the substrate between the conductive structures; iv) forming oxide spacers on side surfaces of the gate structure on which the etch stop layer is formed; v) further implanting low concentration of impurity ions into the substrate on which the oxide film spacer is formed to form a high concentration source and drain region under the substrate between the oxide film spacers; vi) removing the oxide spacers; vii) forming a first interlayer insulating layer to fill the space between the conductive structures while the etch stop layer is exposed on the top surface; viii) etching the portions of the exposed etch stop layer and the first nitride layer pattern, and sequentially etching a portion of the first interlayer insulating layer adjacent to the side surface of the first nitride layer pattern, thereby forming a width wider than the width of the conductive layer pattern. Forming an opening having; ix) filling the inside of the opening with a nitride film to form a second nitride film pattern having a width wider than that of the conductive film pattern; x) forming a second interlayer insulating film on the second nitride film pattern and the first interlayer insulating film; xi) A contact selectively etching the second interlayer insulating film and the first interlayer insulating film formed between the second nitride film patterns, and sequentially etching the etch stop layer to partially expose the substrate between the conductive structures. Forming a hole; xii) growing doped silicon by selective epitaxial growth in a vertical direction from the exposed substrate; And xiii) A method of forming a MOS transistor comprising a pad electrode, wherein the contact hole in which the doped silicon is formed is filled with a conductive material. The method of claim 6, wherein in step i), a length of the gate structure and a distance between the gate structures in the substrate are differently formed for each region. The method of claim 6, wherein in step v), the thickness of the oxide spacer according to the length of the gate structure and the distance of each gate structure is adjusted to form different areas of the source / drain regions of high concentration. A method of forming a MOS transistor comprising a pad electrode. The method of claim 8, wherein step v), Selectively implanting impurity ions under the substrate between the oxide spacers only in a region where the gate structure has a relatively short length; Isotropically etching the oxide spacer formed on the side of the gate structure by a predetermined thickness to form an oxide spacer having a reduced thickness; And selectively implanting impurity ions under an exposed substrate between the oxide spacers having a reduced thickness, selectively in a region where the gate structure has a relatively long length. Method of formation. The method of claim 6, wherein step viii), Etching the etch stop layer, and sequentially etching the first nitride layer pattern while leaving the first nitride layer pattern on the conductive layer pattern by a predetermined thickness; And isotropically etching the first interlayer insulating film exposed to the portion where the first nitride film pattern is etched by a predetermined thickness. The method of claim 10, wherein the etching of the first nitride layer pattern is performed by a wet etching method using a H ₂ PO ₄ solution. The MOS transistor of claim 6, further comprising isotropically etching the exposed first and second interlayer insulating layers by a predetermined thickness after the step xi) to extend the size of the contact hole. Forming method.