KR100745894B1 - Method for forming recess gate of semiconductor device - Google Patents

Method for forming recess gate of semiconductor device Download PDF

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Publication number
KR100745894B1
KR100745894B1 KR1020050058192A KR20050058192A KR100745894B1 KR 100745894 B1 KR100745894 B1 KR 100745894B1 KR 1020050058192 A KR1020050058192 A KR 1020050058192A KR 20050058192 A KR20050058192 A KR 20050058192A KR 100745894 B1 KR100745894 B1 KR 100745894B1
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South Korea
Prior art keywords
recess gate
region
forming
gate
semiconductor substrate
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KR1020050058192A
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Korean (ko)
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KR20070002590A (en
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서문식
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주식회사 하이닉스반도체
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Priority to KR1020050058192A priority Critical patent/KR100745894B1/en
Publication of KR20070002590A publication Critical patent/KR20070002590A/en
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/108Dynamic random access memory structures
    • H01L27/10805Dynamic random access memory structures with one-transistor one-capacitor memory cells
    • H01L27/10823Dynamic random access memory structures with one-transistor one-capacitor memory cells the transistor having a trench structure in the substrate
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/108Dynamic random access memory structures
    • H01L27/10844Multistep manufacturing methods
    • H01L27/10847Multistep manufacturing methods for structures comprising one transistor one-capacitor memory cells
    • H01L27/1085Multistep manufacturing methods for structures comprising one transistor one-capacitor memory cells with at least one step of making the capacitor or connections thereto
    • H01L27/10852Multistep manufacturing methods for structures comprising one transistor one-capacitor memory cells with at least one step of making the capacitor or connections thereto the capacitor extending over the access transistor
    • H01L27/10855Multistep manufacturing methods for structures comprising one transistor one-capacitor memory cells with at least one step of making the capacitor or connections thereto the capacitor extending over the access transistor with at least one step of making a connection between transistor and capacitor, e.g. plug
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/108Dynamic random access memory structures
    • H01L27/10844Multistep manufacturing methods
    • H01L27/10847Multistep manufacturing methods for structures comprising one transistor one-capacitor memory cells
    • H01L27/10882Multistep manufacturing methods for structures comprising one transistor one-capacitor memory cells with at least one step of making a data line
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312Gate electrodes for field effect devices
    • H01L29/42316Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356Disposition, e.g. buried gate electrode
    • H01L29/4236Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568Lateral single gate silicon transistors
    • H01L29/66613Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66621Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a recess gate of a semiconductor device, wherein the recess gate mask is misaligned in a direction of a storage electrode region to form an asymmetric structure, thereby increasing the gate sidewall oxide layer of the storage electrode region to reduce leakage current due to a decrease in electric field. The present invention provides a technique of improving the electrical characteristics by minimizing the variation of Vt and Rc due to misalignment by reducing the gate sidewall oxide layer of the bit line region.

Description

Recess gate formation method of a semiconductor device {METHOD FOR FORMING RECESS GATE OF SEMICONDUCTOR DEVICE}

1 and 2 are a plan view and a cross-sectional view showing a recess gate forming method of a semiconductor device according to the prior art.

3 is a plan view showing a recess gate forming method of a semiconductor device according to the present invention;

4A to 4E are cross-sectional views illustrating a method of forming a recess gate in a semiconductor device according to the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a recess gate of a semiconductor device, wherein the recess gate mask is misaligned in a direction of a storage electrode region to form an asymmetric structure, thereby increasing the gate sidewall oxide layer of the storage electrode region to reduce leakage current due to a decrease in electric field. The present invention provides a technique of improving the electrical characteristics by minimizing the variation of Vt and Rc due to misalignment by reducing the gate sidewall oxide layer of the bit line region.

1 and 2 are plan and cross-sectional views illustrating a method of forming a recess gate of a semiconductor device according to the related art.

Referring to FIG. 1, a gate line 3 is formed on a semiconductor substrate including an active region 1, and a recess gate mask 5 is formed on the gate line 3.

Referring to FIG. 2, the cutting line ⓐ-ⓐ ′ of FIG. 1 is illustrated, and a recess gate region misaligned in the bit line region direction is formed on the semiconductor substrate 10 having the device isolation layer 15. Next, a stacked structure of the polysilicon layer 25, the tungsten silicide layer 30, and the hard mask layer 35 filling the recess gate region is formed, and the stacked structure is etched to form a recess gate electrode. .

An oxide spacer 40 may be formed on the sidewalls of the recess gate electrode, but the oxide layer may be formed to increase in the misaligned portion of the bit line region.

Next, a nitride film spacer 45 is formed on sidewalls of the recess gate electrode and the hard mask layer 35, and a contact plug 50 is formed by filling a region exposed by the nitride film spacer 45 with an insulating film.

In the above-described method of forming a recess gate of a semiconductor device according to the related art, a misalignment occurs between the gate electrode and the recess gate region when the recess gate is formed, thereby reducing the oxide film on the sidewall of the storage electrode region, thereby increasing the leakage current due to the increase of the electric field. In addition, there is a problem that Vt and Rc increase due to an increase in the oxide film on the sidewalls of the bit line region.

In order to solve the above problem, the recess gate mask is misaligned toward the storage electrode region to form an asymmetric structure, thereby increasing the gate sidewall oxide layer of the storage electrode region to prevent leakage current due to the reduction of the electric field, thereby improving refresh characteristics. It is an object of the present invention to provide a method for forming a semiconductor device in which the gate sidewall oxide film of the bit line region is reduced to minimize the change of Vt and Rc due to misalignment, thereby improving electrical characteristics.

Recess gate forming method of a semiconductor device according to the present invention
Forming a well and a threshold voltage control region on the semiconductor substrate including the device isolation layer;
Etching the semiconductor substrate to a predetermined depth to form a recess gate region, wherein the recess gate region is misaligned so as to be biased toward the storage electrode region;
Forming a stacked structure of a polysilicon layer, a gate metal layer, and a gate hard mask layer filling the recess gate region;
Etching the stacked structure to form a recess gate pattern, wherein the misaligned recess gate region is partially exposed;
Forming an oxide film and forming a source / drain junction on the exposed recess gate region, the recess gate sidewall and the surface of the semiconductor substrate; And
Forming a contact plug on a sidewall of the recess gate and then filling a exposed semiconductor substrate; To include,
The recess gate region is formed to a depth of 50 to 2500Å,

The recess gate misalignment width is 0.1 to 0.5 times the gate line width.

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Hereinafter, with reference to the accompanying drawings an embodiment of the present invention will be described in detail.

3 is a plan view illustrating a recess gate mask of the present invention.

Referring to FIG. 3, a gate line 80 is formed on a semiconductor substrate including an active region 60, and a recess gate mask 70 is formed on the gate line 80.

Here, the recess gate mask 70 may have a width misaligned by 0.1 to 0.5 times the gate line width in the storage electrode region 35 direction.

4A to 4E are cross-sectional views illustrating a semiconductor device and a method of forming the semiconductor device according to the present invention, and illustrates a cut surface of ⓑ-ⓑ 'of FIG.

Referring to FIG. 4A, a well and a threshold voltage adjusting region are formed on the semiconductor substrate 100 provided with the device isolation layer 110.

Referring to FIG. 4B, a photoresist pattern 120 defining a recess gate region is formed on the semiconductor substrate 100, and the recessed substrate region is etched by a predetermined depth using the photoresist pattern 120 as a mask. To form.

Here, the recess gate region may be formed by etching to a depth of 500 to 2500 시켜 by misaligning the gate line width by 0.1 to 0.5 times in the direction of the storage electrode region than the recess gate region formed in the related art.

Referring to FIG. 4C, a gate oxide layer 140 is formed on an entire surface of the semiconductor substrate 100 including the recess gate region, and the polysilicon layer 150 and the gate metal layer 160 filling the recess gate region are buried. And forming a stacked structure of the gate hard mask layer 170 and then etching the stacked structure to form a recess gate.

In this case, since the recess gate region is misaligned as shown in FIG. 4B, the polysilicon layer 150 may be partially exposed to the recess gate region in the direction of the storage electrode region when the recess gate is etched.

Referring to FIG. 4D, after forming the first spacer 180 on the semiconductor substrate 100 and the recess gate sidewall, the source / drain region 185 is formed.

Here, the first spacer 180 is formed of a silicon oxide film so that the exposed recess gate region is buried, and is formed on the surface of the semiconductor substrate 100, the polysilicon layer 150, and the gate metal layer 160.

Referring to FIG. 4E, a second spacer 190 is formed on sidewalls of the recess gate and the semiconductor substrate 100, and the semiconductor substrate 100 exposed by the second spacer 190 is etched to a predetermined depth. The exposed area is filled to form the contact plug 200.

The second spacer 190 may be formed of a nitride film, and the contact plug 200 may be formed of an n-type polysilicon layer.

 5 is a cross-sectional view illustrating a method of forming a recess gate according to another exemplary embodiment of the present invention.

Referring to FIG. 5, a recess gate region in a bit line region direction is formed as an outer gate structure on the semiconductor substrate 200 having the active region 210, and a recess gate in the storage electrode region direction is aligned. Recessed gate regions are formed.

Next, a gate oxide film 220 is formed on the entire surface of the semiconductor substrate 200 including the recess gate region, and the polysilicon layer 230, the gate metal layer 240, and the hard mask filling the recess gate region are filled. After forming the stacked structure of the layer 250, the stacked structure is etched.

Next, after forming the oxide spacer 260 on the sidewalls of the polysilicon layer 230 and the gate metal layer 240, the nitride spacer 270 is formed on the sidewalls of the oxide spacer 260 and the hard mask layer 250.

Here, it is preferable that the width of the recess gate region is reduced and an asymmetric recess gate is formed.

In the method of forming a recess gate of a semiconductor device according to the present invention, the recess gate mask is misaligned toward the storage electrode region to form an asymmetric structure, thereby increasing the gate sidewall oxide layer of the storage electrode region to prevent leakage current due to a decrease in electric field. The refresh characteristic is improved, and the gate sidewall oxide layer of the bit line region is reduced to minimize the change of Vt and Rc due to misalignment, thereby improving electrical characteristics.

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Claims (3)

  1. Forming a well and a threshold voltage control region on the semiconductor substrate including the device isolation layer;
    Etching the semiconductor substrate to a predetermined depth to form a recess gate region, wherein the recess gate region is misaligned so as to be biased toward the storage electrode region;
    Forming a stacked structure of a polysilicon layer, a gate metal layer, and a gate hard mask layer filling the recess gate region;
    Etching the stacked structure to form a recess gate pattern, wherein the misaligned recess gate region is partially exposed;
    Forming an oxide film and forming a source / drain junction on the exposed recess gate region, the recess gate sidewall and the surface of the semiconductor substrate; And
    Forming a contact plug on the sidewall of the recess gate and then filling the exposed semiconductor substrate
    Recess gate forming method of a semiconductor device comprising a.
  2. The method of claim 1,
    And the recess gate region is formed to a depth of 50 to 2500 microns.
  3. The method of claim 1,
    And the recess gate misalignment width is 0.1 to 0.5 times the gate line width.
KR1020050058192A 2005-06-30 2005-06-30 Method for forming recess gate of semiconductor device KR100745894B1 (en)

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