KR20100028435A - Method for fabricating semiconductor device having saddle fin transistor - Google Patents

Abstract

PURPOSE: A method for manufacturing a semiconductor device including a saddle fin transistor is provided to secure the property of the semiconductor device and a process margin by preventing the contact between a poly-silicon layer and a landing plug contact. CONSTITUTION: Gate electrodes(510) are formed on a semiconductor substrate. An insulation layer(530) covers the gate electrodes. The area in which a contact is formed in the insulation layer is etched to expose an active area and an element isolation layer(502) between the gate electrodes. The exposed element isolation layer is etched to form a cavity. An insulation layer is formed on the surface of the cavity. A landing plug is contacted to the active area.

Description

Method for fabricating semiconductor device having saddle fin transistor {Method for fabricating semiconductor device having saddle Fin transistor}

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device having a saddle fin transistor.

Recently, as the design rule of a semiconductor device is rapidly reduced to a level below sub-50 nm, the area of the active region in which the device can be formed is rapidly decreasing. As a result, deterioration of cell operating current characteristics is the biggest obstacle to the development of the device, and such deterioration of cell operating current characteristics is the root cause of the tWR failure. In order to secure the cell operating current, reduction of the Rc and Rs of the cell junction region and the plug region must be accompanied, and a more expanded current path is required. As the current current path decreases, i.e., the width of the active region decreases, it is virtually impossible to secure a cell driving current for the operation of the ultra-high density device. In order to overcome this limitation, various transistor structures have been proposed.

1 is a perspective view illustrating a fin transistor structure, which is one of techniques proposed to secure a current driving capability of a semiconductor device.

In Fig. 1, reference numeral 100 denotes a semiconductor substrate, 102 denotes a field oxide film, 110 denotes a gate electrode, and S and D denote a source and a drain, respectively. The transistor having a fin structure protrudes the semiconductor substrate of the portion where the channel is to be formed in the vertical direction to form the active region 100a, and forms a gate electrode 110 crossing the active region 100a of the semiconductor substrate thereon. Three surfaces of the semiconductor substrate surrounded by the gate electrode 110 may be used as a channel of a transistor. In this case, when the fin-type transistor is applied, three surfaces are used as the channel, thereby greatly improving the current driving capability of the memory device. However, in the case of the fin structure, since the three-sided channel may increase the source of the junction leakage current, it is disadvantageous in terms of securing the information storage time, which is applied to a cell transistor that requires sufficient information storage time. There is a limit to what you do.

2 is a cross-sectional view illustrating a structure of a recess transistor as a technique proposed to secure an information storage time of a highly integrated semiconductor memory device.

Reference numeral 200 denotes a semiconductor substrate, 210 denotes a gate insulating film, 220 denotes a gate electrode, and S and D denote a source and a drain, respectively. The recess transistor structure recesses the semiconductor substrate 200 by a predetermined depth to maximize the distance between the source / drain region and the channel region. When the recess transistor structure is applied as the transistor of the memory device, the junction leakage current of the memory device is greatly reduced, thereby ensuring information storage time. However, there is a disadvantage that the current driving capability is not as good as the pin transistor structure.

Therefore, in recent years, by simultaneously implementing the pin transistor and the recess transistor in one cell, the saddle fin structure of the saddle fin structure capable of simultaneously achieving the effect of improving the current driving capability of the pin transistor and the information storage time of the recess transistor can be simultaneously achieved. Research on transistors (Saddle FIN FET) is being actively conducted.

3A and 3B are perspective views illustrating a manufacturing process of a conventional saddle fin structure transistor.

Referring to FIG. 3A, a trench is formed by etching a predetermined portion of the semiconductor substrate 300 to form an active region 300a that protrudes vertically from the semiconductor substrate 300. Subsequently, an insulating film having a predetermined thickness is embedded in the trench to form a field oxide film 302.

The channel region in the active region 300a is selectively etched to form a first recess portion having a predetermined depth. In addition, a portion of the field oxide layer 302 through which the gate electrode will pass is selectively etched to form a second recessed portion having a predetermined depth integrally connected with the first recessed portion. The structure formed by the first groove portion and the second groove portion is called a saddle, and in particular, a portion of the saddle structure that protrudes, that is, a portion of the active region 300a that protrudes above the surface of the field oxide film 302 is called a saddle pin. do.

Referring to FIG. 3B, a gate insulating layer is formed on the surface of the active region 300a exposed through the process of forming the first and second recesses. The gate electrode 310 is formed to overlap the saddle structure and cross the top surface of the active region 300a. In this case, the gate electrode 310 may be formed as a stacked structure of the first conductive film 312 and the second conductive film 314. Subsequently, a source / drain region S / D is formed in the active region 300a on both sides of the gate electrode 310 by an ion implantation process.

The saddle fin structure ensures stable refresh characteristics in the conventional recess gate structure, and at the same time, the bottom surface of the recess gate is implemented with a fin structure to extend the current path in the gate width direction to improve cell operating current characteristics. Can be improved. Such a FINFET employing structure can significantly improve the refresh characteristics due to the reduction of the cell threshold voltage (Vt), and at the same time, improve the cell current characteristics.

FIG. 4A is a cross-sectional view illustrating a problem occurring in a conventional saddle fin transistor manufacturing process, and FIG. 4B is an electron microscope (SEM) photograph. The same reference numerals as in FIG. 3 denote the same parts.

After the gate electrode 310 including the hard mask 316 is formed, the landing plug contact is additionally formed so that the top of the active region and the device isolation region is reliably opened after the etching process for forming the landing plug contact (LPC). The etch back process is performed. In this process, the device isolation layer made of SOD (Spin On Dielectric) material is more etched because the density of the film is lower than the active region made of silicon (Si). Therefore, the side surface of the fin gate formed in the device isolation layer may be exposed. In addition, in the etching process of forming a groove in the device isolation layer to form a fin gate, the landing plug contact is caused by the widening phenomenon of the gate formed in the device isolation layer due to the lower density of the device isolation layer than the silicon substrate. In the etching process, the sides of the gate are easily exposed. As a result, the polysilicon film of the pin gate and the landing plug polysilicon film are in contact with each other, thereby causing a problem of contact failure.

An object of the present invention is to provide a method of manufacturing a semiconductor device having a saddle pin transistor that can prevent the problem of contact failure caused by the contact between the polysilicon film of the pin gate and the landing plug contact. .

In order to achieve the above technical problem, a method of manufacturing a semiconductor device including a saddle fin transistor according to the present invention includes forming an isolation layer on a semiconductor substrate to define an active region, a semiconductor substrate of the active region, and a gate to pass through. Etching the portion of the device isolation layer to form a first trench in the active region and a second trench in the device isolation layer, forming a gate electrode across the active region while filling the first and second trenches, and forming a gate electrode. Forming an insulating film covering the insulating layer, etching the insulating film in the region where the contact is to be formed, exposing the active region and the isolation layer between the gate electrodes, and etching the exposed portion of the isolation layer to form a cavity Forming an insulating film on the surface of the cavity, and a landing plug control in contact with the active region between the gate electrodes A characterized in that it comprises forming.

The forming of the gate electrode may include forming a gate insulating layer on inner walls of the first and second trenches, forming a gate conductive layer to fill the first and second trenches, and forming a gate conductive layer on the gate conductive layer. The method may include forming a low resistance layer and a hard mask layer, and patterning the hard mask layer, the low resistance layer, the gate conductive layer, and the gate insulating layer.

The conductive layer may be formed of a doped polysilicon film, and the low resistance layer may be formed of a tungsten silicide or a hybrid tungsten film.

The forming of the cavity may include wet etching a predetermined thickness of the exposed device isolation layer and dry etching the wet etching device isolation layer.

In the step of dry etching the device isolation layer, it is preferable that the etch rate in the horizontal direction is higher than in the vertical direction so that an elliptical cavity elongated in the horizontal direction is formed.

In the step of dry etching the device isolation layer, the HBr gas and the chlorine (Cl ₂ ) gas may be used as an etching gas, and the etching power may be etched with a bias power of 20 to 80W.

The insulating film formed on the surface of the cavity may be formed to a thickness of 10 to 100 GPa, and may be formed of an oxide film or a nitride film.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, embodiments of the present invention may be modified in many different forms, and the scope of the present invention should not be construed as limited by the embodiments described below.

 The present invention provides a method for preventing contact failure by introducing a new structure for recessing the landing plug polysilicon film formed on the device isolation film to the device isolation film.

5 to 9 are cross-sectional views illustrating a method of manufacturing a saddle fin transistor according to the present invention.

Referring to FIG. 5, a device isolation layer 502 is formed in an inactive region of the semiconductor substrate 500 for isolation between devices. The device isolation layer 502 may be formed using a conventional shallow trench isolation (STI) method. Specifically, a pad oxide film (not shown) and a pad nitride film (not shown) are formed on the semiconductor substrate 500 to expose a region where the device isolation film is to be formed, and the semiconductor substrate having the pad nitride film exposed as a mask is anisotropic. Etching forms a trench of a predetermined depth. The trench is filled with an insulating material such as SOD, and then planarized to form an isolation layer 502. The impurity ion implantation process for screen oxidation, well formation, and threshold voltage control is selectively performed on the semiconductor substrate 500 on which the device isolation film 502 is formed.

Next, a hard mask layer 504 to be used as a mask for etching saddle fins is formed on the semiconductor substrate 500. The hard mask layer 504 may be formed by sequentially laminating an amorphous carbon film 504a and silicon oxynitride (SiON, 504b), for example. The hard mask layer 504 is patterned to expose a region where a saddle fin gate is to be formed, and then the semiconductor substrate 500 and the device isolation layer 502 of the exposed region are selectively etched to form a saddle fin gate trench. . In order to form the saddle transistor, the channel region in the active region must be selectively etched, and the portion of the device isolation layer through which the gate electrode passes is selectively etched.

Referring to FIG. 6, after the hard mask layer is removed, an oxide film is formed to a thickness of 30 to 60 GPa to form a gate insulating film (not shown). A doped polysilicon film 512 having a thickness of about 400 to 700 GPa, a tungsten silicide film 514 having a thickness of about 1,000 to 1,500 GPa, or a hybrid tungsten film having a thickness of about 400 to 500 GPa, and a thickness of about 2,000 to 2,500 GPa on the gate insulating film The hard mask layer 516 is sequentially formed. After performing a predetermined photolithography process, the hard mask layer 516 is patterned, and the tungsten silicide layer 514, the polysilicon layer 512, and the gate insulating layer are sequentially etched using the patterned hard mask layer as a mask. The gate pattern 510 is formed.

Referring to FIG. 7, an oxide film or a nitride film having a thickness of about 10 to about 100 μs is formed on the entire surface of the barrier film 520 for protecting the gate pattern in an etching process for forming a subsequent self-aligned contact (SAC). On the semiconductor substrate on which the barrier layer 520 is formed, a photoresist pattern (not shown) is formed to open a region where a landing plug contact of a cell region is to be formed and cover a peripheral circuit region. An etching process using a photoresist pattern as a mask is performed to remove the barrier layer 520 in a region where a landing plus contact is to be formed. At this time, the over-etching is performed as shown in order to ensure that the active region in which the landing plug contact is to be formed and the upper portion of the device isolation region are opened.

Referring to FIG. 8, a photoresist pattern (not shown) that masks a peripheral circuit region is formed to open only a cell region, and between the barrier layer 520 and the gate of the cell region using the photoresist pattern as a mask. The device isolation film 502 is selectively etched. In this case, a predetermined thickness of the device isolation layer 502 in the exposed region is first removed by wet etching, and then dry etching is performed to form a cavity. At this time, the etching conditions are adjusted such that the etch rate in the horizontal direction is faster than the etch rate in the vertical direction so that an elongated elliptic cavity is formed in the horizontal direction as shown. Dry etching of the device isolation layer 502 uses HBr gas and chlorine (Cl ₂ ) gas as an etching gas, and in order to increase the amount of etching in the horizontal direction, the bias power is lowered than that of a general dry etching process. For example, it is set as about 20-80W.

Referring to FIG. 9, after removing the photoresist pattern formed in the peripheral circuit region, an oxidation or nitriding process is performed to form an insulating film 530 formed of an oxide film or a nitride film on the surface of a cavity formed in the device isolation film.

For example, a doped polysilicon film is deposited on the resultant layer on which the insulating film 530 is formed to form a landing plug conductive layer 540. For example, the landing plug conductive layer 540 may have a polysilicon film doped with an N-type dopant such as phosphorus (P) at a concentration of 6.0 × 10 ²⁰ to 9.0 × 10 ²⁰ atoms / cm 2. It can be formed by depositing to a thickness. Subsequently, the conductive layer is patterned by photolithography to form a landing plug contact.

According to the present invention described above, by forming a cavity in the device isolation film of the portion where the landing plug contact hole is formed, and then forming an insulating film on the surface of the cavity to form a conductive film for landing plug contact, an etching process for forming a landing plug contact hole Due to the loss of the device isolation layer, the contact between the pin gate and the conductive film for landing plug contact may be prevented in advance. Therefore, it is possible to prevent contact failure and to ensure excellent device characteristics and to secure process margins for subsequent processes.

Although the present invention has been described in detail with reference to preferred embodiments, the present invention is not limited to the above embodiments, and various modifications may be made by those skilled in the art within the technical spirit of the present invention. Do.

1 is a perspective view illustrating a fin transistor structure proposed to secure a current driving capability of a semiconductor device.

2 is a cross-sectional view illustrating a structure of a recess transistor proposed to secure an information storage time of a highly integrated semiconductor memory device.

3A and 3B are perspective views illustrating a manufacturing process of a conventional saddle fin structure transistor.

FIG. 4A is a cross-sectional view illustrating a problem occurring in a conventional saddle fin transistor manufacturing process, and FIG. 4B is an electron microscope (SEM) photograph.

5 to 9 are cross-sectional views illustrating a method of manufacturing a saddle fin transistor according to the present invention.

Claims (9)

Forming an isolation layer on the semiconductor substrate to define an active region; Etching the semiconductor substrate in the active region and the device isolation layer in a portion through which the gate passes, forming a first trench in the active region and a second trench in the device isolation layer; Forming a gate electrode crossing the active region while filling the first and second trenches; Forming an insulating film covering the gate electrode; Etching the insulating film in a region where a contact is to be formed to expose an active region and a device isolation layer between the gate electrodes; Etching the exposed portion of the device isolation layer to form a cavity; Forming an insulating film on a surface of the cavity; And And forming a landing plug contact in contact with an active region between the gate electrodes. The method of claim 1, Forming the gate electrode, Forming a gate insulating film on inner walls of the first and second trenches; Forming a gate conductive layer to fill the first and second trenches, Forming a low resistance layer and a hard mask layer on the gate conductive layer; And patterning the hard mask layer, the low resistance layer, the gate conductive layer, and the gate insulating layer. The method of claim 2, The conductive layer is formed of a doped polysilicon film, And the low resistance layer is formed of a tungsten silicide or a hybrid tungsten film. The method of claim 1, Forming the cavity (cavity), Wet etching a predetermined thickness of the exposed device isolation layer; And dry-etching the wet-etched device isolation layer. The method of claim 4, wherein In the step of dry etching the device isolation film, A method of manufacturing a semiconductor device having a saddle fin transistor, wherein the etch rate in the horizontal direction is higher than that in the vertical direction to form a long elliptical cavity in the horizontal direction. The method of claim 4, wherein In the step of dry etching the device isolation film, A method of manufacturing a semiconductor device having a saddle fin transistor, characterized by using HBr gas and chlorine (Cl ₂ ) gas as an etching gas. The method of claim 4, wherein In the step of dry etching the device isolation film, A method for manufacturing a semiconductor device having a saddle pin transistor, which is etched with a bias power of 20 to 80 W. The method of claim 1, An insulating film formed on the surface of the cavity is formed to a thickness of 10 ~ 100 kHz, the manufacturing method of a semiconductor device having a saddle fin transistor. The method of claim 1, And an insulating film formed on the surface of the cavity is formed of an oxide film or a nitride film.

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