KR101133709B1 - Method for manufacturing semiconductor device - Google Patents

Abstract

The present invention is to provide a method of manufacturing a semiconductor device which can prevent the landing plug contact and the gate electrode from being shorted, and can prevent the landing plug contact from being opened during etching. A method of manufacturing a semiconductor device of the present invention includes forming a recess gate region in a semiconductor substrate; Forming a polysilicon film gap-filling the recess gate region; Stacking a metal film and a hard mask film on the polysilicon film; Etching the hard mask layer and the metal layer to form a metal electrode; Forming a capping film protecting sidewalls of the metal electrode; Etching the polysilicon film to form a polysilicon electrode; Recessing sidewalls of the polysilicon electrode; And forming a spacer film on a front surface of the polysilicon electrode so as to cover the recessed sidewall of the polysilicon electrode. By recessing, the gate electrode and the landing plug contact can be prevented from being shorted, and the sickle opening can be prevented from occurring during the etching of the contact hole for the landing plug contact.

Description

Semiconductor device manufacturing method {METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device in which a gate short is prevented.

As the semiconductor devices are highly integrated, as the channel length of the cell transistors is shortened, the refresh characteristics are rapidly deteriorated. In order to solve this problem, a recess gate process has been proposed. In the recess gate process, a gate gate region of the semiconductor substrate is etched to form a recess gate region, and a gate electrode is formed on the recess gate region to fabricate a transistor to increase channel length to improve refresh characteristics. to be. In the recess gate process, the gate electrode is formed by stacking a polysilicon film and a metal film.

In the recess gate process, when etching the polysilicon film and the metal film used as the gate electrode, the polysilicon film formed on the lower portion may be etched with a slope rather than vertical. As such, when the lower polysilicon layer constituting the gate electrode is etched with a slope, there are the following problems.

First, when forming a landing plug contact (LPC) after the formation of the gate electrode, the gate electrode and the landing plug contact may be shorted. In addition, the spacing between the gate electrodes is narrowed, causing contact etch to be immediately open to form a landing plug contact.

As the degree of integration of the semiconductor device increases, the process margin of the gap between the gate electrodes decreases, and even though the polysilicon film, which is a lower layer of the gate electrode, is etched vertically, the following problems may occur.

First, after forming the gate electrode, a spacer layer is formed on the top including the gate electrode to prevent self-aligned contact (SAC) fail. In this case, the contact area is narrowed during the contact etching process so that a better opening occurs, and the spacer layer is thinly formed. Even though the spacer is damaged during the contact etching process, SAC fail occurs.

When the polysilicon layer, which is a lower layer of the gate electrode, is etched with a slope, the CD (critical dimension) of the gate electrode formed in the peripheral circuit is increased, and in order to reduce the CD, the CD of the gate mask must be reduced so that the gate mask process is performed. This causes a problem of decreasing margins.

The present invention has been proposed to solve the above-described problems in the prior art, and prevents the landing plug contact and the gate electrode from being shorted, and at the same time prevents the opening of the landing plug contact during etching. The purpose is to provide.

A semiconductor device manufacturing method of the present invention for achieving the above object comprises the steps of forming a recess gate region on a semiconductor substrate; Forming a first conductive layer gap-filling the recess gate region; Stacking a second conductive film and a hard mask film on the first conductive film; Etching the hard mask layer and the second conductive layer to form a second conductive layer pattern; Forming a capping film protecting sidewalls of the second conductive film pattern; Etching the first conductive film to form a first conductive film pattern; Recessing sidewalls of the first conductive film pattern; And forming a spacer film on the entire surface of the first conductive film pattern so as to cover the recessed sidewall of the first conductive film pattern.

In addition, the semiconductor device manufacturing method of the present invention comprises the steps of forming a recess gate region on the semiconductor substrate; Forming a polysilicon film gap-filling the recess gate region; Stacking a metal film and a hard mask film on the polysilicon film; Etching the hard mask layer and the metal layer to form a metal electrode; Forming a capping film protecting sidewalls of the metal electrode; Etching the polysilicon film to form a polysilicon electrode; Recessing sidewalls of the polysilicon electrode; And forming a spacer film on a front surface of the polysilicon electrode to cover the recessed sidewall of the polysilicon electrode. Recessing the sidewalls of the polysilicon electrode may be performed by wet etching or isotropic plasma dry etching. The wet etching is characterized in that using a mixed solution of NH ₄ OH, H ₂ O ₂ and HO ₂ is mixed.

In the present invention described above, the side surface of the lower conductive film (polysilicon film) constituting the gate electrode is recessed during the recess gate process, thereby preventing the gate electrode and the landing plug contact from shorting, and the landing plug contact. There is an effect that can prevent the sickle opening occurs during the contact etching.

Thereby, the manufacturing yield of a semiconductor device can be improved.

1A to 1I are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

1A to 1I are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

As shown in FIG. 1A, an isolation layer 13 is formed in a field region of a semiconductor substrate 11 in which an active region and a field region are defined. In this case, the device isolation layer 13 is manufactured through a shallow trench isolation (STI) process. That is, the trench 12 is formed in the semiconductor substrate 11, and the device isolation layer 13 is formed by filling the inside of the trench 12 with an HDP (High Density Plasma) oxide film or an insulating film having insulating properties.

Subsequently, the recessed gate region 14 is formed by etching the predetermined region where the gate electrode of the semiconductor substrate 11 is to be formed to a predetermined depth. The recess gate region 14 may be formed by simultaneously etching the active region and the device isolation layer 13. The depth of the recess gate region 14 is preferably formed to be shallower than the depth of the trench 12.

As shown in FIG. 1B, the gate insulating layer 15 is formed along the upper surface of the semiconductor substrate 11 including the recess gate region 14.

The first conductive layer 16 and the second conductive layer 17 are sequentially stacked on the gate insulating layer 15. The first conductive layer 16 and the second conductive layer 17 are materials used as gate electrodes. The first conductive film 16 includes a polysilicon film. The second conductive film 17 includes a metal film such as a tungsten film. The first conductive layer 16 is formed on the gate insulating layer 15 to have a thickness for gap filling the recess gate regions 14.

Subsequently, a gate hard mask film 18 is formed on the second conductive film 17. The gate hard mask film 18 includes a nitride film.

An amorphous carbon film 19 and an antireflection film (ARC) 20 are laminated on the gate hard mask film 18. The amorphous carbon film 19 serves as an etching barrier in a subsequent etching process. The antireflection film 20 prevents diffuse reflection in subsequent photolithography processes. The anti-reflection film 20 includes a silicon oxynitride film (SiON).

Subsequently, after the photoresist film is applied on the antireflection film 20, the photoresist film is patterned so that the portion to be opened by the photolithography process is exposed. As a result, the gate mask 21 is formed.

As shown in FIG. 1C, the antireflection film 20 and the amorphous carbon film 19 are etched using the gate mask 21 as an etch barrier. Thereafter, the gate hard mask film 18 and the second conductive film 17 are etched using the amorphous carbon film 19 as an etch barrier. After etching the second conductive film 17, the gate mask 21 is stripped, and at this time, the anti-reflection film 20 and the amorphous carbon film 19 are simultaneously removed.

As described above, only the second conductive film 17, which is a metal film material, is etched using the gate mask 21, and the first conductive film 16 is not etched. When etching the second conductive layer 17, the surface of the first conductive layer 16 may be partially etched. The gate hard mask film and the second conductive film remain as shown by reference numerals '18A' and '17A', which are abbreviated as 'gate hard mask film pattern 18A' and 'metal electrode 17A'.

As shown in FIG. 1D, a capping layer 22 is formed on the entire surface including the gate hard mask layer pattern 18A. In this case, the capping layer 22 may be formed of an insulating layer, in particular, a nitride layer. The capping layer 22 may prevent deformation of a profile due to abnormal oxidation of the metal electrode 17A, which is a metal layer, in a subsequent process. It also acts as a mask for patterning the first conductive film 16.

As shown in FIG. 1E, the etch back is performed to remove the capping film on the surface of the gate hard mask film pattern 18A and the first conductive film 16. Accordingly, the capping film remains on the sidewalls of the gate hard mask film pattern 18A and the metal electrode 17A in the form of a capping spacer 22A.

Next, the polysilicon electrode 16A is formed by etching the first conductive film 16 in a vertical shape with the capping spacer 22A as an etch barrier. At this time, the stacked polysilicon electrode 16A and the metal electrode 17A constitute the gate electrode 30, and the gate electrode 30 has a line shape in which a lower layer is embedded in the recess region 14. As such, when the gate electrode 30 is formed by filling the recess region 14, the channel length of the gate electrode 30 may be increased.

As shown in Fig. 1F, the side surface of the polysilicon electrode 16A, which is a lower film constituting the gate electrode 30, is recessed. This is called side recess 23.

The side recesses 23 are formed on the polysilicon electrode 16A formed of the polysilicon film, and the side recesses 23 are formed on the metal electrode 17A whose sidewalls are protected by the capping spacer 22A. It will not proceed.

Preferably, the side recesses 23 comprise a wet etching process. At this time, since the polysilicon electrode 16A is a polysilicon film, wet etching is performed using a mixed solution in which NH ₄ OH, H ₂ O _2, and HO ₂ are mixed. For example, the wet etching is performed by mixing NH ₄ OH: H ₂ O ₂ : HO ₂ at a ratio of 1 to 2: 2 to 8:10 to 100 at a temperature of 40 to 120 ° C. When the wet etching process is performed, the etching ratio of the polysilicon electrode 16A formed of the polysilicon film and the etching selectivity of the gate insulating film 15 may be adjusted.

When the process conditions are performed, the sidewalls of the polysilicon electrode 16A are etched and have a high etching selectivity with respect to the gate insulating film 15, thereby preventing the gate insulating film 15 from being damaged. In particular, when the side recess 23 is driven at a high temperature, the etching selectivity of the oxide film relative to the polysilicon film may be further increased, thereby preventing damage to the gate insulating film 15.

By such a side recess 23 process, the width of the polysilicon electrode 16B becomes narrower than the width of the upper metal electrode 17A, and the lower interval between neighboring gate electrodes 30A becomes wider.

The process of wet etching the side of the polysilicon electrode 16B to be recessed may be performed using HNO ₃ solution or Tetra Methyl Ammonium Hydroxide (TMAH) solution.

As described above, the process may be performed by isotropic plasma dry etching in addition to the wet etching process such that the side surface of the polysilicon electrode 16B is recessed. In this isotropic plasma dry etching, bias power may be applied from 0 to 100 W, and the etching gas may be CF ₄ , SF ₆ , NF ₃ , C ₂ F ₆ , CHF ₃ , HBr, Cl ₂ , SiCl ₄ , O ₂ , At least one gas selected from the group consisting of N ₂ , Ar, CH ₄ , He, H ₂ O, SO ₂ and COS is used. Alternatively, at least two or more of these gases may be mixed and used.

The gate electrode 30A including the polysilicon electrode 16B and the metal electrode 17A is formed by the side recess 23 process. The polysilicon electrode 16B is smaller in width than the metal electrode 17A.

Thereafter, as shown in FIG. 1G, the gate spacer film 24 is formed on the entire surface including the gate electrode 30A. The gate spacer film 24 may be formed of a nitride film.

At this time, the polysilicon electrode 16B, which is the lower layer constituting the gate electrode 30A, is recessed inwardly from the upper metal electrode 17A, so that the gate spacer film 24 is formed on the side surface of the polysilicon electrode 16B. It is formed inward along.

As described above, when the side surface of the polysilicon electrode 16B, which is the lower layer of the gate electrode 30A, is recessed and the gate spacer layer 24 is formed inward along the side surface, a landing plug contact to be subsequently performed is performed. In the LPC process, a short circuit with the polysilicon electrode 16B, which is a gate lower layer, is prevented, and a lower gap between the gate electrodes 30A is increased, thereby increasing the open area during the etching of the interlayer dielectric layer for the landing plug contact (LPC). Sickle can prevent opening.

In addition, the gate spacer film 24 forming process may be formed thicker than the metal electrode 17A side at the side of the recessed polysilicon electrode 16B by depositing a plurality of times instead of depositing at once as described above.

In the process of forming the gate spacer layer 24, deposition and etching are repeated several times without deposition at a time so that the gate spacer layer 24 is formed thicker than the side surface of the metal electrode 17A at the side of the polysilicon electrode 16B. You may.

As shown in Fig. 1H, an interlayer insulating film (not shown) is formed on the entire surface including the gate spacer film 24 to gap-fill the gate electrodes 30A.

Subsequently, the contact etching process is performed to form the landing plug contact hole 25. When the landing plug contact hole 25 is formed, the gate spacer layer 24 and the gate insulating layer 15 are etched to expose the surface of the semiconductor substrate 11 between the gate electrodes 30A. The process of forming the landing plug contact hole 25 applies a self aligned contact (SAC) process.

As shown in FIG. 1I, a plug conductive film is formed on the front surface to fill the landing plug contact hole 25, and then a chemical mechanical polishing (CMP) process or an etch back process is performed to connect the landing plug contact to the landing plug contact hole. Landing Plug Contact, 26). At this time, the landing plug contact 26 is separated by exposing the upper portion of the gate hard mask layer 18A. The landing plug contact 26 and the gate electrode 30A are insulated by the gate spacer film 24A and the capping spacer 22A.

Thus far, the present invention has been described with respect to the recessed gate electrode having an increased length of the channel through the embodiment. However, the present invention is not limited thereto, and the above-described step of recessing the lower film of the gate electrode can be applied to the manufacturing process of all the semiconductor devices having the gate electrodes laminated with conductive films.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

11: semiconductor substrate 13: device isolation film
14: recess gate region 15: gate insulating film
16B: polysilicon electrode 17A: metal electrode
18A: Gate hard mask film 22A: Capping spacer
24A: gate spacer film 30A: gate electrode

Claims (14)

Forming a recess gate region in the semiconductor substrate;
Forming a first conductive layer gap-filling the recess gate region;
Stacking a second conductive film and a hard mask film on the first conductive film;
Etching the hard mask layer and the second conductive layer to form a second conductive layer pattern;
Forming a capping film protecting sidewalls of the second conductive film pattern;
Etching the first conductive film to form a first conductive film pattern;
Recessing sidewalls of the first conductive film pattern; And
Forming a spacer film on a front surface of the first conductive film pattern to cover the recessed sidewall of the first conductive film pattern
≪ / RTI >
Claim 2 has been abandoned due to the setting registration fee. The method of claim 1,
After the forming of the spacer film,
Forming a contact hole exposed by a surface of the semiconductor substrate; And
Forming a landing plug contact to fill the contact hole
A semiconductor device manufacturing method further comprising.
Claim 3 was abandoned when the setup registration fee was paid. The method of claim 1,
Recessing the sidewalls of the first conductive film pattern,
A method of manufacturing a semiconductor device by wet etching.
Claim 4 was abandoned when the registration fee was paid. The method of claim 1,
Recessing the sidewalls of the first conductive film pattern,
A method of manufacturing a semiconductor device proceeding by isotropic plasma dry etching.
Forming a recess gate region in the semiconductor substrate;
Forming a polysilicon film gap-filling the recess gate region;
Stacking a metal film and a hard mask film on the polysilicon film;
Etching the hard mask layer and the metal layer to form a metal electrode;
Forming a capping film protecting sidewalls of the metal electrode;
Etching the polysilicon film to form a polysilicon electrode;
Recessing sidewalls of the polysilicon electrode; And
Forming a spacer layer on a front surface of the polysilicon electrode to cover the recessed sidewall of the polysilicon electrode;
≪ / RTI >
Claim 6 was abandoned when the registration fee was paid. The method of claim 5,
After the forming of the spacer film,
Forming a contact hole exposed by a surface of the semiconductor substrate; And
Forming a landing plug contact to fill the contact hole
A semiconductor device manufacturing method further comprising.
Claim 7 was abandoned upon payment of a set-up fee. The method of claim 5,
Recessing the sidewall of the polysilicon electrode,
A method of manufacturing a semiconductor device by wet etching.
Claim 8 was abandoned when the registration fee was paid. The method of claim 7, wherein
The wet etching is performed using a mixed solution of NH ₄ OH, H ₂ O ₂ and HO ₂ is a semiconductor device manufacturing method.
Claim 9 was abandoned upon payment of a set-up fee. The method of claim 8,
The wet etching is a method of manufacturing a semiconductor device to proceed by mixing the NH ₄ OH: H ₂ O ₂ : HO ₂ in a ratio of 1 ~ 2: 2: 8 ~ 10 ~ 100 at a temperature of 40 ~ 120 ℃.
Claim 10 was abandoned upon payment of a setup registration fee. The method of claim 7, wherein
The wet etching is performed using a HNO ₃ solution or TMAH (Tetra Methyl Ammonium Hydroxide) solution.
Claim 11 was abandoned upon payment of a setup registration fee. The method of claim 5,
Recessing the sidewall of the polysilicon electrode,
A method of manufacturing a semiconductor device proceeding by isotropic plasma dry etching.
Claim 12 was abandoned upon payment of a registration fee. The method of claim 11,
The isotropic plasma dry etching,
A bias power of 1 to 100 W is applied, and as etching gas, CF ₄ , SF ₆ , NF ₃ , C ₂ F ₆ , CHF ₃ , HBr, Cl ₂ , SiCl ₄ , O ₂ , N ₂ , Ar, CH ₄ , He And at least one selected from the group consisting of H ₂ O, SO ₂ and COS, or a mixture of two or more gases.
Claim 13 was abandoned upon payment of a registration fee. The method of claim 5,
The capping film, the hard mask film and the spacer film include a nitride film.
Claim 14 was abandoned when the registration fee was paid. The method of claim 5,
Forming the spacer film,
And depositing all of the recessed sidewalls of the polysilicon electrode by repeating the deposition and etching several times.

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