KR101009068B1 - Method of manufacturing a semiconductor device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to providing a semiconductor substrate having a gate insulating film, a polysilicon film, a tungsten film, and a hard mask film sequentially, patterning the hard mask film and the tungsten film, and exposing the same. And forming a protective film having a nitride film and an oxide film stacked structure on the entire surface including the tungsten film and patterning the bottom surface of the protective film and the polysilicon film between sidewalls of the protective film.

Tungsten Gate, Double Shielding, Retention, Charge Loss

Description

Method of manufacturing a semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and in particular, to substantially suppress the occurrence of tungsten-containing metallic residues that may occur on the sidewalls of the dielectric film and the tunnel insulating film during tungsten film etching, thereby improving retention characteristics of the device. It relates to a method for manufacturing a semiconductor device that can be.

In order to reduce the resistance of NAND flash recently, CKBD is adopted by using tungsten having lower resistivity than tungsten silicide (WSix), and at the same time, due to the metal residue formed by the general tungsten gate etching method as the design rule becomes smaller. A retention board (Check Board Retention Fail) is occurring.

Tungsten gates were first employed in DRAMs, but flash is relatively complex in structure, and the electrical environment used is much weaker than DRAM. In other words, since DRAM operates at a low bias, the resistance of a ring oscillator, that is, a high resistance material at the interface between tungsten and polysilicon film, becomes an issue when tungsten is applied, thus forming a hybrid electrode. Substantially, in the advanced sidewall scheme developed by Micron, gate etch damage can be sufficiently reduced by selective oxidation. However, in the case of NAND flash, unlike the tungsten silicide, the residues formed are different and the metallic residues formed on the sidewalls of the dielectric film and the tunnel insulation film cannot be removed.

Countermeasures to solve this problem are to develop a cleaning material that effectively removes metallic residues including tungsten after etching of the tungsten gate, or to change the etching chemistry used for etching to make soluble residues. However, these are all methods that can be achieved by a lot of experience and solution synthesis, and it is believed that much basic research should be continued in reality.

The present invention forms a double passivation layer on the exposed sidewall of the tungsten layer after patterning the tungsten layer to prevent the tungsten layer from being exposed through the passivation layer during the subsequent gate etching process. It is to provide a method of manufacturing a semiconductor device that can essentially suppress the occurrence of the containing metallic residue to improve the retention characteristics of the device.

According to one or more exemplary embodiments, a method of manufacturing a semiconductor device may include providing a semiconductor substrate on which a gate insulating film, a polysilicon film, a tungsten film, and a hard mask film are sequentially formed, patterning the hard mask film and the tungsten film, and exposing the same. Forming a protective film having a nitride film and an oxide film stacked structure on the entire surface including the tungsten film; and patterning the bottom surface of the protective film and the polysilicon film between the protective film sidewalls.

In the above, a part of the polysilicon film is etched during the tungsten film patterning.

The oxide film has high etching selectivity with respect to the dry chemistry for gate etching and excellent step coverage characteristics.

The oxide film is formed by Low Pressure Chemical Vapor Deposition (LPCVD).

The LPCVD oxide film is formed of a Low Pressure-Tetra Ethyl Ortho Silicate (LP-TEOS) film or a High Temperature Oxide (HTO) film.

After the polysilicon film patterning, the nitride film is left on the sidewall of the tungsten film at a thickness of at least 50 GPa.

In the polysilicon film patterning, a part of the gate insulating film is etched.

A laminated film of a polysilicon film for floating gate and a dielectric film is further formed below the polysilicon film.

A laminated film of a nitride film and a dielectric film is further formed below the polysilicon film.

After the polysilicon film patterning, the method may further include performing a re-oxidation process on the gate pattern.

After etching the tungsten film, the present invention forms a double passivation layer of a nitride film and an oxide layer structure on the exposed sidewall of the tungsten film to completely protect the tungsten film through the passivation layer during the subsequent gate etching process, and thus may occur on the lower side of the dielectric layer and the tunnel insulation layer. By essentially suppressing the occurrence of metallic tungsten-containing metallic residues, it is possible to prevent charge loss and improve the retention characteristics of the device, which allows mass production of gated flash devices using tungsten. .

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

1A through 1C are cross-sectional views illustrating a method of manufacturing a flash memory device according to an exemplary embodiment of the present invention.

Referring to FIG. 1A, the tunnel insulating film 102, the floating silicon polysilicon film 104, the dielectric film 106, the control gate conductive film 108, and the hard mask film 114 are sequentially formed by a known method. Provided is a semiconductor substrate 100 formed. The tunnel insulating layer 102 may be formed of a silicon oxide layer (SiO ₂ ), and in this case, may be formed by an oxidation process. In a DRAM manufacturing process, the tunnel insulating film 102 is used as a gate insulating film. The floating gate polysilicon film 104 is used as a gate electrode in a floating gate and a DRAM manufacturing process of a NAND flash memory device.

After the floating gate polysilicon layer 104 is formed, the floating gate polysilicon layer 104, the tunnel insulating layer 102, and the semiconductor substrate 100 are etched by an etching process using a mask (not shown). And a trench (not shown) is formed. Subsequently, an isolation material is deposited on the floating gate polysilicon film 104 including the trench and then planarized to form an isolation layer (not shown) in the region where the trench is formed. Meanwhile, an isolation mask (not shown) may be further formed on the floating gate polysilicon layer 104 to be used as an etch mask when forming the trench and to prevent loss of the floating gate polysilicon layer 104. .

The dielectric film 106 is formed on the floating silicon polysilicon film 104 and the device isolation film, and may be formed of a laminated film of an oxide film, a nitride film, and an oxide film (Oxide-Nitride-Oxide; ONO). The control gate conductive film 108 is used as a gate electrode in a control gate and DRAM manufacturing process of a NAND flash memory device, and may be formed of a polysilicon film, a metal layer, or a stacked film thereof. In order to implement a high speed device, the polysilicon film 110 for the control gate and the tungsten (W) film 112 for the control gate are preferably formed as a laminated film. Meanwhile, when the control gate conductive film 108 is formed of a laminated film of the control gate polysilicon film 110 and the control gate tungsten film 112, a tungsten nitride film (WN) is disposed below the control gate tungsten film 112. (Not shown) may be formed by further deposition. The hard mask layer 114 may be formed by including an oxide-based or nitride-based material. For example, the hard mask layer 114 may be formed of a laminated film such as a SiON / TEOS (Tetra Ethyl Ortho Silicate) oxide film or an amorphous carbon film. Can be.

Subsequently, a first gate etching process may be performed to pattern the hard mask film 114 and the tungsten film 112 for control gate in an etching process using a mask (not shown). The primary gate etching process is performed by a dry etch process. The etching process of the tungsten film 112 for the control gate is performed by using N ₂ and Cl ₂ in HBr gas to prevent anisotropic etching of the polysilicon film 110 for the control gate. This can be carried out using a plasma of a mixed gas to which a gas is added. At this time, added N ₂ and Cl ₂ The gas serves to prevent anisotropic etching of the control gate polysilicon film 110 formed under the control gate tungsten film 112.

The primary gate etching process stops etching in a state where a part of the control silicon polysilicon layer 110 is etched so that the control gate tungsten film 112 is completely patterned. As a result, the polysilicon film 110 for the control gate is partially etched.

Although not illustrated in the drawings, the first gate etching process may pattern the hard mask layer 114 and the tungsten layer 112 for the control gate by an etching process using a mask, and may be etched on the upper surface of the polysilicon layer 110 for the control gate. It may be implemented to stop.

However, in the primary gate etching process, the etching is not stopped in the ONO dielectric film 106, and a part of the polysilicon film 110 for the control gate is etched or the tungsten film 112 for the control gate is etched. Stops etching. This is because a residue containing tungsten, which is formed once on the sidewall of the dielectric film 106, is not completely removed.

Referring to FIG. 1B, a passivation layer 120 having a stacked structure of a first passivation layer 116 and a second passivation layer 118 may be formed on an entire surface including the exposed control gate polysilicon layer 110. The first passivation layer 116 may be formed of a nitride film.

The second passivation layer 118 has a high selectivity to gate etch dry chemistry, and step coverage to secure the width of the active region (ie, secure the channel length). ) It is formed of a material with excellent properties. In order to satisfy this, the second protective film 118 may be formed of an oxide film using a low pressure chemical vapor deposition (LPCVD) method. In this case, the oxide film using the LPCVD method may be formed of a low pressure-tetra ethyl ortho silicate (LP-TEOS) film or a high temperature oxide (HTO) film.

Buffered Oxide Etchant (BOE) and O ₃ A cleaning process or a very short cleaning process using a mixture of H ₂ SO ₄ and H ₂ O ₂ and BOE (Buffered Oxide Etchant) is performed sequentially.

Referring to FIG. 1C, a secondary gate etching process is performed to pattern the control gate polysilicon layer 110, the dielectric layer 106, and the floating gate polysilicon layer 104. The secondary gate etching process is performed by a dry etching process, and the bottom surface of the passivation layer 120 between the sidewalls of the passivation layer 120, the polysilicon layer 110 for the control gate, the dielectric layer 106, and the polysilicon layer for the floating gate ( 104) is sequentially etched.

The polysilicon film 110 for the control gate and the polysilicon film 104 for the floating gate are O ₂ in HBr gas. Etching may be performed by using a plasma of a mixed gas or HBr single gas added with a gas. The dielectric film 106 is formed of CxFy (1 ≦ x ≦ _6, such as CF ₄ , C ₂ F ₆ , C ₃ F ₈ , C ₄ F ₈ , C ₅ F ₈ , C ₄ F ₆ , C ₆ F _6, etc.). 4≤y≤8) and at least one of CHxFy (1≤x≤4, 0≤y≤3) series gases such as CHF ₃ , CH ₂ F ₂ , CH ₃ F, CH ₄ Etching may be performed using plasma etching using a single gas or a mixed gas as a stock angle gas. In order to control the etch stop, the etching rate, or the plasma uniformity, the stock angle gas may further include at least one additional gas of HBr, O ₂ , N ₂ , He, Ne, and Ar.

In this case, the secondary gate etching process stops the etching in a state where a part of the tunnel insulating layer 102 is etched so that the patterning of the floating silicon polysilicon layer 104 is performed intact. As a result, a portion of the tunnel insulating film 102 is etched. The tunnel insulating layer 102 may be partially used to prevent attack of the semiconductor substrate 100 or may be used as a buffer layer in a subsequent ion implantation process.

In particular, in the second gate etching process, the passivation layer 120 on the upper surface and the upper sidewall is removed, and a part of the passivation layer 120 on the sidewall of the tungsten layer 112 for the control gate is also etched due to the difference in selectivity to the gate etching chemistry. do. Therefore, the control gate tungsten film 112 is formed to have a thickness of at least 50 μs by controlling the process conditions during the second gate etching so that the control gate tungsten film 112 is not exposed after the secondary gate etching. It remains on the side wall of the. Because of this, After the second gate etching, a portion of the passivation layer 120 is left in the form of a spacer on the edges of both sidewalls of the floating gate polysilicon layer 110 to the hard mask layer 114. In addition, in the second gate etching process, the hard mask layer 114 may be etched together to be lowered by some thickness.

As a result, the floating gate 104a including the floating gate polysilicon film 104, the control gate polysilicon film 110, and the control gate tungsten film 112 are laminated to the control gate conductive film 108. The control gate 108a is formed. In this case, the hard mask layer may be formed from a partial thickness of the tunnel insulating layer 102, the floating gate 104a, the dielectric layer 106, the control gate 108a, the hard mask layer 114, and the floating silicon polysilicon layer 110. The gate pattern 122 including the passivation layer 120 remaining on the edges of both side walls up to 114 is formed.

However, when only the tungsten film 112 for the control gate is patterned in the primary gate etching process, the tunnel insulating film 102, the floating gate 104a, the dielectric film 106, the control gate 108a, and the hard mask film are patterned. A gate pattern 122 including a passivation layer 120 remaining on the sidewalls 114 and 114 of the tungsten layer 112 for the control gate and the hard mask layer 114 is formed.

If a protective layer is formed on the entire surface including the exposed tungsten film for the control gate after etching of the conventional control gate tungsten film, the etching margin for the gate etch dry chemistry is insufficient for the subsequent etching of the gate. The tungsten film for the control gate may be exposed at the portion to generate a metallic residue including tungsten on the sidewalls of the lower dielectric film and the tunnel insulating film. However, in one embodiment of the present invention, the protective film 120 of the oxide / nitride layer stacked structure is formed on the exposed sidewall of the tungsten film 112 for the control gate through the selectivity difference with respect to the dry chemistry of the subsequent gate etching. As the etching margin is secured, a part of the first passivation layer 116 remains on the sidewall of the tungsten film 112 for control gate during the subsequent secondary gate etching process, thereby completely protecting the sidewall of the tungsten film 112 for control gate. do. As a result, the secondary gate etching process according to an embodiment of the present invention is to etch the polysilicon gate stacked structure in which the tungsten film 112 for the control gate is not employed. Accordingly, CKBD retention characteristics of the device are prevented by essentially suppressing the generation of metallic residues such as tungsten-containing metallic residues that may occur on the sidewalls of the dielectric film 106 and the tunnel insulation film 102. Can be improved.

Thereafter, a cleaning process is performed to remove poly residues or oxide residues generated during the secondary gate etching process. Poly residues or oxide residues generated during the secondary gate etching process include a mixed solution of H ₂ SO ₄ and H ₂ O ₂ , buffered oxide etchant (BOE) and SC-1 (NH ₄ OH, H ₂ O ₂ and Since it is sufficiently removed with a cleaning liquid such as H ₂ 0 mixed solution, it is possible to fundamentally solve a charge loss problem.

Although not shown, after the gate etching process, a re-oxidation process is performed to mitigate damage generated during the gate etching. The reoxidation process applies the oxidation concept rather than the deposition concept and can preferably be carried out in a selective oxidation process. As a result, a selective oxide layer is formed on the entire surface of the gate pattern 122, which keeps the thickness at the sidewall of the gate pattern 122 at least 50 GPa or more to completely eliminate the charge loss phenomenon.

The gate etching method according to an exemplary embodiment of the present invention uses a flash memory having a metal structure such as a metal-oxide-nitride-oxide-silicon (MONOS) structure using a nitride film as a charge storage film instead of a polysilicon film as well as a semiconductor device such as a DRAM. Applicable to the device.

The present invention is not limited to the above-described embodiments, but may be implemented in various forms, and the above embodiments are intended to complete the disclosure of the present invention and to completely convey the scope of the invention to those skilled in the art. It is provided to inform you. Therefore, the scope of the present invention should be understood by the claims of the present application.

1A through 1C are cross-sectional views illustrating a method of manufacturing a flash memory device according to an exemplary embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

100 semiconductor substrate 102 tunnel insulating film

104: polysilicon film for floating gate 104a: floating gate

106 dielectric film 108 conductive film for control gate

108a: control gate 110: polysilicon film for control gate

112: tungsten film for control gate 114: hard mask film

116: first protective film 118: second protective film

120: protective film 122: gate pattern

Claims (10)

Providing a semiconductor substrate on which a gate insulating film, a polysilicon film, a tungsten film, and a hard mask film are sequentially formed; Patterning the hard mask film and the tungsten film; Forming a protective film having a nitride film and an oxide film stacked structure on the entire surface including the exposed tungsten film; And Patterning a bottom surface of the passivation layer and the polysilicon layer between the passivation layer sidewalls; A method of manufacturing a semiconductor device to etch a portion of the gate insulating film when the polysilicon film is patterned. The method of claim 1, wherein in the tungsten film patterning, A method of manufacturing a semiconductor device for etching a portion of the polysilicon film. The method of claim 1, The oxide film has a high selectivity ratio to a gate etch dry chemistry, and has excellent step coverage. The method of claim 3, wherein The oxide film is a low pressure chemical vapor deposition (LPCVD) method of manufacturing a semiconductor device. The method of claim 4, wherein And the oxide film of the LPCVD method is formed of an LP-TEOS film or an HTO film. The method of claim 1, wherein after the polysilicon film patterning, And the nitride film remains on the sidewall of the tungsten film at a thickness of at least 50 GPa. delete The method of claim 1, A method of manufacturing a semiconductor device, further comprising a stacked film of a polysilicon film for floating gate and a dielectric film under the polysilicon film. The method of claim 1, And a stacked layer of a nitride film and a dielectric film is further formed below the polysilicon film. The method of claim 1, After the polysilicon film patterning, performing a reoxidation process on the gate pattern.

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