KR20100076568A - Method for fabricating charge trap type nonvolatile memory device - Google Patents

Abstract

PURPOSE: A manufacturing method of a non-volatile memory device of a charge trap type is provided to prevent the damage of an exposed tunnel insulating layer not using CHF5 gas in a first etching process. CONSTITUTION: A tunnel insulating layer(12) formed from an oxide layer is formed on a substrate(11). A charge trap layer(13) formed from a nitride layer is formed on the turner insulating layer. A dielectric layer(14), a gate conductive layer and a hard mask layer(16) are successively formed on the charge trap layer. The gate conductive layer is etched using the hard mask layer as an etching barrier to form a gate electrode(15A). The insulating layer is etched using the hard mask layer as the etching barrier.

Description

METHODS FOR FABRICATING CHARGE TRAP TYPE NONVOLATILE MEMORY DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a manufacturing technique of a semiconductor device, and more particularly, to a method of manufacturing a charge trap type nonvolatile memory device.

Recently, in order to implement highly integrated nonvolatile memory devices of 40 nm or less, research on charge trap type nonvolatile memory devices has been actively conducted. The charge trap type nonvolatile memory device has a structure in which a tunnel insulating film, a charge trap film, a dielectric film, and a gate electrode are sequentially stacked on a substrate, and have trap sites having a deep level in the charge trap film. Data is stored by trapping (or capturing) the charge on it.

Charge-trap nonvolatile memory devices include SONOS (Si / Oxide / Nitride / Oxide / Si) structures, SANOS (Si / Al ₂ O ₃ / Nitride / Oxide / Si), and MANOS (Metal / Al ₂ O ₃ / Nitride) / Oxide / Si) structure, which is known to have excellent memory device characteristics of the MANOS structure, in particular, the TANOS structure in which a tantalum nitride film (TaN) or a titanium nitride film (TiN) is applied as a gate electrode.

1 is a cross-sectional view illustrating a charge trapping nonvolatile memory device having a TANOS structure according to the prior art, and FIG. 2 is an image illustrating a problem according to the prior art.

Referring to FIG. 1, a method of manufacturing a charge trap type nonvolatile memory device having a TANOS structure includes a tunnel insulating film 101, a charge trap film 102, a dielectric film 103, and an oxide film formed on a silicon substrate 100. After the gate conductive film and the hard mask film 105 are sequentially formed, the gate conductive film is etched using the hard mask film 105 as an etch barrier to form the gate electrode 104.

Next, after the spacer film 106 is formed on both sidewalls of the hard mask film 105 and the gate electrode 104, the stop on oxide film stops on the hard mask film 105 and the spacer film 106 as an etch barrier. The dielectric film 103 and the charge trap film 102 are etched using an oxide scheme.

However, the related art has a problem in that the tunnel insulation film 101 exposed by the charge trap film 102 is damaged due to the lack of an etching selectivity with the tunnel insulation film 101 during the etching process of the charge trap film 102 ( See reference numeral 'B' in FIG. 1).

To solve this problem, the charge trap film 102, an etching process when the tunnel insulating film 101, an etching selection ratio is greater etching conditions for example, as an etching gas large etching of oxide selectivity CH ₂ F ₂ gas, CHF ₃ gas and O _The charge trap film 102 is etched using a mixed gas (CH ₂ F ₂ / CHF ₃ / O ₂ ) in which _two gases are mixed. In this case, a problem arises in that tails (T) are formed on both side walls of the charge trap layer 102 without vertical etching of the sidewalls of the charge trap layer 102 (reference numerals of FIGS. 1 and 2). See "A"). As such, when the tails T are formed on both sidewalls of the charge trap layer 102, the adjacent charge trap layers 102 may be interconnected by the tail T, which causes deterioration of the characteristics of the memory device.

Therefore, when overetching is additionally performed to prevent the tail T from being formed, a problem arises in that the tunnel insulating film 101 is damaged due to the overetching (see reference numeral 'B' in FIG. 1). ). In particular, in the above-described mixed gas, since the CHF ₃ gas has a low etching selectivity with respect to the oxide film, damage to the tunnel insulating film 101 is intensified by the CHF ₃ gas.

In addition, an aluminum oxide film is used as the dielectric film 103, and there is a problem in that a by-product (eg, a polymer) is generated in the process of etching the aluminum oxide film. Due to the polymer generated during the etching of the dielectric film 103, there is a problem in that the tail T is formed on both sidewalls of the charge trap film 102. In addition, the polymer remains inside the chamber (or the inner wall) to act as a particle source or to contaminate the equipment.

SUMMARY OF THE INVENTION The present invention has been proposed to solve the above problems of the prior art, and an object thereof is to provide a method for manufacturing a charge trap type nonvolatile memory device capable of preventing a tail from being formed on both side walls of the charge trap layer.

Another object of the present invention is to provide a method for manufacturing a charge trapping nonvolatile memory device capable of preventing damage (or loss) of a tunnel insulating layer exposed during a charge trapping film etching process.

According to an aspect of the present invention, there is provided a method for manufacturing a charge trap type nonvolatile memory device, the method including: forming a tunnel insulating film formed of an oxide film on a substrate; Forming a charge trap film made of a nitride film on the tunnel insulating film; Sequentially forming a dielectric film, a gate conductive film, and a hard mask film on the charge trap film; Etching the gate conductive layer using the hard mask layer as an etch barrier to form a gate electrode; Etching the dielectric layer using the hard mask layer as an etch barrier; And a second etching step of etching the charge trap layer using the hard mask layer as an etching barrier, and a second etching step of removing tails of both side walls of the charge trap layer formed during the first etching.

In addition, the present invention may further include a step of removing the polymer generated during the etching of the dielectric film before the first etching step. Specifically, the removing of the polymer includes injecting and purging Ar gas into the chamber to remove the polymer remaining in the chamber and injecting oxygen gas into the chamber to remove the polymer remaining on the substrate surface. It may include the step of performing a flush process.

During the oxygen flushing process, carbon fluoride gas may be further injected into the chamber. At this time, it is preferable to perform the oxygen flush process using the oxygen gas of a higher flow rate than the fluorocarbon gas. For example, the oxygen gas may use a flow rate in the range of 150 sccm to 250 sccm, and the fluorocarbon gas may use a flow rate in the range of 4 sccm to 8 sccm.

The first etching and the second etching may be performed in situ in the same chamber.

The first etching step, the CH ₂ F ₂ gas and O ₂ gas can be carried out using a mixed gas mixed in a ratio of 1.5: 1 ~ 2: 1 (CH ₂ F ₂ : O ₂ ), the mixed gas It can be carried out by further adding Ar gas to the.

The secondary etching step may be performed using a mixed gas in which HBr gas and O ₂ gas are mixed. At this time, it is preferable to carry out using the HBr gas of a higher flow rate than the O ₂ gas. For example, the HBr gas may use a flow rate in the range of 150 sccm to 250 sccm, and the O ₂ gas may use a flow rate in the range of 4 sccm to 8 sccm. In addition, the secondary etching step may be performed using a bias power in the range of 150V to 250V.

The dielectric film is any one selected from the group consisting of aluminum oxide (Al ₂ O ₃ ), hafnium oxide (HfO ₂ ), zirconium oxide (ZrO ₂ ), yttrium oxide (Y ₂ O ₃ ), and lanthanum oxide (La ₂ O ₃ ). One or these can be formed into a laminated film in which they are laminated.

The etching of the dielectric film may be performed using a mixed gas in which BCl ₃ gas, Cl ₂ gas, and Ar gas are mixed.

The forming of the gate electrode, the etching of the dielectric film, and the first and second etching may be performed by using an inductively coupled plasma (ICP) etching apparatus.

The gate electrode may include a tantalum nitride film (TaN) or a titanium nitride film (TiN).

In addition, after forming the gate electrode, the method may further include forming a spacer layer on both sidewalls of the hard mask layer and on both sidewalls of the gate electrode. The spacer film is selected from the group consisting of a single film made of an oxide film or a nitride film, a laminated film (oxide film / nitride film) in which an oxide film and a nitride film are laminated, and a laminated film (oxide film / nitride film / oxide film) in which an oxide film, a nitride film and an oxide film are sequentially stacked. It can be formed by either.

The present invention based on the above-described problem solving means has the effect of preventing damage (or loss) of the exposed tunnel insulating film by not using the CHF ₃ gas during the primary etching.

In addition, the present invention by the secondary etching using the mixed gas mixed with HBr gas and O ₂ gas, while removing the tail of both side walls of the charge trap film and at the same time has the effect of preventing damage to the exposed tunnel insulating film have.

In addition, by removing the polymer generated during the dielectric film etching process, the present invention has an effect of preventing the deep formation of tails on both side walls of the charge trap film by the polymer. In addition, there is an effect that can prevent the chamber and the substrate is contaminated by the polymer.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings, in order to facilitate a person skilled in the art to easily carry out the technical idea of the present invention.

3A to 3E are cross-sectional views illustrating a method of manufacturing a charge trap type nonvolatile memory device according to an exemplary embodiment of the present invention.

As shown in FIG. 3A, a tunnel insulating film 12 is formed on a substrate 11, for example, a silicon substrate. The tunnel insulating film 12 may be formed of an oxide film, for example, silicon oxide film (SiO ₂ ), and the silicon oxide film for the tunnel insulating film 12 may be formed using thermal oxidation. In this case, the tunnel insulating layer 12 may be formed to have a thickness of 30 μs or more, for example, 30 μs to 40 μs in order to improve data retention characteristics of the memory device.

Next, the charge trap film 13 is formed on the tunnel insulating film 12. The charge trap film 13 is a space in which charge is stored, that is, a space in which data is stored, and is preferably formed of a material having a deep level trap site in the film. For example, the charge trap film 13 may be formed of a nitride film. In this case, a silicon nitride film (Si ₃ N ₄ ) may be used as the nitride film.

The charge trap film 13 may be formed to have a thickness in the range of 50 kV to 60 kV.

Next, the dielectric film 14 is formed on the charge trap film 13. The dielectric film 14 is preferably formed of a material having a high dielectric constant (High-K). Here, a material having a high dielectric constant greater than that of a silicon oxide film. Therefore, it means a material having a dielectric constant of 3.9 or more.

The dielectric film 14 may be formed of a metal oxide film having a high dielectric constant. As the metal oxide film, any one selected from the group consisting of aluminum oxide film (Al ₂ O ₃ ), hafnium oxide film (HfO ₂ ), zirconium oxide film (ZrO ₂ ), yttrium oxide film (Y ₂ O ₃ ), and lanthanum oxide film (La ₂ O ₃ ) One or these can be formed into a laminated film in which they are laminated. Hereinafter, in the embodiment of the present invention, a case where the dielectric film 14 is formed of an aluminum oxide film will be described.

Next, the gate conductive film 15 is formed on the dielectric film 14. The gate conductive film 15 may be formed of a silicon film, a metallic film, or a laminated film in which a silicon film and a metallic film are stacked. As the silicon film, a polysilicon film (poly Si), a silicon germanium film (SiGe), or the like can be used. Tungsten film (W), titanium film (Ti), tantalum film (Ta), tungsten nitride film (WN), tantalum nitride film (TaN), titanium nitride film (TiN), tungsten silicide (WSi) and the like can be used as the metallic film. .

Here, the gate conductive film 15 in contact with the dielectric film 14 is preferably formed of a material having a larger work function than silicon, such as a tantalum nitride film or a titanium nitride film. This reduces the electron injection from the gate electrode to the charge trap film 13 during the erase operation when a material having a work function larger than that of silicon is formed on the dielectric film 14 and used as the gate electrode. This is because the erase speed can be improved.

For example, the gate conductive film 15 may be a tantalum nitride film, a polysilicon film, a tungsten nitride film, or a laminated film (TaN / poly-Si / WN / W) in which a tungsten film is sequentially stacked, or a titanium nitride film, a polysilicon film, or a tungsten nitride film. , A tungsten film may be formed as a stacked film (TiN / poly-Si / WN / W) sequentially stacked.

Next, a hard mask film 16 is formed on the gate conductive film 15. The hard mask film 16 may be formed of any one selected from the group consisting of an oxide film, a nitride film, and an oxynitride, or a laminated film in which these layers are stacked. For example, the hard mask layer 17 may be formed as a laminated layer in which a silicon oxynitride layer (SiON) and a tetraethoxy orthosilicate (TEOS) are stacked.

As shown in FIG. 3B, the gate conductive layer 15 is etched using the hard mask layer 16 as an etch barrier to form the gate electrode 16. An etching process for forming the gate electrode 16 may be performed using a dry etching method, and a plasma etching method may be used as the dry etching method. In this case, the etching process is preferably performed using an inductively coupled plasma (ICP) etching equipment.

Next, a spacer film 17 is formed on both side walls of the hard mask film 16 and both side walls of the gate electrode 15A. The spacer layer 17 serves to prevent damage to (or loss) of the sidewalls of the hard mask layer 16 and the gate electrode 15A during subsequent processes. At this time, the spacer layer 17 is preferably formed to have a thickness in the range of 40 kPa to 70 kPa in order to effectively prevent damage to the sidewalls of the hard mask film 16 and the gate electrode 15A during subsequent processes.

The spacer film 17 may be formed of a single film made of an oxide film or a nitride film, or may be formed of a laminated film (oxide film / nitride film or oxide film / nitride film / oxide film) in which an oxide film and a nitride film are laminated.

Next, the dielectric film 14 is etched using the hard mask film 16 and the spacer film 17 as etch barriers. Hereinafter, the reference numeral of the etched dielectric film 14 is changed to '14A'.

The etching process of the dielectric film 14A may be performed by using a dry etching method, and the plasma etching method may be used as a dry etching method. In this case, the etching process is preferably performed using an inductively coupled plasma (ICP) etching equipment.

In addition, the etching process of the dielectric film 14A may be performed using a mixed gas in which a gas containing chlorine (Cl) and an inert gas are mixed. Here, the gas containing chlorine serves as a main etching gas for etching the dielectric film 14A, and the inert gas serves to generate plasma. In this case, as the gas containing chlorine, BCl ₃ gas, Cl ₂ gas, or the like may be used, and as the inert gas, Ar gas may be used. For example, the etching process of the dielectric film 14A may be performed using a mixed gas (BCl ₃ / Cl ₂ / Ar) in which BCl ₃ gas, Cl ₂ gas, and Ar gas are mixed.

In addition, the etching process of the dielectric film 14 may be performed at a temperature in the range of 100 ° C to 130 ° C.

Meanwhile, a polymer (P) may be generated during the etching process of the dielectric layer 14A, and the generated polymer P may remain in the chamber and on the surface of the substrate 11. The polymer P remaining inside the chamber (or the inner wall) may act as a particle source between processes or may contaminate other substrates (or wafers). Further, due to the polymer P remaining on the surface of the substrate 11, tails may occur on both sidewalls of the charge trap layer 13 during the subsequent etching process of the charge trap layer 13. Therefore, it is preferable to proceed with the subsequent process after removing the polymer (P) generated during the etching process of the dielectric film 14A.

As shown in FIG. 3C, a cleaning process for removing the polymer P generated during the etching process of the dielectric film 14A is performed. At this time, the polymer P remaining inside the chamber (or the inner wall) may be removed by injecting and purging the inert gas into the chamber, and the polymer P remaining on the surface of the substrate 11 may be flushed with oxygen. Can be removed through the process. Hereinafter, the washing step will be described in detail.

First, an inert gas such as argon gas (Ar) is injected into and purged into the chamber to remove polymer P remaining in the chamber (or inner wall), and then an oxygen flush process is performed to polymer remaining on the surface of the substrate 11. Remove (P). At this time, the oxygen flush process is a process similar to the O ₂ plasma treatment process to remove the polymer (P) by reacting the oxygen activated by the plasma with the polymer (P). At this time, in order to improve the polymer (P) removal efficiency during the oxygen flush process, in addition to the oxygen gas (O ₂ ) in addition to the carbon fluoride gas (C _x F _y , x, y is natural water except 0) Can be. As the fluorocarbon gas, CF ₄ gas may be used.

Here, the oxygen flushing step is preferably performed using oxygen gas at a higher flow rate than carbon fluoride gas. For example, the oxygen gas may use a flow rate in the range of 150 sccm to 250 sccm, and the fluorocarbon gas may use a flow rate in the range of 4 sccm to 8 sccm.

Meanwhile, the polymer P remaining in the chamber (or the inner wall) during the oxygen flush process may also be removed.

As shown in FIG. 3D, the hard trap film 16 and the spacer film 17 are used as etching barriers to etch the charge trap film 13 by using a stop on oxide film scheme. Carry out an etching process. Hereinafter, the reference numeral of the etched charge trap film 13 is changed to '13A' and described.

Here, the primary etching process may be referred to as a main etching process, and may be performed using a dry etching method. Plasma etching may be used as the dry etching method. In this case, the first etching process is preferably performed using an inductively coupled plasma (ICP) etching equipment.

Specifically, the present invention is a mixed gas (CH ₂ F ₂ / O CH ₂ F ₂ gas and O ₂ gas in a ratio of 1.5: 1 ~ 2: 1 (CH ₂ F ₂ : O ₂ ) during the first etching process _It is characterized by using ₂ ). In addition, an inert gas such as Ar gas may be further added to the above-described mixed gas for the purpose of forming the charge trap film 13A having the vertical profile of the sidewall (CH ₂ F ₂ / O ₂ / Ar).

Here, conventionally, a mixed gas (CH ₂ F ₂ / CHF ₃ / O ₂ ) in which the CH ₂ F ₂ gas, the CHF ₃ gas, and the O ₂ gas were mixed during the charge trap film 13A etching process was used. At this time, the tunnel insulating film 12 is damaged due to the CHF ₃ gas having a relatively low selectivity to the oxide film (see reference numeral 'B' in FIG. 1). However, according to the present invention, since the CHF ₃ gas is not used during the charge trap film 13A etching process, that is, the primary etching process, the exposed tunnel insulating film 12 may be prevented from being damaged.

On the other hand, in order to prevent damage to the tunnel insulating film 12 exposed during the process, a condition having a large etching selectivity with respect to the tunnel insulating film 12 (for example, using an CH ₂ F ₂ / O ₂ gas as an etching gas) is 1. Since the differential etching is performed, tails T and T may be formed on both sidewalls of the charge trap film 13A. Due to the tail T, adjacent charge trap layers 13A may be interconnected, resulting in deterioration of characteristics of the memory device.

As shown in FIG. 3E, a secondary etching process is performed to remove the tails T formed on both side walls of the charge trap film 13A during the primary etching process. In this case, the secondary etching process may be referred to as an overetch process, and is preferably performed in-situ in the same chamber as the primary etching process. In addition, the secondary etching process may be performed using the same etching method and etching equipment as the primary etching process. Therefore, the secondary etching process may be performed using a dry etching method, for example, a plasma etching method, or may be performed using an inductively coupled plasma (ICP) etching apparatus. Hereinafter, the reference numeral of the secondary-etched charge trap film 13A is changed to '13B' and described.

In addition, the secondary etching process is preferably performed using the tunnel insulating film 12, that is, an etching gas having a large etching selectivity with respect to the oxide film. For example, the secondary etching process may be performed using a mixed gas (HBr / O ₂ ) in which HBr gas and O ₂ gas are mixed.

Here, it is preferable to perform the secondary etching process using HBr gas having a flow rate higher than that of O ₂ gas. For example, the HBr gas may use a flow rate in the range of 150 sccm to 250 sccm, and the O ₂ gas may use a flow rate in the range of 4 sccm to 8 sccm.

In addition, the secondary etching process may be performed using a bias power in the range of 150V to 250V to form the sidewall of the charge trap film 13B to have a vertical profile, that is, to increase the straightness of the etching gas.

For reference, conventionally, the main etching gas was subjected to the transient etching using the CH ₂ F ₂ / CHF ₃ / O ₂ mixed gas. As a result, a problem arises in that the exposed tunnel insulation layer 12 is damaged during the transient etching process. However, the present invention is carried out using a mixed gas in which HBr gas and O ₂ gas are mixed during the transient etching, that is, the secondary etching process, thereby preventing the exposed tunnel insulating film 12 from being damaged and at the same time the charge trap film ( 13B) The tails T formed on both side walls can be removed.

Next, although not shown in the figure, impurities are implanted into the substrate 11 on both sides of the gate electrode 15A to form a junction region. In this case, since the present invention uses a stop-on oxide film scheme, only the tunnel insulation layer 12 may act as a screen barrier to form a junction region having uniform characteristics in the entire substrate 11.

For reference, the junction region may be formed by etching the dielectric film 14A using a Stop On Nitride scheme and then performing an ion implantation process. However, in this case, since the charge trap film 13A and the tunnel insulating film 12 serve as screen barriers, the thickness of the screen barriers is so thick that it is difficult to form a junction region having uniform characteristics in the entire substrate 11. .

4 is a cross-sectional image illustrating a charge trapping nonvolatile memory device according to an exemplary embodiment of the present invention.

As shown in FIG. 4, the present invention may confirm that tails are not formed on both sidewalls of the charge trap film 13A through primary and secondary etching processes (reference numeral 'A' of FIGS. 3E and 4). Reference).

As described above, the present invention does not use the CHF ₃ gas during the primary etching, thereby preventing the exposed tunnel insulation layer 12 from being damaged (or lost).

In addition, according to the present invention, the secondary etching is performed by using the mixed gas mixed with the HBr gas and the O ₂ gas, thereby removing the tail T of both side walls of the charge trap film 13B and damaging the tunnel insulating film 12. Can be prevented.

In addition, the present invention removes the polymer (P) generated during the etching process of the dielectric film (14A) through the cleaning process, thereby deepening the formation of the tail (T) of the side walls of the charge trap film (13B) by the polymer (P). Can be prevented. In addition, the contamination of the chamber and the substrate 11 by the polymer P can be prevented.

Although the technical spirit of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will appreciate that various embodiments within the scope of the technical idea of the present invention are possible.

1 is a cross-sectional view showing a charge trap type nonvolatile memory device having a TANOS structure according to the prior art.

Figure 2 is an image showing a problem according to the prior art.

3A through 3E are cross-sectional views illustrating a method of manufacturing a charge trap type nonvolatile memory device according to an exemplary embodiment of the present invention.

4 is an image showing a charge trap type memory device according to an embodiment of the present invention.

* Description of symbols on the main parts of the drawings *

11 substrate 12 tunnel insulating film

13, 13A, 13B: charge trap film 14, 14A: dielectric film

15: gate conductive film 15A: gate electrode

16: hard mask film 17: spacer film

Claims (19)

Forming a tunnel insulating film made of an oxide film on the substrate; Forming a charge trap film made of a nitride film on the tunnel insulating film; Sequentially forming a dielectric film, a gate conductive film, and a hard mask film on the charge trap film; Etching the gate conductive layer using the hard mask layer as an etch barrier to form a gate electrode; Etching the dielectric layer using the hard mask layer as an etch barrier; A first etching step of etching the charge trap layer by using the hard mask layer as an etching barrier; And A secondary etching step of removing tails of both side walls of the charge trap layer formed during the first etching Charge trap type non-volatile memory device manufacturing method comprising a. The method of claim 1, Before the first etching step, And removing the polymer generated during the etching of the dielectric film. The method of claim 2, Removing the polymer, Injecting and purging Ar gas into the chamber to remove polymer remaining inside the chamber; And Injecting oxygen gas into the chamber to perform an oxygen flush process to remove polymer remaining on the substrate surface Charge trap type non-volatile memory device manufacturing method comprising a. The method of claim 3, In the oxygen flush process, A charge trapping type nonvolatile memory device for injecting carbon fluoride gas further into the chamber. The method of claim 4, wherein In the oxygen flush process, A charge trapping nonvolatile memory device manufacturing method using the oxygen gas at a higher flow rate than the fluorocarbon gas. The method of claim 5, The oxygen gas uses a flow rate in the range of 150sccm ~ 250sccm, the carbon fluoride gas using a flow rate of 4sccm ~ 8sccm range. The method of claim 1, And the first etching and the second etching are performed in situ in the same chamber. The method of claim 1, The first etching step, A method for manufacturing a charge trapping nonvolatile memory device using a mixed gas in which a CH ₂ F ₂ gas and an O ₂ gas are mixed at a ratio of 1.5: 1 to 2: 1 (CH ₂ F ₂ : O ₂ ). The method of claim 8, The first etching step, And adding Ar gas to the mixed gas. The method of claim 1, The secondary etching step, A charge trapping nonvolatile memory device manufacturing method using a mixed gas of HBr gas and O ₂ gas. The method of claim 10, The secondary etching step, A method for manufacturing a charge trapping nonvolatile memory device using the HBr gas at a flow rate higher than that of the O ₂ gas. The method of claim 11, The secondary etching step, The HBr gas uses a flow rate in the range of 150sccm ~ 250sccm, the O ₂ gas is used in the flow rate of 4sccm ~ 8sccm range. The method of claim 1, The secondary etching step, A method of manufacturing a charge trapping nonvolatile memory device using bias power in a range of 150V to 250V. The method of claim 1, The dielectric film, Any one selected from the group consisting of aluminum oxide (Al ₂ O ₃ ), hafnium oxide (HfO ₂ ), zirconium oxide (ZrO ₂ ), yttrium oxide (Y ₂ O ₃ ) and lanthanum oxide (La ₂ O ₃ ) A method for manufacturing a charge trapping nonvolatile memory device, which is formed of a laminated film. The method of claim 14, Etching the dielectric film, A charge trapping nonvolatile memory device manufacturing method using a mixed gas of BCl ₃ gas, Cl ₂ gas and Ar gas. The method of claim 1, Forming the gate electrode, etching the dielectric film, and the primary and secondary etching step, A method of manufacturing a charge trap type nonvolatile memory device using an inductively coupled plasma (ICP) etching apparatus. The method of claim 1, The gate electrode, A charge trapping type nonvolatile memory device comprising a tantalum nitride film (TaN) or a titanium nitride film (TiN). The method of claim 1, After forming the gate electrode, And forming a spacer layer on both sidewalls of the hard mask layer and both sidewalls of the gate electrode. The method of claim 18, The spacer film, It is formed of any one selected from the group consisting of a single film consisting of an oxide film or a nitride film, a laminated film in which an oxide film and a nitride film are laminated (an oxide film / nitride film), and a laminated film in which an oxide film, a nitride film and an oxide film are sequentially stacked. A method of manufacturing a charge trapping nonvolatile memory device.

Images