KR20100078986A - Method for fabricating charge trap type nonvolatile memory device - Google Patents

Abstract

PURPOSE: A method for manufacturing a charge trap type nonvolatile memory device is provided to use vapor etching during a charge trap film etching process, thereby preventing a tail from being formed on both side walls of a charge trap film. CONSTITUTION: A turner insulating film(12), a charge trap film(13A), a dielectric film(14A), and a gate conductive film are successively formed on a substrate(11). A gate conductive film is etched by a hard mask film(16) to form a gate electrode(15A). A capping film(17) is formed on both side walls of the hard mask film and both side walls of the gate electrode. The dielectric film is etched by the hard mask film and the capping film. Vapor etching is performed using the hard mask film and the capping film to etch the charge trap film.

Description

METHODS FOR FABRICATING CHARGE TRAP TYPE NONVOLATILE MEMORY DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a manufacturing technique of a semiconductor device, and more particularly, to a manufacturing method of a charge trap type nonvolatile memory device (CTD).

Recently, in order to implement highly integrated nonvolatile memory devices of 40 nm or less, research on charge trap type nonvolatile memory devices has been actively conducted. The charge trap type nonvolatile memory device has a structure in which a tunnel insulating film, a charge trap film, a dielectric film, and a gate electrode are sequentially stacked on a substrate, and have trap sites having a deep level in the charge trap film. Data is stored by trapping (or capturing) the charge on it.

1 is a cross-sectional view showing a charge trap type nonvolatile memory device according to the prior art.

Referring to FIG. 1, a method of manufacturing a charge trapping nonvolatile memory device includes a tunnel insulating film 101 made of an oxide film, a charge trap film 102 made of a nitride film, a dielectric film 103, and the like on a silicon substrate 100. After the gate conductive film and the hard mask film 105 are sequentially formed, the gate conductive film is etched using the hard mask film 105 as an etch barrier to form the gate electrode 104.

Next, after the capping film 106 is formed on both sidewalls of the hard mask film 105 and the gate electrode 104, the stop layer oxide is stopped on the hard mask film 105 and the capping film 106 as an etch barrier. The dielectric film 103 and the charge trap film 102 are etched using an oxide scheme.

However, the related art uses plasma etching in the process of etching the dielectric film 103 and the charge trap film 102 using the hard mask film 105 and the capping film 106 as an etch barrier. At this time, a micro trench (refer to 'C' in FIG. 1) is generated on the surface of the tunnel insulation film 101 by plasma, or a charge in the plasma damages the tunnel insulation film 101. There is a problem that deteriorates the characteristics of the memory device.

In addition, the prior art has a problem that the tunnel insulating film 101 exposed by the charge trap film 102 is damaged due to the lack of etching selectivity with the tunnel insulating film 101 during the charge trap film 102 etching process ( See reference numeral 'B' in FIG. 1).

In order to solve this problem, when an etching condition with a large etching selectivity with respect to the tunnel insulating film 101 is used during the etching process of the charge trap film 102, the sidewalls of the charge trap film 102 are not vertically etched and the charge trap is not etched. A problem arises in which tails (T) are formed on both side walls of the film (see reference numeral 'A' in FIG. 1). As such, when the tails T are formed on both sidewalls of the charge trap layer 102, a problem occurs in that adjacent charge trap layers 102 are interconnected by the tail T. When adjacent charge trap layers 102 are connected to each other, a problem of deterioration of characteristics of the memory device may occur due to horizontal movement of charges stored in the charge trap layers.

Therefore, when overetching is additionally performed to prevent the tail T from being formed, a problem arises in that the tunnel insulating film 101 is damaged due to the overetching (see reference numeral 'B' in FIG. 1). ).

SUMMARY OF THE INVENTION The present invention has been proposed to solve the above problems of the prior art, and an object thereof is to provide a method for manufacturing a charge trap type nonvolatile memory device capable of preventing the tunnel insulating film from being damaged by plasma.

Another object of the present invention is to provide a method for manufacturing a charge trapping nonvolatile memory device capable of preventing tails from being formed on both side walls of the charge trapping film.

Another object of the present invention is to provide a method for manufacturing a charge trapping type nonvolatile memory device capable of preventing damage (or loss) of a tunnel insulating layer exposed during a charge trapping film etching process.

According to an aspect of the present invention, there is provided a method of manufacturing a charge trapping nonvolatile memory device, including sequentially forming a tunnel insulating film, a charge trapping film, a dielectric film, and a gate conductive film on a substrate; Forming a gate electrode by etching the gate conductive layer using an hard barrier layer as an etch barrier; Forming a capping layer on both sidewalls of the hard mask layer and both sidewalls of the gate electrode; Etching the dielectric layer using the hard mask layer and the capping layer as an etch barrier, and etching the charge trap layer by sequentially performing neutron etching and vapor etching with the hard mask layer and the capping layer as etch barriers.

The present invention, based on the above-described problem solving means, by sequentially performing neutron etching and steam etching to etch the charge trap film, to prevent damage to the tunnel insulating film between the process and at the same time the tail is formed on both sides of the charge trap film There is an effect that can be prevented. In addition, there is an effect that the tunnel insulating film can be prevented from being damaged by the plasma in the charge trap film etching process and the charge in the plasma.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings, in order to facilitate a person skilled in the art to easily carry out the technical idea of the present invention.

According to the present invention described below, a charge trapping type nonvolatile memory device capable of preventing a tail from being formed on both sidewalls of a charge trapping film between processes and preventing the exposed tunnel insulating film from being lost (or damaged). memory device) is provided. To this end, according to the present invention, the neutron etching and the vapor etching are continuously performed during the charge trap film etching process.

2A through 2D are cross-sectional views illustrating a method of manufacturing a charge trap type nonvolatile memory device according to an exemplary embodiment of the present invention.

As shown in Fig. 2A, a tunnel insulating film 12 is formed on a substrate 11, for example, a silicon substrate. The tunnel insulation film 12 may be formed of an oxide film, for example, silicon oxide film (SiO ₂ ), and the silicon oxide film for the tunnel insulation film 12 may be formed using a thermal oxidation method. In this case, the tunnel insulating layer 12 may be formed to have a thickness of 30 μs or more, for example, 30 μs to 40 μs in order to improve data retention characteristics of the memory device.

Next, the charge trap film 13 is formed on the tunnel insulating film 12. The charge trap film 13 is a space in which charge is stored, that is, a space in which data is stored, and is preferably formed of a material having a deep level trap site in the film. For example, the charge trap film 13 may be formed of a nitride film. In this case, a silicon nitride film (Si ₃ N ₄ ) may be used as the nitride film.

The charge trap film 13 may be formed to have a thickness in the range of 50 kV to 60 kV.

Next, the dielectric film 14 is formed on the charge trap film 13. The dielectric film 14 is preferably formed of a material having a high dielectric constant (High-K). Here, a material having a high dielectric constant greater than that of a silicon oxide film. Therefore, it means a material having a dielectric constant of 3.9 or more.

Specifically, the dielectric film 14 may be formed of a metal oxide film having a high dielectric constant. As the metal oxide film, any one selected from the group consisting of aluminum oxide film (Al ₂ O ₃ ), hafnium oxide film (HfO ₂ ), zirconium oxide film (ZrO ₂ ), yttrium oxide film (Y ₂ O ₃ ), and lanthanum oxide film (La ₂ O ₃ ) One or these can be formed into a laminated film in which they are laminated.

Next, the gate conductive film 15 is formed on the dielectric film 14. The gate conductive film 15 may be formed of a silicon film, a metallic film, or a laminated film in which a silicon film and a metallic film are stacked. As the silicon film, a polysilicon film (poly Si), a silicon germanium film (SiGe), or the like can be used. Tungsten film (W), titanium film (Ti), tantalum film (Ta), tungsten nitride film (WN), tantalum nitride film (TaN), titanium nitride film (TiN), tungsten silicide (WSi) and the like can be used as the metallic film. .

Here, the gate conductive film 15 in contact with the dielectric film 14 is preferably formed of a material having a larger work function than silicon, such as a tantalum nitride film or a titanium nitride film. This reduces the electron injection from the gate electrode to the charge trap film 13 during the erase operation when a material having a work function larger than that of silicon is formed on the dielectric film 14 and used as the gate electrode. This is because the erase speed can be improved.

For example, the gate conductive film 15 may be a tantalum nitride film, a polysilicon film, a tungsten nitride film, or a laminated film (TaN / poly-Si / WN / W) in which a tungsten film is sequentially stacked, or a titanium nitride film, a polysilicon film, or a tungsten nitride film. , A tungsten film may be formed as a stacked film (TiN / poly-Si / WN / W) sequentially stacked.

Next, a hard mask film 16 is formed on the gate conductive film 15. The hard mask film 16 may be formed of any one selected from the group consisting of an oxide film, a nitride film, and an oxynitride, or a laminated film in which these layers are stacked. For example, the hard mask layer 17 may be formed as a laminated layer in which a silicon oxynitride layer (SiON) and a tetraethoxy orthosilicate (TEOS) are stacked.

As shown in FIG. 2B, the gate conductive layer 15 is etched using the hard mask layer 16 as an etch barrier to form the gate electrode 15A. An etching process for forming the gate electrode 15A may be performed using a dry etch method, and a plasma etch method may be used as the dry etching method.

Next, the capping film 17 is formed on both side walls of the hard mask film 16 and both side walls of the gate electrode 15A. The capping layer 17 serves to prevent damage (or loss) of the sidewalls of the hard mask layer 16 and the gate electrode 15A during the subsequent processes, and may be formed of a nitride layer. As the nitride film, a silicon nitride film can be used.

Here, the present invention is characterized in that it is formed thicker than the thickness of the capping film 17 is formed conventionally. Specifically, the capping film 17 of the present invention is preferably formed at least twice as thick as the thickness of the capping film 17 remaining at the time when the charge trap film 13 etching process is completed (see FIG. 2D). This is hard to prevent damage to the tunnel insulation layer 12 due to plasma and charge in the plasma during subsequent processes, in particular, during the etching of the charge trap layer 13. This is to prevent the loss of the mask film 16 and the gate electrode 15A. In particular, a capping film made of a nitride film because the etching selectivity of the tunnel insulating film 12 is greater than that of the charge trap film 13 during vapor etching, that is, the oxide film does not etch well and the nitride film proceeds using an etching gas that etches well. Since much loss of (17) occurs, it is preferable to form the deposition thickness of the first capping film 17 thicker than usual.

For example, assuming that the capping layer 17 is formed to have a thickness in the range of 40 μs to 70 μs in a charge trap type nonvolatile memory device to which a 40 nm-class design rule is applied, in the embodiment of the present invention, 80 μs to 140 μs It is preferable to form to have a thickness of.

Next, the dielectric film 14 is etched using the hard mask film 16 and the capping film 17 as etch barriers. The etching process of the dielectric film 14 may be performed using a dry etching method, and the dry etching method may be performed using a plasma etching method. Hereinafter, the reference numeral of the etched dielectric film 14 is changed to '14A'.

In the present invention, since the neutron etching and the vapor etching are sequentially performed in the subsequent charge trap film 13 etching process, the sidewalls of the dielectric film 14A are formed at the time when the charge trap film 13 etching process is completed. 13) The sidewall of the dielectric film 14A is formed to have a recessed structure toward the inside of the capping film 17 during the etching process of the dielectric film 14A in order to prevent the sidewall or the capping film 17 from protruding outward from the sidewall. It is desirable to. This is because the etching selectivity of the tunnel insulating film 12 is greater than that of the charge trap film 13 during the vapor etching process, that is, the oxide film is not etched well but the nitride film is etched well.

To this end, during the etching process of the dielectric film 14A, the etching rate in the horizontal direction of the substrate 11 may be faster than the etching rate in the vertical direction of the substrate 11. For example, by adjusting the chuck temperature in the etching chamber to adjust the substrate 11 temperature in the range of 120 ℃ to 250 ℃, using a bias power (bias power in the range of 10W ~ 50W, for example) When the etching process is performed, the sidewalls of the dielectric film 14A may be formed to have a recessed structure toward the capping layer 17 while minimizing the loss of the exposed charge trap film 13.

As illustrated in FIG. 2C, the charge trap layer 13 is etched by performing neutron etching on the hard mask layer 16 and the capping layer 17 as an etch barrier. In this case, the etching process of the charge trap layer 13 using neutron etching may be referred to as a main etching. Hereinafter, the reference numeral of the etched charge trap film 13 is changed to '13A' and described.

Neutron etching is an etching process using neutral particles from which charges of ions generated by plasma are removed. Accordingly, the present invention can prevent damage (or loss) of the tunnel insulating film 12 by plasma and charge in the plasma by etching the charge trap film 13A using neutron etching. In this case, since the neutron etching has an anisotropic etching characteristic, the sidewalls of the capping layer 17 and the sidewalls of the charge trap layer 13A may be co-linear.

In addition, since the neutron etching is etched using the neutral particles, the selectivity between the thin films is poor. Therefore, the etching process of the charge trap film 13A using neutron etching of the present invention is preferably performed only until the surface of the tunnel insulating film 12 is exposed. This is to prevent the tunnel insulation film 12 from being damaged (or lost) by the neutral particles.

On the other hand, since the neutron etching is performed under the condition that the surface of the tunnel insulating film 12 is exposed in order to prevent the tunnel insulating film 12 from being damaged by the neutral particles, tails may be formed on both side walls of the charge trap film 13A. have. When adjacent charge trap layers 13A are interconnected by the tails remaining on both side walls of the charge trap layers 13A, the characteristics of the memory device may be degraded due to the horizontal movement of the charges stored in the charge trap layers 13A. Done.

As shown in FIG. 2D, steam etching is performed to remove tails remaining on both side walls of the charge trap film 13A. In this case, the steam etching may proceed in-situ in the same chamber as the neutron etching, and the etching of the charge trap layer 13A using the steam etching may be referred to as overetching. Hereinafter, the reference numeral of the vapor-etched capping film 17 is changed to '17A' and the reference numeral of the charge trap film 13A is changed to '13B'.

Here, in order to prevent damage (or loss) of the tunnel insulating film 12 during the vapor etching process, etching conditions having a large etching selectivity between the charge trap film 13B and the tunnel insulating film 12, for example, the oxide film may not be etched well. The nitride film is preferably carried out using an etching gas which is well etched. At this time, since the vapor etching has an isotropic etching characteristic, the capping film 17A made of a nitride film is also partially etched during the etching process, but since the deposition thickness of the first capping film 17A is formed thicker than usual, the capping film 17A is formed. ) It is possible to prevent the problems caused by loss.

Further, during vapor etching, the capping film 17A, the dielectric film 14A, and the charge trap film are positioned on the same line as the capping film 17A sidewall, the dielectric film 14A sidewall, and the sidewall of the charge trap film 13B. It is preferable to adjust the etching time so that the sidewall of the pattern on which 13B is laminated has a vertical profile.

As described above, the present invention can prevent the tunnel insulation film 12 from being damaged (or lost) by neutron etching during the charge trap film etching process.

In addition, the present invention can prevent the formation of the tail on both side walls of the charge trap film 13B by using steam etching during the charge trap film etching process.

Although the technical spirit of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will appreciate that various embodiments within the scope of the technical idea of the present invention are possible.

1 is a cross-sectional view showing a charge trap type nonvolatile memory device according to the prior art.

2A to 2D are cross-sectional views illustrating a method of manufacturing a charge trap type nonvolatile memory device according to an exemplary embodiment of the present invention.

* Description of symbols on the main parts of the drawings *

11 substrate 12 tunnel insulating film

13, 13A, 13B: charge trap film 14, 14A: dielectric film

15: gate conductive film 15A: gate electrode

16: hard mask film 17, 17A: capping film

Claims (9)

Sequentially forming a tunnel insulating film, a charge trap film, a dielectric film, and a gate conductive film on the substrate; Forming a gate electrode by etching the gate conductive layer using an hard barrier layer as an etch barrier; Forming a capping layer on both sidewalls of the hard mask layer and both sidewalls of the gate electrode; Etching the dielectric layer using the hard mask layer and the capping layer as an etch barrier; And Etching the charge trap layer by sequentially performing neutron and vapor etching on the hard mask layer and the capping layer as an etch barrier; Charge trap type non-volatile memory device manufacturing method comprising a. The method of claim 1, The neutron etching is, The charge trapping type nonvolatile memory device of claim 1, wherein the method is performed until the surface of the tunnel insulating layer is exposed. The method of claim 1, Etching the dielectric film, And etching sidewalls of the dielectric layer to be recessed inwardly of the capping layer. The method of claim 3, Etching the dielectric film, And a etch rate in the substrate horizontal direction is higher than the etch rate in the vertical direction of the substrate. The method of claim 4, wherein Etching the dielectric film, And the substrate temperature is in the range of 120 ° C to 250 ° C and is performed using a bias power in the range of 10W to 50W. The method of claim 3, During the neutron etching, The sidewall of the dielectric layer has a structure recessed inwardly than the sidewall of the capping layer and the sidewall of the charge trapping layer, and the sidewall of the capping layer and the sidewall of the chargetrapping layer are etched to be located on the same line. Way. The method of claim 3, During the steam etching, And capping the sidewalls of the capping layer, the sidewalls of the dielectric layer, and the sidewalls of the charge trapping layer so that they are colinear with each other. The method of claim 1, Forming the capping film, And forming a thickness of at least two times thicker than the thickness of the capping layer remaining at the time when the charge trap layer etching process is completed. The method of claim 1, And the tunnel insulating film comprises an oxide film and the charge trap film comprises a nitride film.

Images