TWI559455B - Method for manufacturing non-volatile memory - Google Patents

Description

Non-volatile memory manufacturing method

The present invention relates to a method of fabricating a memory device, and more particularly to a method of fabricating a non-volatile memory.

With the rapid development of the electronic information industry, the production of memory components is one of the important technologies in the semiconductor industry today. Among various memory-related products, non-volatile memory has the advantage of being able to store, read, or erase multiple data, and the stored data does not disappear after power-off. A memory component widely used in personal computers and electronic devices.

A typical non-volatile memory component can have a stacked Stacked-Gate structure including a floating gate and a control gate fabricated with doped polysilicon. The floating gate is located between the control gate and the substrate and is not connected to any circuit. The control gate is connected to the word line (Word Line). In addition, the tunneling oxide layer (Tunneling Oxide) and the gate chamber are also included. An Inter-Gate Dielectric Layer is located between the substrate and the floating gate and between the floating gate and the control gate.

In recent years, in the fabrication technology of memory devices, a design has been proposed in which a charge trapping layer containing tantalum nitride is used in place of a conventional polysilicon floating gate. The tantalum nitride charge trapping layer usually has a layer of yttrium oxide on top of each other to form a stacked structure comprising a yttria/nitride-oxide (ONO) layer. An element having such a gate structure may be referred to as a silicon-oxide-nitride-oxide-silicon (SONOS) memory element.

With the rapid development of technology, the accumulation of semiconductor-related components continues to increase, so the size of various memory components must be further reduced to speed up the operation. However, when the size of the memory element is to be reduced, serious problems such as a short channel effect and deterioration in stability are caused. In order to further improve the reliability and stability of components, it is necessary to provide a technical solution capable of improving the above problems.

The present invention provides a method of manufacturing a non-volatile memory that can avoid the generation of a short channel effect and further improve the reliability and stability of the memory element.

The method for manufacturing a non-volatile memory provided by the present invention comprises: sequentially forming a composite layer, a first conductor layer and a first cap layer on a substrate; and the first cap layer, the first conductor layer, the composite layer, and The substrate is patterned to form a plurality of shallow trenches in the substrate, the shallow trenches extending in a first direction; and an element isolation structure is formed in the shallow trenches, wherein a surface of the component isolation structure is located on the first cap layer And substrate Patterning the first cap layer, the first conductor layer, the composite layer, and the substrate to form a plurality of trenches in the substrate, the trenches extending in the second direction, wherein the first direction and the second direction Interleaving; forming an insulating layer and a second conductor layer in the trench, wherein the insulating layer surrounds and covers the second conductor layer; removing the first cap layer and forming a second surface on both sides of the exposed insulating layer a cap layer; and a second cap layer as a mask, patterning the first conductor layer and the composite layer such that the first conductor layer is formed as a control gate.

In an embodiment of the invention, the step of forming the insulating layer and the second conductor layer in the trench includes: forming a first insulating material layer on the inner wall of the trench; forming a second conductor filling the trench a material layer; removing at least a portion of the second conductor material layer in the trench; and forming a second insulating material layer to cover the second conductor material layer.

In an embodiment of the invention, the step of forming a second cap layer on each side of the exposed insulating layer comprises: forming a capping material layer on the insulating layer and the first conductor layer; removing the cap material Part of the layer.

In an embodiment of the invention, the method further includes performing a doping process on the substrate to form a source region and a drain region.

In an embodiment of the invention, the step of forming the element isolation structure includes: forming an insulating material layer in each shallow trench; planarizing the insulating material layer; and removing a portion of the insulating material layer.

In an embodiment of the invention, the composite layer comprises yttrium oxide/yttria/yttria.

In an embodiment of the invention, the material of the first conductor layer and the second conductor layer comprises a doped polysilicon.

In an embodiment of the invention, the material of the first cap layer comprises tantalum nitride.

In an embodiment of the invention, the material of the second cap layer comprises tantalum nitride.

In an embodiment of the invention, the material of the insulating layer comprises yttrium oxide.

Based on the above, with the method of manufacturing a non-volatile memory provided by the present invention, it is possible to avoid the short channel effect of the memory element and further improve the reliability and stability of the semiconductor element. Further, in the manufacturing method provided by the present invention, the manufacturing steps can be further simplified by using a self-aligned process or the like, thereby more efficiently manufacturing the non-volatile memory element.

The above described features and advantages of the invention will be apparent from the following description.

100‧‧‧Base

102‧‧‧Composite layer

102a‧‧‧Charge storage structure

104‧‧‧First conductor layer

104a‧‧‧Control gate

106‧‧‧First cover

108‧‧‧ trench

110, 200‧‧‧ insulation

110a‧‧‧First insulating material layer

110b‧‧‧Second layer of insulating material

112‧‧‧Second conductor layer

112a‧‧‧Second conductor material layer

114‧‧‧Second top cover

114a‧‧‧Top cover material layer

116‧‧‧ source area

118‧‧‧Bungee Area

1A-1G are schematic cross-sectional views showing a method of manufacturing a non-volatile memory according to an embodiment of the invention.

2A-2F are schematic cross-sectional views showing the flow of a method of manufacturing a non-volatile memory according to an embodiment of the invention.

1A-1G are schematic cross-sectional views showing a method of manufacturing a non-volatile memory according to an embodiment of the invention. It should be noted that the cross-sections shown in FIGS. 1A to 1G are parallel to the bit-line direction of the memory cell (or perpendicular to the word line direction of the memory cell); FIGS. 2A to 2F are shown. The profile is parallel to the direction of the word line of the memory cell (or perpendicular to the direction of the bit line of the memory cell).

First, referring to FIG. 1A and FIG. 2A, the composite layer 102, the first conductor layer 104, and the first cap layer 106 are sequentially formed on the substrate 100. The substrate 100 is, for example, a crucible substrate.

The composite layer 102 is composed of, for example, a bottom dielectric layer, a charge trapping layer, and a top dielectric layer. The material of the bottom dielectric layer is, for example, ruthenium oxide, and the formation method thereof is, for example, a thermal oxidation method. The material of the charge trapping layer is, for example, tantalum nitride, and the formation method thereof is, for example, a chemical vapor deposition method. The material of the top dielectric layer is, for example, ruthenium oxide, and the formation method thereof is, for example, chemical vapor deposition. Of course, the bottom dielectric layer and the top dielectric layer may also be other similar materials. The material of the charge trapping layer is not limited to tantalum nitride, and may be other materials capable of trapping charges therein, such as a tantalum oxide layer, a barium titanate layer, a tantalum oxide layer, or a doped polysilicon. In the present embodiment, the material of the composite layer 102 is, for example, a yttria/niobium nitride/yttria composite layer.

The material of the first conductor layer 104 is, for example, doped polysilicon. The formation method is, for example, forming an undoped polysilicon layer by chemical vapor deposition, and then performing an ion implantation step to form the substrate. It is formed by chemical vapor deposition in a manner of doping.

The material of the first cap layer 106 is, for example, tantalum nitride, and the forming method thereof is, for example, a chemical vapor deposition method.

Next, the first cap layer 106, the first conductor layer 104, the composite layer 102, and the substrate 100 are patterned to form a plurality of shallow trenches in the substrate 100, and the shallow trenches are along the first direction (ie, Extending in a direction parallel to the direction of the bit line of the memory cell to be formed, and then forming the insulating layer 200 in each shallow trench, thereby obtaining a structure as shown in FIG. 2A. The material of the insulating layer 200 is, for example, cerium oxide. The method for forming the insulating layer 200 is, for example, first forming an insulating material layer in each shallow trench by chemical vapor deposition, and then, after planarizing the insulating material layer by chemical mechanical polishing, etching is performed to remove a portion. The insulating material layer is formed to form the insulating layer 200, wherein the surface of the insulating layer 200 is located between the first capping layer 106 and the substrate 100, and the insulating layer 200 is used as an element isolation structure.

Next, referring to FIG. 1B and FIG. 2B, the first cap layer 106, the first conductor layer 104, the composite layer 102, and the substrate 100 are patterned by a mask (not shown) to form a plurality of layers in the substrate 100. The trenches 108 extend in the second direction (ie, a direction parallel to the direction of the word line of the memory cell to be formed, which is interlaced with the aforementioned first direction). The bottoms of the trenches 108 are located in the substrate 100, and from the surface of the first capping layer 106, the depth of the trenches 108 is, for example, 100 nm to 500 nm, and the bottom of the trenches 108 is unpatterned. The distance of the surface of the substrate 100 is, for example, 10 nm to 100 nm, but is not limited thereto. It will be understood by those of ordinary skill in the art that by removing a portion of the substrate 100 such that the bottom of the trench 108 is within the substrate 100, a longer channel length can be obtained. Thereby avoiding the occurrence of short channel effects.

Thereafter, referring to FIG. 1C and FIG. 2C, a conformal first insulating material layer 110a is formed on the inner wall of the trench 108, and then the remaining portion of the trench 108 is formed on the first insulating material layer 110a. A portion of the second layer of conductor material 112a. The material of the first insulating material layer 110a is, for example, cerium oxide. The material of the second conductor material layer 112a is, for example, doped polysilicon. The method for forming the first insulating material layer 110a is, for example, a chemical vapor deposition method, and the method for forming the second conductive material layer 112a is formed by, for example, chemical vapor deposition combined with an ion implantation step, or by using a field implant. The way of doping is formed by chemical vapor deposition.

Then, referring to FIG. 1D and FIG. 2D, at least a portion of the second conductive material layer 112a in the trench 108 is removed, and a second insulating material layer 110b is formed. The second insulating material layer 110b covers the surface of the second conductor material layer 112a. Thereby, the insulating layer 110 and the second conductor layer 112 can be formed in the trench 108, and the insulating layer 110 composed of the first insulating material layer 110a and the second insulating material layer 110b surrounds and covers the second conductive layer 112.

The material of the second conductor layer 112 is, for example, doped polysilicon. In addition, the method of removing at least a portion of the second conductive material layer 112a in the trench and forming the second insulating material layer 110b is performed by, for example, planarizing by chemical mechanical polishing, and performing etch back. At least a portion of the second conductive material layer 112a is removed, and then the second insulating material layer 110b is deposited by chemical vapor deposition, and finally a chemical mechanical polishing is performed. In addition, the material of the second insulating material layer 110b may be the same as the first insulating material layer 110a, for example, yttrium oxide.

Next, referring to FIG. 1E and FIG. 2E, the first cap layer 106 is removed. The method of removing the first cap layer 106 is, for example, removal by wet etching using an etching solution such as phosphoric acid (H ₃ PO ₄ ). Then, a capping material layer 114a is formed on the insulating layer 110 and the first conductor layer 104 exposed after the first cap layer 106 is removed. The material of the cap material layer 114a is, for example, tantalum nitride. The method of forming the cap material layer 114a is, for example, a chemical vapor deposition method.

Referring to FIGS. 1F and 2F, a portion of the cap material layer 114a is removed, and a second cap layer 114 is formed on each of the exposed insulating layers 110. A method of removing a portion of the cap material layer 114a is, for example, an anisotropic etching method.

Finally, referring to FIG. 1G, the first cap layer 114 and the composite layer 102 are patterned by using the second cap layer 114 as a mask, and the patterning uses an anisotropic etching process to form the first conductor layer 104 as The gate 104a is controlled. The composite layer 102 patterned as described above is, for example, a charge storage structure 102a, and the second conductor layer 112 is, for example, a word line gate. In addition, the substrate 100 may be further doped to form a source region 116 and a drain region 118, which may also be a drain region and 118 a source region.

In summary, the method for manufacturing a non-volatile memory provided by the present invention can avoid the short channel effect of the memory element, and can further improve the reliability and stability of the semiconductor element. Specifically, in the manufacturing method provided by the present invention, a deep-depth groove is formed by removing a part of the substrate, and an element having a longer channel length can be obtained, thereby avoiding occurrence of a short-channel effect; By using a damascene process and a self-aligned process (self-aligned) The process steps such as the conventional use of the photomask can be further simplified, and the manufacture of components such as a single memory cell (2 bit/cell) SONOS memory can be performed more efficiently.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

100‧‧‧Base

102a‧‧‧Charge storage structure

104a‧‧‧Control gate

110‧‧‧Insulation

112‧‧‧Second conductor layer

114‧‧‧Second top cover

116‧‧‧ source area

118‧‧‧Bungee Area

Claims (10)

A method for manufacturing a non-volatile memory, comprising: sequentially forming a composite layer, a first conductor layer and a first cap layer on a substrate; the first cap layer, the first conductor layer, The composite layer and the substrate are patterned to form a plurality of shallow trenches in the substrate, the shallow trenches extending along a first direction; and an element isolation structure is formed in the shallow trenches, the component The surface of the isolation structure is located between the cap layer and the substrate; the first cap layer, the first conductor layer, the composite layer and the substrate are patterned to form a plurality of trenches in the substrate, The trenches extend along a second direction, wherein the first direction is staggered with the second direction; an insulating layer and a second conductor layer are formed in the trenches, wherein the insulating layer surrounds the first layer a second conductor layer; removing the first cap layer and forming a second cap layer on both sides of the exposed insulating layer; and patterning the first cap layer as a mask a conductor layer and the composite layer such that the first conductor layer is formed as a control gate The method for manufacturing a non-volatile memory according to claim 1, wherein the step of forming the insulating layer and the second conductor layer in the trenches comprises: forming a sidewall on the inner walls of the trenches a first layer of insulating material; forming a second layer of conductive material filling the trenches; Removing at least a portion of the second layer of conductor material in the trenches; and forming a second layer of insulating material to cover the second layer of conductor material. The method for manufacturing a non-volatile memory according to claim 1, wherein the step of forming the second cap layer on both sides of the exposed insulating layer comprises: the insulating layer and the first Forming a layer of capping material on a conductor layer; and removing a portion of the capping material layer. The method for manufacturing a non-volatile memory according to claim 1, further comprising: performing a doping process on the substrate to form a source region and a drain region. The method for manufacturing a non-volatile memory according to claim 1, wherein the step of forming the element isolation structure comprises: forming an insulating material layer in each of the shallow trenches; planarizing the insulating material layer And removing a portion of the layer of insulating material. The method for producing a non-volatile memory according to claim 1, wherein the material of the composite layer comprises cerium oxide/cerium nitride/cerium oxide. The method for manufacturing a non-volatile memory according to claim 1, wherein the material of the first conductor layer and the second conductor layer comprises doped polysilicon. The method for manufacturing a non-volatile memory according to claim 1, wherein the material of the first cap layer comprises tantalum nitride. Manufacturer of non-volatile memory as described in claim 1 The method, wherein the material of the second cap layer comprises tantalum nitride. The method for producing a non-volatile memory according to claim 1, wherein the material of the insulating layer comprises cerium oxide.