TWI508232B - Non-volatile memory cell and method of the same - Google Patents

Description

Non-volatile memory cell and method of making same

The present invention relates to an integrated circuit and a method of fabricating the same, and more particularly to a non-volatile memory cell and a method of fabricating the same.

Non-volatile memory allows multiple data stylization, reading and erasing operations, and even saves the data stored in the memory after the power is interrupted. Because of these advantages, non-volatile memory has become a widely used memory in personal computers and electronic devices.

Well-known electrically programmable and erasable non-volatile memory technologies such as electronic erasable programmable read-only memory (EEPROM) and flash memory using charge storage structures Memory (flash memory) has been used in a variety of modern applications. The flash memory is designed to have an array of memory cells that can be programmed and read independently. A typical flash memory cell stores charge in a floating gate. Another non-volatile memory similar to a general flash memory uses tantalum nitride to create a charge-trapping structure to replace the conductive material of the floating gate. When the charge of tantalum nitride When the capture memory cell is programmed, the charge is captured and does not move through the charge trapping structure of the tantalum nitride. When the power supply is not continuously supplied, the charge remains in the tantalum nitride charge trap layer, maintaining its data state until the memory cell is erased. Since the charge does not move through the tantalum nitride charge trapping layer, the charge can be located at a different charge trap. In other words, in the flash memory structure of the charge trapping structure type, information of more than one bit can be stored in each memory cell.

At present, there are various methods proposed to fabricate the above two kinds of non-volatile memory, but since the apex angle of the trench in which the isolation structure is formed is easily exposed in the process or damaged by etching, the tunneling layer formed on the apex angle of the trench is formed. The thickness of the electrical layer is thin, causing problems in memory reliability. Furthermore, if the height of the isolation structure is to be reduced by etch back to increase the gate coupling ratio (GCR), it is necessary to prevent the tunneling dielectric layer above the apex angle of the trench from being etched and become thinner. Therefore, The etchback process must also be precisely controlled, and its process margin is very small.

The present invention provides a non-volatile memory cell having a high gate coupling ratio and reliability.

The invention proposes a method for manufacturing a non-volatile memory cell, the process of which has sufficient process margin.

The present invention provides a non-volatile memory cell comprising a substrate, a charge storage structure, and a tunneling dielectric layer. The substrate has an isolation structure defining an active region. The charge storage structure is located on the active area. The bottom width of the charge storage structure is substantially equal to The width of the active region, the first angle of the sidewall of the charge storage structure and the upper surface of the substrate is different from the second angle of the sidewall of the isolation structure to the upper surface of the substrate. The tunneling dielectric layer is between the charge storage structure and the substrate. The lower surface of the tunneling dielectric layer is flat and the upper surface of the tunneling dielectric layer is substantially parallel to the upper surface of the substrate.

According to an embodiment of the invention, the material of the charge storage structure is a dielectric charge trapping layer or a conductor layer.

According to an embodiment of the invention, the first angle is smaller than the second angle.

According to an embodiment of the invention, the intermediate width of the charge storage structure is substantially the same as the bottom width, or the difference is less than 10 nm.

According to an embodiment of the invention, the intermediate width of the charge storage structure is substantially the same as the top width, or the difference is less than 10 nm.

The present invention provides a method of fabricating a non-volatile memory cell comprising forming a plurality of patterned mask layers on a substrate. A plurality of spacers are formed in the sidewalls of the patterned mask layer. A patterned mask layer and a spacer are used as a mask to remove a portion of the substrate to form a plurality of trenches, wherein an active region is defined between any two adjacent trenches. A plurality of isolation structures are formed, the isolation structures being located in the trench and extending upwardly between the spacers. The patterned mask layer and the spacers are removed to form a plurality of openings between the isolation structures and on the active regions. A tunneling dielectric layer and a charge storage structure are formed in each opening. Wherein the lower surface of the tunneling dielectric layer is flat and substantially parallel to the upper surface of the substrate, the bottom width of the charge storage structure is substantially equal to the width of the corresponding active region, and the sidewall of the charge storage structure and the first surface of the substrate are first Different angle a second angle between the sidewall of the isolation structure and the upper surface of the substrate.

According to an embodiment of the invention, the method for manufacturing the non-volatile memory cell further includes forming a plurality of lining layers between the spacer and the patterned mask layer. The liner is removed prior to forming the tunnel dielectric layer and the charge storage structure in each opening.

According to an embodiment of the invention, the lining layer is different from the material of the spacer and different from the material of the patterned mask layer.

According to an embodiment of the invention, the step of forming the isolation structure includes forming an insulating layer on the substrate and filling the trench, and then performing a planarization process to remove the insulating layer on the mask layer.

According to an embodiment of the invention, the method for fabricating the non-volatile memory cell further includes etching back the insulating layer on the trench.

According to an embodiment of the invention, the method for fabricating the non-volatile memory cell further includes etching back a portion of the isolation structures.

Based on the above, in the method of manufacturing a non-volatile memory cell according to an embodiment of the present invention, the step of removing the insulating layer before the tunneling dielectric layer is formed has a large process window. In addition, by the etch back of the isolation structure, the coupling area between the control gate and the charge storage structure can be increased, and the gate coupling ratio can be increased.

Furthermore, the charge storage structure can have vertical sidewalls to avoid problems with the conductor stringer and to avoid void formation under charge storage.

Non-volatile memory cells of embodiments of the invention having high gate coupling Ratio and reliability.

The method for manufacturing a non-volatile memory cell according to an embodiment of the present invention has a process margin with sufficient process margin.

The above described features and advantages of the invention will be apparent from the following description.

10‧‧‧Base

12‧‧‧ patterned mask layer

14‧‧‧ first floor

16‧‧‧ second floor

18, 18a, 18b‧‧‧ lining

20‧‧‧ spacer material layer

20a‧‧‧ spacer

22‧‧‧ Ditch

24‧‧‧active area

26‧‧‧Insulation

26a, 26b‧‧‧Isolation structure

28, 29‧‧‧ openings

30‧‧‧Tunnel dielectric layer

32‧‧‧Charge storage structure

34‧‧‧ dielectric layer

36‧‧‧Control gate

1A through 1I are flow cross-sectional views showing a method of fabricating a non-volatile memory cell according to an exemplary embodiment of the invention.

A patterned mask layer 12 is formed on the substrate 10 in accordance with FIG. 1A. Substrate 10 can be a semiconductor substrate such as tantalum or tantalum. The substrate 10 may also be a ruthenium (SOI) substrate on the insulating layer. The aforementioned patterned mask layer 12 may be a single layer material layer, a two layer material layer or a multilayer material layer. In an exemplary embodiment, each of the patterned mask layers 12 is formed of a two-layer layer of a first layer 14 and a second layer 16. The first layer is, for example, a pad oxide layer, and the second layer is, for example, a tantalum nitride layer. The forming method may sequentially form the first material layer and the second material layer, and then pattern the second material layer and the first material layer via a lithography and etching process.

Next, referring to FIG. 1A, a liner 18 is formed on the substrate 10 to cover the patterned mask layer 12 and the substrate 10. Thereafter, a spacer material layer 20 is formed on the liner 18. The material of the liner 18 is different from the material of the patterned mask layer 12. In an exemplary embodiment, the material of the liner 18 is different than the material of the second layer 16 of the patterned mask layer 12. The material of the lining 18 is, for example, cerium oxide, borophosphon glass or polycrystalline germanium. The formation method of the underlayer 18 is, for example, a chemical vapor deposition method or an atomic layer deposition method, and the thickness is, for example, 1 nm to 20 nm. The material of the spacer material layer 20 is different from the liner 18 and is different from the subsequently formed insulating layer 26 (Fig. 1C). The material of the spacer material layer 20 is, for example, tantalum nitride, oxynitride or polysilicon. The method of forming the spacer material layer 20 is, for example, a chemical vapor deposition method or an atomic layer deposition method, and the thickness is, for example, 1 nm to 20 nm.

Referring to FIG. 1B, the spacer material layer 20 and the liner 18 are anisotropically etched to form a spacer 20a and a liner 18a on the sidewalls of the patterned mask layer 12. Next, a portion of the substrate 10 is removed with the patterned mask layer 12, the liner layer 18a and the spacers 20a as masks to form the trenches 22, wherein the active regions 24 are defined between any two adjacent trenches 22. Thereafter, an insulating layer 26 is formed on the substrate 10 and in the trench 20. The material of the insulating layer 26 may be an insulating material such as cerium oxide or borophosphon glass, which is formed by, for example, chemical vapor deposition.

Referring to FIG. 1C, a planarization process is performed to remove the insulating layer 26 on the patterned mask layer 12. The planarization process can be performed using a patterned mask layer 12 as a polishing stop layer using a chemical mechanical polishing process.

Referring to FIGS. 1D through 1F, the patterned mask layer 12, the liner 18a, and the spacers 20a are removed. More specifically, in an exemplary embodiment, referring to FIG. 1D, the second layer 16 of the patterned mask layer 12 is removed first. Next, referring to FIG. 1E, a portion of the liner 18a and the first layer 14 of the patterned mask layer 12 are removed, leaving a residual liner. Layer 18b. Thereafter, referring to FIG. 1F, the spacers 20a and the remaining liner 18a are removed, and openings 28 are formed between the isolation structures (the remaining insulating layers) 26a and the active regions 24.

Referring to FIGS. 1C and 1D, when the second layer 16 of the patterned mask layer 12 is removed, the material of the first layer 14 of the liner layer 18a and the patterned mask layer 12 is different from the patterned mask. The material of the second layer 16 of layer 12, therefore, the first layer 14 of liner 18a and patterned mask layer 12 can protect insulating layer 26 from damage by etching. Similarly, referring to FIGS. 1D and 1E, when the first layer 14 of the lining layer 18a and the patterned mask layer 12 is removed, the material of the spacer 20a is different from the lining layer 18a and the patterned mask layer 12 The first layer 14, therefore, the spacers 20a can protect the insulating layer 26 from the etch damage of the insulating layer 26, while the upper surface of the insulating layer 26 is partially removed without any protection, leaving the insulation Layer 26 acts as isolation structure 26a. 1E and 1F, in the process of removing the spacer 20a, since the material of the spacer 20a is different from that of the insulating layer 26, an etchant having a high etching selectivity ratio to the spacer 20a/insulation 26 can be selected. An etching process is performed to reduce the damage of the sidewall of the isolation structure 26a. Therefore, after the spacers 20a are removed, the upper surface of the substrate 10 is substantially flat, and the sidewalls of the isolation structure 26a are substantially free of depressions. Further, in the process of removing the spacers 20a, the residual lining 18a can also protect the substrate 10 at the apex angle of the trench 22 and the isolation structure 26a from dent formation. The residual liner 18a may be removed after the spacer 20a is removed, or removed during removal of the spacer 20a.

Referring to FIG. 1G, a tunneling dielectric layer 30 is formed between the isolation structures (the remaining insulating layers) 26a and the openings 28 on the active regions 24. Tunneling the dielectric layer 30 The material is, for example, cerium oxide. The method of forming the tunnel dielectric layer 30 may be a thermal oxidation method or a chemical vapor deposition method. The thickness of the tunnel dielectric layer 30 is, for example, 1 nm to 10 nm. Since the upper surface of the substrate 10 is still substantially flat after the spacers 20a are removed, the lower surface of the tunneling dielectric layer 30 is also substantially flat, and the upper surface thereof is substantially opposite to the substrate 10. The upper surface is parallel.

Next, a charge storage structure 32 is formed on the tunnel dielectric layer 30. The material of the charge storage structure 32 may be a dielectric charge trapping layer or a conductor layer. The dielectric charge trapping layer may be a single layer structure or a multilayer structure. The material of the dielectric charge trap layer includes tantalum nitride. In one embodiment, the material of the dielectric charge trapping layer comprises a stack structure of yttrium oxide, lanthanum nitride, and lanthanum oxide from bottom to top, and the forming method is, for example, chemical vapor deposition or thermal oxidation or thermal nitridation. The thickness is, for example, 1 nm to 5 nm, 1 nm to 5 nm, and 1 nm to 5 nm, respectively. The material of the conductor layer is, for example, doped polysilicon, and the formation method is, for example, chemical vapor deposition, and the thickness is, for example, 1 nm to 100 nm. Since the sidewalls of the isolation structure 26a are substantially free of recesses, the charge storage structure 32 formed in the opening 28 between the isolation structures 26a has, for example, a vertical sidewall having a width W2 substantially the same as the top width W1 thereof. Or a difference of less than 1 nm; and the intermediate width W2 of the charge storage structure 32 is substantially the same as its bottom width W3, or a difference of less than 10 nm. Moreover, the bottom width W3 of the charge storage structure 32 is substantially equal to the width W4 of the corresponding active region 24. Since the charge storage structure 32 has vertical sidewalls, the problem of the conductor stringer can be avoided, and the formation of voids under the charge storage can also be avoided.

After that, please refer to Figure 1H, which can be based on the actual gate coupling ratio (Gate The need for a coupling ratio, GCR, selectively removes a portion of the upper surface of the isolation structure 26a to form an opening 29. The surface height of the remaining isolation structure 26b is reduced to increase the coupling area between the subsequently formed control gate 36 and the charge storage structure 32 to enhance the GCR. The method of selectively removing the isolation structure 26a may employ an etch back method. The etch back method may be a wet etching method, for example, using a hydrofluoric acid solution as an etchant. Since the opening 29 on the isolation structure 26b is formed at different times from the trench 22 in the substrate 10, and the sidewalls thereof have different inclinations, the sidewall of the charge storage structure 32 in the opening 29 and the upper surface of the substrate 10 An angle a is different from the second angle β of the side wall of the isolation structure 26a in the trench 22 and the upper surface of the substrate 10. The difference between the first angle α and the second angle β is, for example, 0 to 10 degrees.

Thereafter, referring to FIG. 1I, a dielectric layer 34 and a control gate 36 are formed on the substrate 10 and the opening 29. The material of the dielectric layer 34 is, for example, ruthenium oxide, and the formation method is, for example, a chemical vapor deposition method or a thermal oxidation method, and the thickness is, for example, 1 nm to 20 nm. The control gate 36 is a conductor layer which may be a single layer material or a two layer material. In an exemplary embodiment, the control gate 36 is a single layer of material, such as doped polysilicon, formed by, for example, chemical vapor deposition, having a thickness of, for example, 10 nm to 200 nm. Since the charge reservoir structure 32 has smooth sidewalls (eg, vertical sidewalls), the dielectric layer 34 can be co-planned over the surface of the charge reservoir structure 32, and the control gate 36 can be in contact with the dielectric layer 34 and The opening 29 is filled and there is no possibility that the dielectric layer 34 cannot be contacted or the opening 29 cannot be filled to form a void.

In summary, according to the method for fabricating a non-volatile memory cell according to an embodiment of the present invention, the step of removing the insulating layer before the tunneling dielectric layer is formed has a large process. The process window. In addition, by the etch back of the isolation structure, the coupling area between the control gate and the charge storage structure can be increased, and the gate coupling ratio can be increased. Furthermore, the bottom width of the charge storage structure of the non-volatile memory cell according to the embodiment of the present invention is substantially equal to the width of the active region, and the first angle between the sidewall of the charge storage structure and the upper surface of the substrate is different from the sidewall of the isolation structure. a second angle of the upper surface of the substrate. The charge storage structure can have vertical sidewalls to avoid problems with conductor stringers and to avoid formation of voids under charge storage. The lower surface of the tunneling dielectric layer of the non-volatile memory cell is flat, and the upper surface of the tunneling dielectric layer is substantially parallel to the upper surface of the substrate, that is, the thickness of the tunneling dielectric layer is uniform, so the non-volatile memory The cell has high reliability.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

10‧‧‧Base

12‧‧‧ patterned mask layer

14‧‧‧ first floor

16‧‧‧ second floor

18a‧‧‧ lining

20a‧‧‧ spacer

22‧‧‧ Ditch

24‧‧‧active area

26‧‧‧Insulation

26a‧‧‧Isolation structure

Claims (8)

A non-volatile memory cell includes: a substrate having an isolation structure defining an active region; and a charge storage structure disposed on the active region, wherein a bottom width of the charge storage structure is substantially equal to a width of the active region, The first angle of the sidewall of the charge storage structure and the upper surface of the substrate is different from the second angle of the sidewall of the isolation structure and the upper surface of the substrate, and the material of the charge storage structure is a dielectric charge trapping layer; a tunneling dielectric layer is disposed between the charge storage structure and the substrate, wherein a lower surface of the tunneling dielectric layer is flat, and an upper surface of the tunneling dielectric layer is substantially parallel to the upper surface of the substrate The width of the tunneling dielectric layer is substantially equal to the intermediate width of the charge storage structure. The non-volatile memory cell of claim 1, wherein the first angle is less than the second angle. The non-volatile memory cell of claim 1, wherein the intermediate width of the charge storage structure is substantially the same as the bottom width, or a difference of less than 10 nm. The non-volatile memory cell of claim 1, wherein the intermediate width of the charge storage structure is substantially the same as the top width, or a difference of less than 10 nm. A method for manufacturing a non-volatile memory cell, comprising: forming a plurality of patterned mask layers on a substrate; Forming a plurality of spacers on sidewalls of the patterned mask layers; forming a plurality of liners between the spacers and the patterned mask layers; and the patterned mask layers and the The spacers are masks, and a portion of the substrate is removed to form a plurality of trenches, wherein an active region is defined between any two adjacent trenches; a plurality of isolation structures are formed, and the isolation structures are located in the trenches and upward Extending between the spacers; removing the patterned mask layer and the spacers to form a plurality of openings between the isolation structures and the active regions; and forming in each opening Tunneling the dielectric layer and the charge storage structure, wherein the liner layer is removed before the tunneling dielectric layer and the charge storage structure are formed in each of the openings, and the lower surfaces of the tunnel dielectric layers are flat and Parallel to the upper surface of the substrate, the bottom width of the charge storage structures is substantially equal to the width of the corresponding active regions, and the first angle of the sidewalls of the charge storage structures is different from the upper surface of the substrate The isolation knot The side walls of the second angle with the substrate surface. The method for manufacturing a non-volatile memory cell according to claim 5, wherein the lining is different from the materials of the spacers and different from the materials of the patterned mask layers. The method for manufacturing a non-volatile memory cell according to claim 5, wherein the forming the isolation structure comprises: forming an insulating layer on the substrate, filling in the trench; and planarizing The process removes the insulating layer on the mask layer. The method for fabricating a non-volatile memory cell according to claim 7, further comprising etching back the insulating layer on the trench.