TWI478293B - Method of fabricating non-volatile memory device - Google Patents

Description

Method for manufacturing non-volatile memory element

The present invention relates to a method of fabricating an integrated circuit, and more particularly to a method of fabricating a non-volatile memory element.

Non-volatile memory components can store, read, and erase data multiple times, and the stored data will not disappear after power-off. Therefore, it has become a memory widely used in personal computers and electronic devices. element.

Typical non-volatile memory components include floating gates and control gates. The control gate is directly disposed on the floating gate, and the floating gate and the control gate are separated by a dielectric layer, and the floating gate and the substrate are separated by a tunneling oxide layer (also referred to as a stacked gate) Extremely fast flash memory).

The floating gates of the currently developed non-volatile memory components are located on both sides of the control gate. The control gate is formed by embedding the trench. The gate dielectric layer under the control gate is formed after the trench is formed and before the control gate is formed. Therefore, as the aspect ratio of the trench gradually increases, The more difficult the deposition process is, the higher the unevenness of the formed gate dielectric layer, especially the thickness at the edge is much smaller than the thickness of the center, resulting in a leakage path at the edge, which causes problems in component reliability.

The invention provides a method for manufacturing a non-volatile memory element, which can increase the uniformity of the gate boundary electrical layer under the control gate, reduce leakage and improve the reliability of the component.

The present invention provides a method of fabricating a non-volatile memory element comprising forming a stacked structure having trenches on a substrate. The stack structure includes a first dielectric layer, a first conductor layer and a first cap layer sequentially stacked on the substrate, and a second dielectric layer on the trench sidewall. Next, a gate dielectric layer is formed on the substrate at the bottom of the trench in at least two different film formation methods. Thereafter, a second conductor layer and a second cap layer are embedded in the trench. Then, the first cap layer is removed, and then a portion of the first conductive layer is removed.

According to an embodiment of the invention, the at least two different film forming methods result in a center-to-edge unevenness of the gate dielectric layer of less than 25%. Here the definition of unevenness is:

Unevenness % = (maximum film thickness - minimum film thickness) / (average film thickness) x 100%

According to an embodiment of the invention, the step of forming the gate dielectric layer comprises: forming a liner on the substrate at the bottom of the trench, and forming a third dielectric layer on the liner.

According to an embodiment of the invention, the method for forming a liner is such that the unevenness of the liner is lower than the unevenness of the third dielectric layer.

In accordance with an embodiment of the invention, the method of forming a liner includes a process method that results in a non-uniformity of the liner of less than 10%.

According to an embodiment of the invention, the method for forming a liner includes a thermal oxidation process or an atomic layer deposition process.

According to an embodiment of the invention, the thermal oxidation process comprises a rapid thermal oxidation process or an on-site water vapor generation (ISSG) process.

According to an embodiment of the invention, the film forming rate of the method for forming the underlayer is lower than the film forming rate for forming the third dielectric layer.

In accordance with an embodiment of the invention, the method for forming the liner is such that the density of the liner is higher than the density of the third dielectric layer.

According to an embodiment of the invention, the thickness of the underlayer is less than the thickness of the third dielectric layer.

The method for manufacturing a non-volatile memory element of the present invention can increase the uniformity of the gate boundary electrical layer under the control gate, reduce leakage, and improve the reliability of the component.

The above described features and advantages of the present invention will be more apparent from the following description.

1 to 7 are schematic cross-sectional views showing a method of fabricating a non-volatile memory device according to an embodiment of the invention.

Referring to FIG. 1, a dielectric layer 12, a first conductor layer 14, and a first cap layer 16 are formed on the substrate 10. The material of the substrate 10 is, for example, a semiconductor such as germanium or a germanium (SOI) on the insulating layer. The material of the substrate 10 may also be other compound semiconductors. The dielectric layer 12 is used to fabricate a tunneling dielectric layer, such as tantalum oxide, or other dielectric material suitable for use in fabricating a tunneling dielectric layer. The method of forming the dielectric layer 12 is, for example, a thermal oxidation method, or a chemical vapor deposition method, or other suitable method. The thickness of the dielectric layer 12 is, for example, about 50 to 100 angstroms. The first conductor layer 14 is used to fabricate a floating gate, the material of which is, for example, a doped polysilicon. The method of forming the first conductor layer 14 is, for example, forming an undoped polysilicon layer by chemical vapor deposition, and then performing an ion implantation step to form it. The first conductor layer 14 may be formed by a chemical vapor deposition method to form a doped polysilicon layer and doping in the field. The thickness of the first conductor layer 14 is, for example, about 800 to 2000 angstroms. The material of the first cap layer 16 is, for example, tantalum nitride or hafnium oxynitride, and the method of forming it is, for example, chemical vapor deposition. The thickness of the first cap layer 16 is, for example, about 1000 to 3000 angstroms.

Referring to FIG. 2, the first cap layer 16 and the first conductor layer 14 are patterned to form a trench 18. The patterning method can utilize lithography and etching processes. Thereafter, a dielectric layer 20 is formed on the substrate 10 to cover the bottom of the trench 18, the sidewalls, and the first cap layer 16. The dielectric layer 20 may be a stacked layer composed of a single layer of material or a plurality of layers of material. In an embodiment, the material of the dielectric layer 20 may be a tantalum oxide or tantalum oxide/yttria (ON) stacked layer, and the forming step is, for example, first forming a layer of tantalum oxide by thermal oxidation, and then utilizing the chemical vapor phase. The deposition method forms a tantalum nitride layer on the ruthenium oxide layer. The thickness of the yttria/tantalum nitride stacked layer is, for example, about 20 to 80 angstroms / 20 to 120 angstroms, respectively. The material of the dielectric layer 20 can also be any other known dielectric material.

Then, referring to FIG. 3, the dielectric layer 20 at the bottom of the trench 18 and the dielectric layer 12 under it are removed, and the surface of the substrate 10 at the bottom of the trench 18 is exposed, leaving the dielectric layer 20 on the sidewall of the trench 18. The method of removing the dielectric layer 20 at the bottom of the trench 18 includes an anisotropic etch, such as a dry etch. During the anisotropic etch to remove the dielectric layer 20 at the bottom of the trench 18, the dielectric layer 20 on the first cap layer 16 is also removed. So far, a stacked structure 40 having a trench 18 is formed on the substrate 10. The stacked structure 40 includes a first dielectric layer 12, a first conductive layer 14 and a first cap layer 16 are sequentially stacked on the substrate 10, and includes The second dielectric layer 20 is located on the sidewall of the trench 18.

Next, referring to FIG. 4, a dielectric layer (22, 24) is formed on the substrate 10 of the trench bottom 18 and the sidewalls of the trench 18 in at least two different film forming methods. First, a liner 22 is formed prior to the bottom of the trench 18. Thereafter, a dielectric layer 24 is formed over the substrate 10 to cover the first cap layer 16, the dielectric layer 20, and the liner 22. The material of the lining layer 22 and the dielectric layer 24 may be the same or different. In an embodiment, the liner 22 and the dielectric layer 24 are both hafnium oxide. The method of forming the liner 22 is different from the method of forming the dielectric layer 24. In more detail, the unevenness of the center and edge of the liner 22 is lower than the unevenness of the center and edge of the dielectric layer 24. The definition of unevenness is as follows:

Unevenness % = (maximum film thickness - minimum film thickness) / (average film thickness) x 100%

In one embodiment, the process method (growth or deposition) used by the liner 22 can be such that the unevenness is controlled to less than 10%. Generally, the uniformity of the film is related to the rate of film formation, and the higher the rate of film formation, the lower the uniformity of the film. In one embodiment, the film formation rate employed by the liner 22 is lower than the film formation rate of the dielectric layer. From another perspective, the density of the liner 22 is higher than the density of the dielectric layer 24. The process methods used for the liner 22 include a thermal oxidation process or an atomic layer deposition process or other suitable method for growing the liner. The thermal oxidation process includes a rapid thermal oxidation process (RTO) or an in-situ steam generation (ISSG) process. The method of forming the dielectric layer 24 is, for example, a chemical vapor deposition method. In one embodiment, the thickness of the liner 22 is less than the thickness of the dielectric layer 24. The thickness of the liner 22 is, for example, 1 to 200 angstroms; and the thickness of the dielectric layer 24 is, for example, 100 to 400 angstroms. The sum of the thicknesses of the liner 22 and the dielectric layer 24 is, for example, 100 to 600 angstroms. The dielectric layer 24 and the dielectric layer 20 on the sidewalls of the trench 18 serve as a gate dielectric layer between the floating gate and the control gate. The dielectric layer 24 and the lining layer 22 at the bottom of the trench 18 are used as a gate dielectric layer between the subsequently formed control gate and the substrate 10, and the center-to-edge unevenness is less than 25%.

Next, a second conductor layer 26 is formed on the substrate, and the second conductor layer 26 covers the dielectric layer 24 and is filled in the trench 18. The material of the second conductor layer 26 is, for example, a doped polysilicon. The second conductor layer 26 is formed by, for example, forming an undoped polysilicon layer by chemical vapor deposition, and performing an ion implantation step to form it. The second conductor layer 26 may be formed by a chemical vapor deposition method to form a doped polysilicon layer and doping in the field. The thickness of the second conductor layer 26 is, for example, about 2,000 to 5,000 angstroms.

Thereafter, referring to FIG. 5, the second conductor layer 26 and the dielectric layer 24 above the first cap layer 16 in FIG. 4 are removed, and a portion of the second conductor layer 26 of the trench 18 is removed to be embedded in the trench. The height of the second conductor layer 26 remaining in the 18 is lower than the height of the first cap layer 16, and the height difference is, for example, about 100 to 1000 angstroms. In one embodiment, the method of removing a portion of the second conductor layer 26 may be, for example, first using a chemical mechanical polishing method with the first cap layer 16 as a polishing stop layer and the second conductor on the first cap layer 16. Layer 26 and dielectric layer 24 are removed. Thereafter, a portion of the second conductor layer 26 in the trench 18 is removed using an etch back process. In another embodiment, the method of removing a portion of the second conductor layer 26 may be, for example, removing the second conductor layer 26 on the first cap layer 16 using an etch back process and continuing to remove the trenches 18 A portion of the second conductor layer 26. Thereafter, the dielectric layer 24 on the first cap layer 16 is removed. The second conductor layer 26, which is embedded in the trench 18, serves as a control gate.

Next, a second cap layer 28 is formed on the second conductor layer 26 in the trench 18. The material of the second cap layer 28 is different from the material of the first cap layer 16, and the material thereof is, for example, cerium oxide, and the thickness is, for example, about 500 to 2000 angstroms. The method for forming the second cap layer 28 is, for example, first depositing a second capping material layer (not shown) by chemical vapor deposition, and then removing the terminating layer by using the first capping layer 16 as a removal terminating layer. A second layer of top cover material on a cap layer 16. A method of removing the second cap material layer on the first cap layer 16 is, for example, a chemical mechanical lapping method.

Thereafter, referring to FIG. 6, the first cap layer 16 is removed to expose the first conductor layer 14. The method of removing the first cap layer 16 may employ an etching process such as a wet etching process. Thereafter, a spacer material layer 30 is formed on the substrate 10 to cover the first conductor layer 14, the dielectric layer 20, the dielectric layer 24, and the second cap layer 28. The material of the spacer material layer 30 is different from the material of the second cap layer 28, and the material thereof is, for example, tantalum nitride. The method of forming is, for example, chemical vapor deposition, and the thickness is, for example, about 100 to 600 angstroms.

then. Referring to FIG. 7, the spacer material layer 30 is anisotropically etched to form a spacer 30a on the sidewall of the dielectric layer 20, and the spacer 30a covers a portion of the first conductive layer 14. The method of anisotropic etching is, for example, a dry etching method. Thereafter, with the spacers 30a and the second cap layer 28 as masks, a portion of the first conductor layer 14 is removed, and the dielectric layer 12 is exposed. The method of removing a portion of the first conductor layer 14 may employ an anisotropic etching method such as a dry etching method. The remaining first conductive layer 14 is located on both sides of the second conductor layer 26 as a control gate. The dielectric layer 24 is combined with the dielectric layer 20 as an inter-gate dielectric layer between the first conductive layer 14 (floating gate) and the second conductor layer 26 (control gate). The dielectric layer 24 is combined with the liner 22 as a gate dielectric between the control gate and the substrate 10.

In the above embodiment of the present invention, the gate dielectric layer between the control gate and the substrate is formed in two steps, and a liner having a higher uniformity is formed first, and then a deposition method having a higher film formation rate is used. To form a dielectric layer. However, the present invention is not limited thereto, and the gate dielectric layer between the control gate and the substrate can be formed in more steps, and is not limited to two steps. Actually, in application, it can be adjusted as needed, as long as It is the film uniformity of the first film forming step that is higher than the subsequent steps, and the subsequent film forming rate is higher than the first film forming step.

In summary, the gate dielectric layer between the control gate and the substrate of the present invention can be formed into two or more steps, and a relatively uniform liner is formed at the bottom of the trench to slow the center and the edge. The difference in height can further alleviate the problem of uneven thickness of the dielectric layer formed by the subsequent deposition process if the aspect ratio is too high, and then use a deposition method with a higher deposition rate to form the dielectric layer. The total thickness required for the gate dielectric layer can be provided, and on the other hand, the throughput of the process can be increased to avoid a lower film formation rate of the liner and affect the output. Therefore, the method of the present invention can make the gate dielectric layer between the control gate and the substrate relatively uniform, and avoid the problem of leakage current and reliability of the derivative caused by the thickness difference.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

10. . . Base

12, 20, 24. . . Dielectric layer

14, 26. . . Conductor layer

16, 28. . . Roof layer

18. . . ditch

twenty two. . . lining

30. . . Gap material layer

30a. . . Clearance wall

40. . . Stack structure

1 to 7 are schematic cross-sectional views showing a method of fabricating a non-volatile memory device according to an embodiment of the invention.

10. . . Base

12, 20, 24. . . Dielectric layer

14, 26. . . Conductor layer

16. . . Roof layer

18. . . ditch

twenty two. . . lining

40. . . Stack structure

Claims (10)

A method of fabricating a non-volatile memory device, comprising: forming a stacked structure having a trench on a substrate, the stacked structure comprising a first dielectric layer, a first conductive layer and a first top cover layer sequentially Stacked on the substrate, and including a second dielectric layer on the sidewall of the trench; forming a gate dielectric layer on the substrate at the bottom of the trench in at least two different film forming methods; embedding in the trench a second conductor layer and a second cap layer; removing the first cap layer; and removing a portion of the first conductive layer. The method of fabricating the non-volatile memory device of claim 1, wherein the at least two different film forming methods result in a non-uniform uniformity of the center and the edge of the gate dielectric layer of less than 25%. The method of manufacturing the non-volatile memory device of claim 1, wherein the step of forming the gate dielectric layer comprises: forming a liner on the substrate at the bottom of the trench; and forming on the liner A third dielectric layer. The method of manufacturing a non-volatile memory element according to claim 3, wherein the method for forming the underlayer is such that the unevenness of the underlayer is lower than the unevenness of the third dielectric layer. The method of manufacturing a non-volatile memory element according to claim 3, wherein the method of forming the liner comprises a process method which can make the unevenness of the underlayer be 10% or less. The method of manufacturing a non-volatile memory element according to claim 5, wherein the process for forming the liner comprises a thermal oxidation process or an atomic layer deposition process. The method of manufacturing a non-volatile memory element according to claim 6, wherein the thermal oxidation process comprises a rapid thermal oxidation process or a on-site water vapor generation process. The method of producing a non-volatile memory element according to claim 3, wherein a film forming rate of the method for forming the underlayer is lower than a film forming rate for forming the third dielectric layer. The method of manufacturing a non-volatile memory element according to claim 3, wherein the method for forming the liner is such that the density of the liner is higher than the density of the third dielectric layer. The method of manufacturing a non-volatile memory element according to claim 3, wherein the thickness of the underlayer is less than the thickness of the third dielectric layer.