TWI548039B - Method for fabricating semiconductor device - Google Patents
Method for fabricating semiconductor device Download PDFInfo
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- TWI548039B TWI548039B TW104108499A TW104108499A TWI548039B TW I548039 B TWI548039 B TW I548039B TW 104108499 A TW104108499 A TW 104108499A TW 104108499 A TW104108499 A TW 104108499A TW I548039 B TWI548039 B TW I548039B
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- sidewall
- gate structure
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- 239000004065 semiconductor Substances 0.000 title claims description 40
- 238000000034 method Methods 0.000 title claims description 30
- 239000010410 layer Substances 0.000 claims description 72
- 125000006850 spacer group Chemical group 0.000 claims description 28
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 claims description 24
- 239000000758 substrate Substances 0.000 claims description 17
- 239000011241 protective layer Substances 0.000 claims description 15
- 238000004519 manufacturing process Methods 0.000 claims description 14
- 238000005468 ion implantation Methods 0.000 claims description 8
- 229910001925 ruthenium oxide Inorganic materials 0.000 claims description 8
- WOCIAKWEIIZHES-UHFFFAOYSA-N ruthenium(iv) oxide Chemical compound O=[Ru]=O WOCIAKWEIIZHES-UHFFFAOYSA-N 0.000 claims description 8
- 229920002120 photoresistant polymer Polymers 0.000 claims description 6
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 claims description 4
- 229910000147 aluminium phosphate Inorganic materials 0.000 claims description 2
- 238000000151 deposition Methods 0.000 claims description 2
- 238000001039 wet etching Methods 0.000 claims description 2
- YBMRDBCBODYGJE-UHFFFAOYSA-N germanium oxide Inorganic materials O=[Ge]=O YBMRDBCBODYGJE-UHFFFAOYSA-N 0.000 claims 1
- PVADDRMAFCOOPC-UHFFFAOYSA-N oxogermanium Chemical compound [Ge]=O PVADDRMAFCOOPC-UHFFFAOYSA-N 0.000 claims 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 14
- 229920005591 polysilicon Polymers 0.000 description 14
- 150000004767 nitrides Chemical class 0.000 description 12
- 230000002093 peripheral effect Effects 0.000 description 10
- 229910000449 hafnium oxide Inorganic materials 0.000 description 9
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 9
- SIWVEOZUMHYXCS-UHFFFAOYSA-N oxo(oxoyttriooxy)yttrium Chemical compound O=[Y]O[Y]=O SIWVEOZUMHYXCS-UHFFFAOYSA-N 0.000 description 9
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 5
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 4
- WJMXTYZCTXTFJM-UHFFFAOYSA-N 1,1,1,2-tetraethoxydecane Chemical compound C(C)OC(C(OCC)(OCC)OCC)CCCCCCCC WJMXTYZCTXTFJM-UHFFFAOYSA-N 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 230000005641 tunneling Effects 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910001936 tantalum oxide Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000007865 diluting Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 238000010405 reoxidation reaction Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- RUDFQVOCFDJEEF-UHFFFAOYSA-N yttrium(III) oxide Inorganic materials [O-2].[O-2].[O-2].[Y+3].[Y+3] RUDFQVOCFDJEEF-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
- H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28247—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon passivation or protection of the electrode, e.g. using re-oxidation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Description
本發明係有關於半導體製程技術領域，特別是有關於具有雙側壁子(dual spacer)結構的半導體裝置的製作方法。 The present invention relates to the field of semiconductor process technology, and more particularly to a method of fabricating a semiconductor device having a dual spacer structure.
隨著半導體製程技術不斷進步，半導體元件越做越小，元件與元件之間的距離也越來越接近。以含有記憶體元件、高壓元件與低壓元件的系統單晶片(System-On-a-Chip，SOC)為例，其中在記憶體區域及低電壓區域內的元件間的間距很小，故需要較小的側壁子寬度。 As semiconductor process technology continues to advance, semiconductor components are getting smaller and smaller, and the distance between components and components is getting closer. Taking a system-on-a-chip (SOC) including a memory element, a high voltage element, and a low voltage element as an example, in which the spacing between components in the memory region and the low voltage region is small, it is necessary to compare Small side wall width.
相反的，在高電壓區域內的高壓元件，由於需要較高的崩潰電壓等電性，故其結構上需要較大的側壁子寬度，以形成分級的(graded)接面。 Conversely, high voltage components in the high voltage region require a relatively large sidewall sub-width to form a graded junction due to the need for higher breakdown voltage isoelectricity.
因此，該技術領域仍需要一種改良的半導體裝置的製作方法，能夠在盡量不增加光罩的情況下(最多增加一道光罩)，提供高壓元件較大的側壁子寬度，而對記憶體區域及低電壓區域內的元件提供較小的側壁子寬度，並且能夠相容於現行的邏輯製程，例如，金屬矽化阻擋(silicide block，SAB)製程等。 Therefore, there is still a need in the art for an improved method of fabricating a semiconductor device that can provide a large sidewall width of a high voltage component without adding a photomask as much as possible, while the memory region and The components in the low voltage region provide a smaller sidewall sub-width and are compatible with current logic processes, such as metal silicide block (SAB) processes and the like.
本發明的主要目的在提供一種半導體裝置的製作方法，僅增加一道光罩，能夠提供高壓元件較大的側壁子寬度，對記憶體區域及低電壓區域內的元件提供較小的側壁子寬度，並且能夠相容於現行的邏輯製程。 SUMMARY OF THE INVENTION A primary object of the present invention is to provide a method of fabricating a semiconductor device that adds only a mask to provide a larger sidewall width of the high voltage component and a smaller sidewall width for components in the memory region and the low voltage region. And can be compatible with the current logic process.
本發明實施例提供一種半導體裝置的製作方法，包含有：提供一半導體基材，具有一第一區域及一第二區域，其中該第一區域與該第二區域 互不重疊；分別在該第一區域及該第二區域的該半導體基材上形成一第一閘極結構及一第二閘極結構；分別於該第一閘極結構及該第二閘極結構側壁上形成一第一偏間隙壁及一第二偏間隙壁；進行一離子佈植製程，於該半導體基材表面形成一輕摻雜汲極區域；分別於該第一閘極結構及該第二閘極結構側壁上形成一第一襯墊層及一第二襯墊層；分別於該第一閘極結構及該第二閘極結構側壁上的該第一襯墊層及該第二襯墊層上形成一第一側壁子及一第二側壁子；於該半導體基材上沉積一第三襯墊層，覆蓋該第一區域及該第二區域，該第三襯墊層共形的形成在第一側壁子及該第二側壁子表面；分別於該第一閘極結構及該第二閘極結構側壁上的該第三襯墊層上形成一第三側壁子及一第四側壁子；形成一犧牲保護層，僅覆蓋住該第二區域內的該第二閘極結構以及該第四側壁子；選擇性的剝除該第一區域內的該第三側壁子；以及去除該犧牲保護層以及部分該第三襯墊層，顯露出該第一區域內的該第一側壁子以及該第二區域內的該第四側壁子。 Embodiments of the present invention provide a method of fabricating a semiconductor device, including: providing a semiconductor substrate having a first region and a second region, wherein the first region and the second region Forming a first gate structure and a second gate structure on the semiconductor substrate of the first region and the second region; respectively, the first gate structure and the second gate Forming a first offset spacer and a second offset spacer on the sidewall of the structure; performing an ion implantation process to form a lightly doped drain region on the surface of the semiconductor substrate; respectively, the first gate structure and the Forming a first liner layer and a second liner layer on the sidewall of the second gate structure; the first liner layer and the second layer respectively on the sidewalls of the first gate structure and the second gate structure Forming a first sidewall and a second sidewall on the liner layer; depositing a third liner layer on the semiconductor substrate to cover the first region and the second region, the third liner layer conformal Forming on the first sidewall and the second sidewall sub-surface; forming a third sidewall and a fourth on the third spacer layer on the sidewalls of the first gate structure and the second gate structure respectively a sidewall spacer; forming a sacrificial protective layer covering only the second gate structure in the second region And the fourth sidewall; selectively stripping the third sidewall in the first region; and removing the sacrificial protective layer and a portion of the third liner to expose the first portion in the first region a sidewall and the fourth sidewall in the second region.
為讓本發明之上述目的、特徵及優點能更明顯易懂，下文特舉較佳實施方式，並配合所附圖式，作詳細說明如下。然而如下之較佳實施方式與圖式僅供參考與說明用，並非用來對本發明加以限制者。 The above described objects, features and advantages of the present invention will become more apparent from the description of the appended claims. However, the following preferred embodiments and drawings are for illustrative purposes only and are not intended to limit the invention.
1‧‧‧半導體裝置 1‧‧‧Semiconductor device
10‧‧‧半導體基材 10‧‧‧Semiconductor substrate
11‧‧‧記憶體結構 11‧‧‧ memory structure
30‧‧‧離子佈植製程 30‧‧‧Ion implantation process
101‧‧‧記憶體區域 101‧‧‧ memory area
102‧‧‧週邊區域 102‧‧‧The surrounding area
102a‧‧‧低電壓區域 102a‧‧‧Low voltage area
102b‧‧‧高電壓區域 102b‧‧‧High voltage area
110‧‧‧記憶胞 110‧‧‧ memory cells
111‧‧‧浮置閘極穿隧氧化層 111‧‧‧Floating gate tunneling oxide
112‧‧‧浮置閘極 112‧‧‧Floating gate
113‧‧‧多晶矽間介電層 113‧‧‧Polysilicon interdielectric dielectric layer
114‧‧‧控制閘極 114‧‧‧Control gate
115‧‧‧氧化矽層 115‧‧‧Oxide layer
116‧‧‧氧化矽側壁子 116‧‧‧矽 矽 sidewall
118‧‧‧四乙氧基矽烷氧化矽層 118‧‧‧tetraethoxydecane ruthenium oxide layer
120‧‧‧閘極結構 120‧‧‧ gate structure
121‧‧‧閘極氧化層 121‧‧‧ gate oxide layer
122‧‧‧多晶矽閘極 122‧‧‧Polysilicon gate
125‧‧‧氧化矽層 125‧‧‧Oxide layer
126‧‧‧氮化矽偏間隙壁 126‧‧‧Nitride nitride spacer
130‧‧‧閘極結構 130‧‧‧ gate structure
131‧‧‧閘極氧化層 131‧‧‧ gate oxide layer
132‧‧‧多晶矽閘極 132‧‧‧Polysilicon gate
135‧‧‧氧化矽層 135‧‧‧Oxide layer
136‧‧‧氮化矽偏間隙壁 136‧‧‧Nitride nitride spacer
210‧‧‧選擇電晶體 210‧‧‧Selecting a crystal
211‧‧‧閘極氧化層 211‧‧‧ gate oxide layer
212‧‧‧多晶矽閘極 212‧‧‧Polysilicon gate
215‧‧‧氧化矽層 215‧‧‧Oxide layer
216‧‧‧氧化矽側壁子 216‧‧‧ yttrium oxide sidewall
316‧‧‧氮化矽偏間隙壁 316‧‧‧Nitride nitride spacer
320‧‧‧輕摻雜汲極區域 320‧‧‧Lightly doped bungee area
415‧‧‧氧化矽襯墊層 415‧‧‧Oxide lining
416‧‧‧氮化矽側壁子 416‧‧‧ nitride sidewalls
425‧‧‧氧化矽襯墊層 425‧‧‧Oxide lining
426‧‧‧氮化矽側壁子 426‧‧‧ nitride sidewalls
435‧‧‧氧化矽襯墊層 435‧‧‧Oxide lining
436‧‧‧氮化矽側壁子 436‧‧‧ nitride sidewalls
505‧‧‧氧化矽層 505‧‧‧Oxide layer
506‧‧‧氮化矽層 506‧‧‧layer of tantalum nitride
509‧‧‧犧牲保護層 509‧‧‧ Sacrificial protective layer
516‧‧‧氮化矽側壁子 516‧‧‧ nitride sidewalls
526‧‧‧氮化矽側壁子 526‧‧‧ nitride sidewalls
536‧‧‧氮化矽側壁子 536‧‧‧ nitride sidewalls
第1圖至第9圖為依據本發明實施例所繪示的半導體裝置的製作方法的剖面示意圖。 1 to 9 are schematic cross-sectional views showing a method of fabricating a semiconductor device according to an embodiment of the invention.
在下文中，將參照附圖說明細節，該些附圖中之內容亦構成說明書細節描述的一部份，並且以可實行該實施例之特例描述方式來繪示。下文實施例已描述足夠的細節俾使該領域之一般技藝人士得以具以實施。當然，亦可採行其他的實施例，或是在不悖離文中所述實施例的前提下作出任何結構性、邏輯性、及電性上的改變。因此，下文之細節描述不應被視為是限制， 反之，其中所包含的實施例將由隨附的申請專利範圍來加以界定。 In the following, the details will be described with reference to the drawings, which also form part of the detailed description of the specification, and are described in the manner of the specific examples in which the embodiment can be practiced. The following examples have been described in sufficient detail to enable those of ordinary skill in the art to practice. Of course, other embodiments may be utilized, or any structural, logical, or electrical changes may be made without departing from the embodiments described herein. Therefore, the following detailed description should not be considered as a limitation. Rather, the embodiments contained therein are defined by the scope of the appended claims.
請參閱第1圖至第9圖，其為依據本發明實施例所繪示的半導體裝置1的製作方法的剖面示意圖。根據本發明實施例，所述半導體裝置1可以是一半導體記憶體裝置，或者是包含有記憶體元件、高壓元件與低壓元件的系統單晶片(System-On-a-Chip，SOC)。 Please refer to FIG. 1 to FIG. 9 , which are schematic cross-sectional views showing a method of fabricating a semiconductor device 1 according to an embodiment of the invention. According to an embodiment of the invention, the semiconductor device 1 may be a semiconductor memory device or a System-On-a-Chip (SOC) including a memory device, a high voltage device, and a low voltage device.
如第1圖所示，在一半導體基材10上設置有一記憶體區域101以及一週邊(periphery)區域102，其中週邊區域102又可區分有一低電壓(low-voltage)區域102a以及一高電壓(high-voltage)區域102b。首先，在記憶體區域101內，形成一記憶體胞110。根據本發明實施例，記憶體結構11可以包括一記憶胞110以及一選擇電晶體210，其中記憶胞110靠近選擇電晶體210而設置。根據本發明實施例，所述半導體基材10可以是一矽基材，但不限於此。根據本發明實施例，所述記憶體胞110可以是一靜態隨機存取記憶體(SRAM)記憶胞，但不限於此。 As shown in FIG. 1, a memory region 101 and a peripheral region 102 are disposed on a semiconductor substrate 10. The peripheral region 102 can be further divided into a low-voltage region 102a and a high voltage. (high-voltage) region 102b. First, in the memory region 101, a memory cell 110 is formed. According to an embodiment of the invention, the memory structure 11 can include a memory cell 110 and a selection transistor 210, wherein the memory cell 110 is disposed adjacent to the selection transistor 210. According to an embodiment of the invention, the semiconductor substrate 10 may be a tantalum substrate, but is not limited thereto. According to an embodiment of the invention, the memory cell 110 may be a static random access memory (SRAM) memory cell, but is not limited thereto.
根據本發明實施例，所述記憶胞110可包括一多層堆疊結構，由一浮置閘極穿隧氧化層(floating gate tunneling oxide)111、一浮置閘極(floating gate)112、一多晶矽間介電層(interpoly dielectric)113，以及一控制閘極(control gate)114堆疊而成。根據本發明實施例，所述選擇電晶體210可包括一閘極氧化層211以及一多晶矽閘極212。熟習該項技藝者應理解，以上記憶體結構僅為例示，並非用以限制本發明範疇。 According to an embodiment of the invention, the memory cell 110 may comprise a multi-layer stack structure, comprising a floating gate tunneling oxide 111, a floating gate 112, and a polysilicon. An interpoly dielectric 113, and a control gate 114 are stacked. According to an embodiment of the invention, the selection transistor 210 may include a gate oxide layer 211 and a polysilicon gate 212. It should be understood by those skilled in the art that the above memory structures are merely illustrative and are not intended to limit the scope of the invention.
根據本發明實施例，所述記憶胞110還可包括一氧化矽(silicon oxide)層115，覆蓋在所述多層堆疊結構的表面。根據本發明實施例，所述記憶胞110還可包括一氧化矽側壁子116，設置在所述多層堆疊結構的側壁上。 According to an embodiment of the invention, the memory cell 110 may further include a silicon oxide layer 115 covering the surface of the multilayer stack structure. According to an embodiment of the invention, the memory cell 110 may further include a ruthenium oxide sidewall spacer 116 disposed on a sidewall of the multilayer stack structure.
根據本發明實施例，所述選擇電晶體210可包括一氧化矽層215，覆蓋在所述多晶矽閘極212的表面以及一氧化矽側壁子216，設置在多晶矽閘極212的側壁上。根據本發明實施例，可另包括一四乙氧基矽烷(TEOS)氧化矽層118，填入所述記憶胞110與選擇電晶體210之間的間隙。 According to an embodiment of the invention, the selection transistor 210 may include a hafnium oxide layer 215 covering the surface of the polysilicon gate 212 and a hafnium oxide sidewall spacer 216 disposed on the sidewall of the polysilicon gate 212. In accordance with an embodiment of the invention, a tetraethoxy decane (TEOS) yttrium oxide layer 118 may be additionally included to fill the gap between the memory cell 110 and the selective transistor 210.
根據本發明實施例，在形成上述記憶體區域101內的記憶體結構11之後，接著在週邊區域102的低電壓區域102a以及高電壓區域102b內，利用微影及蝕刻製程分別定義出閘極結構120以及閘極結構130。其中，閘極結構120可包括一閘極氧化層121以及一多晶矽閘極122，而閘極結構130可包括一閘極氧化層131以及一多晶矽閘極132。根據本發明實施例，閘極氧化層121的厚度小於閘極氧化層131的厚度。相較於高電壓區域102b內的閘極結構130，低電壓區域102a內的閘極結構120彼此間的距離較接近。 According to the embodiment of the present invention, after the memory structure 11 in the memory region 101 is formed, the gate structure is respectively defined by the lithography and the etching process in the low voltage region 102a and the high voltage region 102b of the peripheral region 102. 120 and gate structure 130. The gate structure 120 can include a gate oxide layer 121 and a polysilicon gate 122, and the gate structure 130 can include a gate oxide layer 131 and a polysilicon gate 132. According to an embodiment of the invention, the thickness of the gate oxide layer 121 is less than the thickness of the gate oxide layer 131. The gate structures 120 in the low voltage region 102a are closer to each other than the gate structures 130 in the high voltage region 102b.
如第2圖所示，接著，進行一多晶矽再氧化(poly reoxidation)製程，於所述閘極結構120以及所述閘極結構130表面分別形成一氧化矽層125以及一氧化矽層135。然後，於所述閘極結構120以及所述閘極結構130的側壁上，分別形成一氮化矽(silicon nitride)偏間隙壁(offset spacer)126及氮化矽偏間隙壁136。同時，在所述記憶胞110的側壁上，也會形成氮化矽偏間隙壁316。 As shown in FIG. 2, a poly reoxidation process is performed to form a hafnium oxide layer 125 and a hafnium oxide layer 135 on the gate structure 120 and the gate structure 130, respectively. Then, a silicon nitride offset spacer 126 and a tantalum nitride bias spacer 136 are formed on the gate structure 120 and the sidewall of the gate structure 130, respectively. At the same time, a tantalum nitride spacer spacer 316 is also formed on the sidewall of the memory cell 110.
如第3圖所示，繼續對記憶體區域101以及週邊區域102進行離子佈植製程30，將摻質植入所述半導體基材10的表面，形成輕摻雜汲極(LDD)區域320。所述離子佈植製程30係自動對準(self-align)氮化矽偏間隙壁126、氮化矽偏間隙壁136以及氮化矽偏間隙壁316。 As shown in FIG. 3, the ion implantation process 30 is continued on the memory region 101 and the peripheral region 102, and the dopant is implanted on the surface of the semiconductor substrate 10 to form a lightly doped drain (LDD) region 320. The ion implantation process 30 is a self-aligned tantalum nitride bias spacer 126, a tantalum nitride bias spacer 136, and a tantalum nitride bias spacer 316.
如第4圖所示，在完成離子佈植製程30之後，接著於所述閘極結構120的側壁上，形成一氧化矽襯墊層425及一氮化矽側壁子426，於所述閘極結構130上，形成一氧化矽襯墊層435及一氮化矽側壁子436。同時，在所述記憶胞110的側壁上，也會形成一氧化矽襯墊層415及一氮化矽側壁子416。形成氧化矽襯墊層415、425、435以及氮化矽側壁子416、426、436的方法是先沉積一均厚的氧化矽層，然後在沉積一均厚的氮化矽層，再利用一非等向性乾蝕刻製程回蝕刻所述氮化矽層以及氧化矽層。 As shown in FIG. 4, after the ion implantation process 30 is completed, a hafnium oxide liner layer 425 and a tantalum nitride sidewall spacer 426 are formed on the sidewalls of the gate structure 120 at the gate. On the structure 130, a hafnium oxide liner layer 435 and a tantalum nitride sidewall spacer 436 are formed. At the same time, a tantalum oxide liner layer 415 and a tantalum nitride sidewall spacer 416 are also formed on the sidewalls of the memory cell 110. The method for forming the yttrium oxide liner layers 415, 425, 435 and the tantalum nitride sidewall spacers 416, 426, 436 is to deposit a blanket layer of uniform thickness and then deposit a uniform layer of tantalum nitride, and then use one. The anisotropic dry etching process etches back the tantalum nitride layer and the tantalum oxide layer.
如第5圖所示，接著進行一化學氣相沉積(CVD)製程，沉積一均厚的氧化矽層505，例如，厚度約12奈米(nm)。然後，沉積一均厚的氮化矽 層506，例如，厚度約90奈米。 As shown in Fig. 5, a chemical vapor deposition (CVD) process is then performed to deposit a blanket yttria layer 505, for example, having a thickness of about 12 nanometers (nm). Then, deposit a uniform thickness of tantalum nitride Layer 506, for example, has a thickness of about 90 nm.
如第6圖所示，接著進行一非等向性乾蝕刻製程，回蝕刻氮化矽層506，直到顯露出下方的氧化矽層505，如此於所述閘極結構120的側壁上形成一氮化矽側壁子526，於所述閘極結構130上形成一氮化矽側壁子536，在所述記憶胞110的側壁上形成一氮化矽側壁子516。根據本發明實施例，在顯露出下方的氧化矽層505之後，可以繼續過蝕刻(over etch)氮化矽側壁子516、526、536一預定厚度。根據本發明實施例，此時氧化矽層505並未被蝕穿，而保留一預定厚度。 As shown in FIG. 6, an anisotropic dry etching process is performed to etch back the tantalum nitride layer 506 until the underlying yttrium oxide layer 505 is exposed, thereby forming a nitrogen on the sidewall of the gate structure 120. A silicon nitride sidewall spacer 526 is formed on the gate structure 130, and a tantalum nitride sidewall spacer 516 is formed on the sidewall of the memory cell 110. According to an embodiment of the invention, after exposing the underlying hafnium oxide layer 505, the tantalum nitride sidewall spacers 516, 526, 536 may be over-etched to a predetermined thickness. According to an embodiment of the invention, the yttrium oxide layer 505 is not etched through at this time, while retaining a predetermined thickness.
然後，於週邊區域102的高電壓區域102b內形成一犧牲保護層509，例如，TEOS氧化矽，其厚度可以約為15奈米左右。根據本發明實施例，形成犧牲保護層509的作法可以先在記憶體區域101以及週邊區域102以化學氣相沉積法全面沉積一TEOS氧化矽層，然後以一光阻圖案將週邊區域102的高電壓區域102b內的TEOS氧化矽層蓋住，再以濕蝕刻方式去除未被光阻圖案覆蓋的TEOS氧化矽層，再去除該光阻圖案。 Then, a sacrificial protective layer 509 is formed in the high voltage region 102b of the peripheral region 102, for example, TEOS yttrium oxide, which may have a thickness of about 15 nm. According to an embodiment of the present invention, the formation of the sacrificial protective layer 509 may firstly deposit a TEOS yttrium oxide layer by chemical vapor deposition in the memory region 101 and the peripheral region 102, and then the peripheral region 102 is high in a photoresist pattern. The TEOS ruthenium oxide layer in the voltage region 102b is covered, and the TEOS ruthenium oxide layer not covered by the photoresist pattern is removed by wet etching, and the photoresist pattern is removed.
如第7圖所示，接著可以利用一稀釋氫氟酸(DHF)溶液清除掉氮化矽側壁子516、526、536表面上的原生氧化矽(native oxide)層，此處理步驟也會蝕刻掉部分厚度的犧牲保護層509。根據本發明實施例，約10奈米厚度的犧牲保護層509會在此步驟中被蝕除。然後，以熱磷酸溶液去除未被犧牲保護層509覆蓋住的氮化矽側壁子516、526，僅留下週邊區域102的高電壓區域102b內的氮化矽側壁子536。 As shown in Fig. 7, the native oxide layer on the surface of the tantalum nitride sidewalls 516, 526, 536 can then be removed by a dilute hydrofluoric acid (DHF) solution, and the process step is also etched away. A portion of the thickness of the sacrificial protective layer 509. According to an embodiment of the invention, a sacrificial protective layer 509 having a thickness of about 10 nm is etched away in this step. Then, the tantalum nitride sidewall spacers 516, 526 not covered by the sacrificial protective layer 509 are removed with a hot phosphoric acid solution, leaving only the tantalum nitride sidewall spacers 536 in the high voltage region 102b of the peripheral region 102.
如第8圖所示，在去除氮化矽側壁子516、526之後，繼續以稀釋氫氟酸溶液蝕刻掉犧牲保護層509以及顯露出來的氧化矽層505，如此，在週邊區域102的高電壓區域102b內的閘極結構130上形成由氧化矽襯墊層435、535以及氮化矽側壁子436、536所構成的雙側壁子結構。在週邊區域102的低電壓區域102a內的閘極結構120上則形成由氧化矽襯墊層425以及氮化矽側壁子426所構成的單側壁子結構。 As shown in FIG. 8, after removing the tantalum nitride sidewall spacers 516, 526, the sacrificial protective layer 509 and the exposed hafnium oxide layer 505 are continuously etched away by diluting the hydrofluoric acid solution, thus, the high voltage in the peripheral region 102. A double sidewall substructure composed of yttrium oxide liner layers 435, 535 and tantalum nitride sidewall spacers 436, 536 is formed on the gate structure 130 in the region 102b. A single sidewall substructure composed of a hafnium oxide liner layer 425 and a tantalum nitride sidewall spacer 426 is formed on the gate structure 120 in the low voltage region 102a of the peripheral region 102.
如第9圖所示，進行源極/汲極離子佈植製程，將摻質植入所述半導體基材10的表面，形成源極/汲極區域920。後續步驟可繼續進行退火(anneal)、金屬矽化(silicide)製程、接觸製程以及後段金屬化製程。 As shown in FIG. 9, a source/drain ion implantation process is performed, and a dopant is implanted on the surface of the semiconductor substrate 10 to form a source/drain region 920. Subsequent steps can continue with annealing, metal silicide processes, contact processes, and post-metallization processes.
本發明上述半導體裝置的製作方法，僅需增加一道光罩(用來定義第6圖中的犧牲保護層509)，能夠提供高壓元件較大的側壁子寬度，對記憶體區域及低電壓區域內的元件提供較小的側壁子寬度，並且能夠相容於現行的邏輯製程。此外，本發明製程方法不會傷害到氮化矽偏間隙壁，也不會造成LDD區域的侵蝕損失。 In the method for fabricating the above semiconductor device of the present invention, it is only necessary to add a mask (to define the sacrificial protective layer 509 in FIG. 6), which can provide a large sidewall width of the high voltage component, in the memory region and the low voltage region. The components provide a smaller sidewall width and are compatible with current logic processes. In addition, the process method of the present invention does not damage the tantalum nitride spacer and does not cause erosion loss in the LDD region.
以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。 The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.
1‧‧‧半導體裝置 1‧‧‧Semiconductor device
10‧‧‧半導體基材 10‧‧‧Semiconductor substrate
11‧‧‧記憶體結構 11‧‧‧ memory structure
101‧‧‧記憶體區域 101‧‧‧ memory area
102‧‧‧週邊區域 102‧‧‧The surrounding area
102a‧‧‧低電壓區域 102a‧‧‧Low voltage area
102b‧‧‧高電壓區域 102b‧‧‧High voltage area
110‧‧‧記憶胞 110‧‧‧ memory cells
111‧‧‧浮置閘極穿隧氧化層 111‧‧‧Floating gate tunneling oxide
112‧‧‧浮置閘極 112‧‧‧Floating gate
113‧‧‧多晶矽間介電層 113‧‧‧Polysilicon interdielectric dielectric layer
114‧‧‧控制閘極 114‧‧‧Control gate
115‧‧‧氧化矽層 115‧‧‧Oxide layer
116‧‧‧氧化矽側壁子 116‧‧‧矽 矽 sidewall
118‧‧‧四乙氧基矽烷氧化矽層 118‧‧‧tetraethoxydecane ruthenium oxide layer
120‧‧‧閘極結構 120‧‧‧ gate structure
121‧‧‧閘極氧化層 121‧‧‧ gate oxide layer
122‧‧‧多晶矽閘極 122‧‧‧Polysilicon gate
125‧‧‧氧化矽層 125‧‧‧Oxide layer
126‧‧‧氮化矽偏間隙壁 126‧‧‧Nitride nitride spacer
130‧‧‧閘極結構 130‧‧‧ gate structure
131‧‧‧閘極氧化層 131‧‧‧ gate oxide layer
132‧‧‧多晶矽閘極 132‧‧‧Polysilicon gate
135‧‧‧氧化矽層 135‧‧‧Oxide layer
136‧‧‧氮化矽偏間隙壁 136‧‧‧Nitride nitride spacer
210‧‧‧選擇電晶體 210‧‧‧Selecting a crystal
211‧‧‧閘極氧化層 211‧‧‧ gate oxide layer
212‧‧‧多晶矽閘極 212‧‧‧Polysilicon gate
215‧‧‧氧化矽層 215‧‧‧Oxide layer
216‧‧‧氧化矽側壁子 216‧‧‧ yttrium oxide sidewall
316‧‧‧氮化矽偏間隙壁 316‧‧‧Nitride nitride spacer
320‧‧‧輕摻雜汲極區域 320‧‧‧Lightly doped bungee area
415‧‧‧氧化矽襯墊層 415‧‧‧Oxide lining
416‧‧‧氮化矽側壁子 416‧‧‧ nitride sidewalls
425‧‧‧氧化矽襯墊層 425‧‧‧Oxide lining
426‧‧‧氮化矽側壁子 426‧‧‧ nitride sidewalls
435‧‧‧氧化矽襯墊層 435‧‧‧Oxide lining
436‧‧‧氮化矽側壁子 436‧‧‧ nitride sidewalls
505‧‧‧氧化矽層 505‧‧‧Oxide layer
509‧‧‧犧牲保護層 509‧‧‧ Sacrificial protective layer
516‧‧‧氮化矽側壁子 516‧‧‧ nitride sidewalls
526‧‧‧氮化矽側壁子 526‧‧‧ nitride sidewalls
536‧‧‧氮化矽側壁子 536‧‧‧ nitride sidewalls
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