TWI307961B - - Google Patents

Description

1307961 V. INSTRUCTION DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention: The present invention relates to a thin film transistor array substrate technology for a liquid crystal display, and more particularly to a thin film transistor having a multi-gate structure and a method of fabricating the same. The prior art: a thin film transistor (hereinafter referred to as TFT) of a liquid display (1) is used as a switching element of a halogen element. It is divided into two types: amorphous 矽 TFT> and polycrystalline shi TFT. Since the polycrystalline silicon TFT has a higher carrier mobility, a better integration of the driving circuit, and a smaller leakage current, the polycrystalline germanium TFT is more commonly used in a circuit for operating speed. However, the current in the on (on) and off (off) states of the polysilicon is large, and a large electric field is generated in the depletion region adjacent to the drain region, so that the material gap and the energy gap generated by the piercing effect are extremely easy. When the electrons in the drain region are combined with the holes in the depletion region, the leakage current is liable to occur in the off state. In order to effectively improve the leakage current phenomenon, the current technology is to form an undoped offset region or a lightly doped drain (LDD) region between the gate and the drain. Used to reduce the electricity % of the drain juncti〇n. In addition, the polycrystalline stone T F T is designed as a multi-gate (m u 11 i - g a t e) structure, for example, a dual-gate structure, which can further alleviate the leakage current phenomenon. Please refer to the figure 1A~1 C, which shows the first type of double gate structure of 0773-9592CIPT»F(Nl); P92031; che r ry.ptd page 6 1307961 V. Description of invention (2) Schematic diagram of the spar ray TFT process. First, as shown in FIG. 1a, the glass substrate 10 includes a buffer layer 12 and a polysilicon layer 4, and is subjected to a process of bionic ion implantation (B+i〇n impiantati〇n) 16 for adjustment. , the whole, the threshold voltage of the crystal. Then, as shown in FIG. 1B, a gate insulating layer 8 is sequentially formed, and one of the first open electrodes 20 1 and the second gate layer 2 is separated. Then, a lightly doped ion cloth is used to make a straight process 2 2 ' using the first gate layer 2 〇丨 and the second gate layer 2 〇丨丨 as a hood, on the first gate layer 2 0 I and An N-doped region 14a is formed in the multi-turn layer 14 around the second gate layer 2 0 II. Subsequently, as shown in FIG. 1 : a positive deposition, lithography and etching process to form a photoresist layer 24, such as a gate layer 2〇I and a second gate layer 20丨丨N_doped y 14a. Finally, a heavily doped ion implantation process 26 is performed, using photoresist: domain 2 - 4, first gate layer 201 and second gate layer 2 〇 11 as a mask, two gates The n-domain 14a around the outer side of the layer 201 and the second gate layer 2〇11 becomes two...doped regions 丨", HD. Thus, the Ν-doped region 14a covered by the ϋ隹& 24 becomes an LDDH and Layer:: respectively = 2 〇 1 and the second idle layer ... j covered undoped region heart - 14 C2 becomes two channel regions. 1 The above process is easier to achieve the accuracy and electrical properties of yellow light P # 却 can not form L in the vicinity of the source/dual region of the dispute side of the 筮一托 a 〇» & The structure of the two external TFTs must be sacrificed from the gate, and the polysilicon 矽h± is turned on (the current of 〇1° is increased to improve the leakage current of the region Too big ==

0773-9592CIPIW(Nl) ;P92031 ;cherry .ptd_ Page 7

MS MS1307961

Please refer to the ID diagram for a schematic diagram of the polycrystalline 矽TFT process of the two-gate structure of the Xiangqian soil knot _ ^ ε.Τϋτ A1 ····贝不 S知弟. The method of making a flute is basically the same as that of the above-mentioned process, and the similarities are omitted here. The light is in the design of the layer:==. After the steps of the above ία~iBm are completed, as shown in the figure, the deposition, lithography and etching processes are performed to form - - 篦! „ 241 and a first photoresist layer 2411 ′ such that the first photoresist layer 241 covers the first layer N_# impurity region i4a of the electrode layer 2GI and its surroundings, and the first layer 2411 covers the second gate layer 2GII and The surrounding - part of the N-doped field 14a. Finally, a heavily doped ion implantation process 26 is performed, using the first photoresist layer 241, the second photoresist layer 2411, the gate layer 2 () 1 and the second The idle layer 20 II serves as a mask such that the first gate layer 2〇I and the N-doped region 丨4 a around the outer side of the second gate layer 2 0 II become three N+ doped regions 14S, 14D, US In this way, the N-doped regions 14\, 14^, 14^, 14~ covered by the first photoresist layer 241 and the second photoresist layer 2411 become four LDD regions, and the N+ doping region 143 , UD, 14S/D are respectively a source region, a drain region, and a common source/drain region, and are undoped by the first gate layer 201 and the second gate layer 2〇1丨. The regions HCi and 1 4 C2 are two channel regions. The LDO region can be formed in the periphery of the first and second gate layers 2〇1 and 2〇11 and the polycrystalline layer 14 inside. Can effectively suppress leakage Flow. But 'restricted by the exposure technique's alignment error (ph〇t〇misal ignment) 'difficult to control the four n-doped regions 148丨, 14~, 1 4 a; 5, 1 4 length symmetry' And the positional offset of the lj) d region will occur.

0773-9592CIPTW(Nl);P92031;cherry.ptd Page 8!3〇7961 ---- V. Invention description (4) - Image, which leads to Thunder JBil ---- Preparation order t The problem of electrical asymmetry and low yield is presented. The process is complicated, and the content of the invention: There are 4 supervisors here, too, the purpose of the invention is to provide a method of inserting the side of the eve, which can be used in each of the interpole/diode structures.

And can be exempted from M. < Query, and reach the electrical formation of the LDD region, the symmetry of the food symmetry, the second generation of the ancient ^ ❸ 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本Miscellaneous area;! a first channel region and a first region formed in the second doped region and a second channel region, the first channel region and the fifth lightly doped region, The outer side of the system; the heavily doped region and a second: the outer side of the channel region; the other is formed in the lightly doped region and the first: ± ^ region, respectively, the shape of the shape and a first edge layer formed in This has the side of the lusheng area*. ^The fourth ί the first-heart region of the active layer and =: - the fourth lightly doped region of the central C active layer] the first masking region, the ^-covering; the second lightly doped region of the active layer The second shielding area;; ί on the active layer 'and includes: - - the pole insulating layer: covering the second channel region; a central region, the system covering the ^ ^ system to form the first shielding region, covering the Layer __ benefit the effective j® ~ political layer

0773- C D E -9592CIPWF(N1) ; P92031 ;cherry .ptd 1307961 V. Description of the invention (5) A three-lightly doped region; and a second masking region covering a fifth lightly doped region of the active layer. A first gate layer is formed on the first gate insulating layer and covers a central region of the first gate insulating layer. A second gate layer is formed on the second gate insulating layer and covers a central region of the second gate insulating layer. In order to achieve the above object, the present invention provides a method of fabricating a thin film transistor having a multi-gate structure, which comprises the following steps. An effective layer, an insulating layer and a conductive layer are sequentially formed on a substrate. The conductive layer is defined as a first gate layer and a second gate layer ′ and the insulating layer is defined as a first gate insulating layer and a second gate insulating layer. The first gate insulating layer includes a central region, a first shielding region is formed on one side of the central region, and a second shielding region is formed on the other side of the central region. The first gate layer covers a central region of the first gate insulating layer. The second gate insulating layer includes a central region, a first shielding region is formed on one side of the central region, and a second shielding region is formed on the other side of the central region. The second gate layer covers a central region of the second gate insulating layer. The second shielding region of the first gate insulating layer is adjacent to the first shielding region of the second gate insulating layer, and the second shielding region of the first gate insulating layer and the second gate insulating layer The gap between the first masking regions exposes the active layer below. Performing a lightly doped ion implantation process, forming a plurality of regions having different doping concentrations in the active layer: a first region and a second region are an undoped region, and are respectively formed in the first region a central region of the gate insulating layer and a lower portion of the central region of the second gate insulating layer; a third region and a first

0773-9592CIPTWF(Nl); P92031jcherry.ptd Page 10 1307961 V. Description of the invention (6) The four-region is a region having a first domain doped in the first gate insulating layer; a fifth region and concentration a lightly doped region, and a lightly doped region of the first doped region of the first masking region of the lightly doped edge layer having the second doping tempering, respectively, and a second outer region; The lightly doped region is formed on the photoresist layer of the second gate insulating layer to cover the first mask of the first gate-first insulating layer. Performing a heavily doped ion cloth five-region to have a third doped seven region and the eighth region becomes a light concentration. The first-masking sixth region is formed in a lower impurity region of the first region, and the side; And forming the nine regions as the first gate of the first gate of the first gate region, and the implantation process, and the doping region of the lightly doped region with the impurity concentration is the same as the first system The second gate is formed in the shai region, and the second gate is a second gate, and the second shielding gap at the gap of the second insulating layer is used to dope the third region. The region, the domain 0 and the second doping region of the first doped layer are respectively a first doping layer having a second doping layer and a second doping region. Forming a region, the ninth region, and the first embodiment: The present invention provides a polygate @TFT having a multi-gate structure and a method for fabricating the same by using a gate insulating layer exposed to both sides of the gate layer As a mask for the ion implantation process, the masked area can simultaneously produce the LDD region and the source/drain region. Thus, an LDD region can be formed on both sides of each gate layer so that the polysilicon τ has a very low leakage current, and the problem of yellow light alignment can be eliminated, and the length symmetry of the LDD region is achieved.

0773-9592CIPnvF(Nl);P92031;cherry.ptd Page 11 1307961 V. INSTRUCTIONS (7), Having the above and other objects, features, and characteristics of the present invention, a double-closed structure of polycrystalline stone The TFT is described in detail as an example and is accompanied by the accompanying drawings, and is described in detail as follows: [First Embodiment] Mei &22; 2A to 2E, which shows the 雔n pole of the first embodiment of the present invention, ,. A schematic cross-sectional view of a method of fabricating a TFT. - Gate π bed: You're providing a substrate 30 as shown in Figure 2, and a buffer layer 32 and an active layer 34 on the substrate 30. The preferred substrate 30 is a soil substrate, such as a glass substrate. Preferably, the buffer layer 32 is: :: in the second layer: Example: a layer of yttrium oxide, the purpose of which is to help the effective layer 3 4 : into: = 3 〇. The preferred layer of the active layer 34 is a semiconductor layer such as a layer of n. In order to adjust the threshold voltage Uhreshold V〇1叩6) of the transistor, a B+ 〇r P ion implantation process can be performed, and then, as shown in Fig. 2B, > + layer 36 and A conductive sound 38. Preferably, the upper layer is deposited on the active layer 34 - the insulating - gasified tantalum layer, the preferred one of the niobium oxynitride - the tantalum oxide layer, preferably the - metal layer or - more = and the electric layer 38 light The resistance is used as a mask for dry etching. The π is made into a -first-electrode layer 381 and the first conductive layer 38 is defined as a pattern of ^, 4m ^ 9 Γ ® - first open layer 3811. Following :=2. If the figure is not, the plasma etching should be performed, and it can be used - the right person ¥ yg; ^ ^ gas, the remaining layer of the conductive layer 38 and the mixed table of the chlorine gas Gradually adjusted traffic

0773-9592CIFTWF(Nl);P92031;cherry.ptd 605 Page 12 1307961 V. Description of invention (8) --- To the extreme (even using only gas containing gas as etching reaction gas), to be insected to the insulation At the same time, the layer 36 can simultaneously pass oxygen or increase the oxygen flow rate, and at the same time, the first and second gate layers can be etched to expose the first and second gate layers, and the first and second gate layers 38I can be used. 3811 is formed into a trapezoid having a narrow upper and a lower width, and the insulating layer 36 can be made into two first and second gate insulating layers 40 and 42. The patterned photoresist is subsequently removed. For the first gate insulating layer 4, it includes a central region 40a, a first shielding region 401^, and a second shielding region 4〇b2. The central region 40a is covered by the bottom of the first gate layer 381, and the first and second shielding regions 40b, 4b2 are respectively exposed on both sides of the bottom of the first interlayer 381, and the first gate insulating layer 4 The 0 system exposes one of the predetermined source/drain regions of the active layer 34. Preferably, the lateral length % of the first masking region 4〇bi is 〇. i #m~2·0μπι ′ The lateral length boundary 2 of the second masking region 4〇b2 is 〇.1 〜2_0 # m. According to the circuit design requirements, the length of %, % and its symmetry can be adjusted appropriately. For the second gate insulating layer 42, it comprises a central region 42a, a first shielding region 42 h and a second shielding region 42 b2, and the central region 4 2 a is the second gate layer 3 8 II Covered by the bottom, the first and second shielding regions 42b], 42b2 are respectively exposed to the bottom two sides i of the second gate layer 38 II and the second gate insulating layer 42 is exposed to one of the active layers 34 Source/bungee area. Preferably, the lateral length 匕 of the first shielding area 42 b! is 0.1 /zm to 2.0 / zm, and the lateral length 〇2 of the second shielding area 42b2 is 0.1 / / 111 ~ 2. 0 μ m. According to the circuit design requirements, the lengths of Di and D2 and their symmetry can be adjusted appropriately, and the symmetry of %, W2, D, and D2 can be adjusted. The better one is:

0773-9592CIPTWF(Nl);P92031;cherry.ptd Page 13 1307961

V. Description of the invention (9) wi=D2, 〇 further, the second shielding region 4 〇h of the first gate insulating layer 40 is adjacent to the first shielding region 42N of the second gate insulating layer 42, and The gap between the second shielding area 40b2 and the first shielding area 42bi is exposed to the lower effective layer. The outer side of the first shielding area 40b of the second gate edge layer 40 is exposed to the lower effective layer 34'. The outer side of the second masking region 22t) of the second gate insulating layer 42 exposes the underlying active layer 34. 2, then, as shown in FIG. 2D, a lightly doped ion implantation process 44 is performed, using the first and second gate layers 38, 38, and the masking region 40 of the first gate insulating layer 40. b!, 4 ΟΝ, the shielding regions 421^, 42bz of the second gate insulating layer 42 as a mask' can form a plurality of regions having different doping concentrations in the active layer 34. The first and second regions 341, 342 are undoped regions 'and are correspondingly formed below the central regions 4a, 42a. The second and fourth regions 343 and 344 are an N-doped region, and are correspondingly formed under the first and second shielding regions 4 〇 h, 4 0 b2 of the first gate insulating layer 40. The fifth and sixth regions 345, 346 are an N-doped region, and are correspondingly formed under the first and second shielding regions 42 b!, 42 b > 2 of the second gate insulating layer 42. The seventh region 347 is an N-doped region exposed outside the first shielding region 4Ob! of the first gate insulating layer 40. The 'eight' region 3 4 8 is an N-doped region exposed to the outside of the second masking region 42b2 of the second gate insulating layer 42. The ninth region 349 is an N-doping region ′ that is exposed to the gap of the first shielding region 42b! of the second shielding region 4 〇b2 'the second gate insulating layer 42 of the first gate insulating layer 40 At the office. It is worthy of the main sound, because the shielding area of the first gate insulating layer 40, 4Gb,: 2 brother

1307961 V. INSTRUCTION OF THE INVENTION (10) The shielding region 42b 42b of the gate insulating layer 42 is used as a mask for the light=process, so the third and fourth regions 343 and 3 are “different and five: sixth region 345, The edges of 34 6 are substantially aligned with the edges of the first and first masking regions 42^, 42bz. In addition, by adjusting the light doping distance, the accelerating voltage and the dose of the implantation process 44, the concentrations of the third, fourth, fifth, and sixth regions 343, 344, 345, and 346 can be controlled to be blended. ^ impurity region or a very small interval region (〇f fset regi () n): , after taking, as shown in Figure 2E, deposition, lithography and etching process to y into a photoresist layer 46, so that The second shielding region 4〇b2 of the first gate insulating layer 4, the first shielding region 42h of the second gate insulating layer 42 and the ninth region 34 9 at the gap thereof are covered. Continuing, a heavily doped ion implantation process 48 is performed, using the photoresist layer 46, the first and second gate layers 38I, 3811, the first shielding region 40 bi of the first gate insulating layer 40, and the second gate. The second shielding region 42b2 of the insulating layer 42 serves as a mask to increase the doping concentration of the third region 343, the sixth region 346, the seventh region 347, and the eighth region 348 of the active layer 34. As a result, the third and fourth regions 343, 344 become an N-doped region, the seventh region 347 becomes an N+ doped region, and the eighth region 348 is an N+ doped region. As can be seen from the above, the seventh region 347 and the eighth region 348 are "doped regions, which are used as a source region and a drain region; and the third region 343 and the sixth region 346 are N-doped regions. The LDD region is used as the periphery of the double gate structure; the fourth region 344 and the fifth region 345 are the doped regions, which are used as the LDD region inside the double gate structure; the ninth region 349 is ^

1307961 BRIEF DESCRIPTION OF THE DRAWINGS The first embodiment of FIGS. 1A to 1C shows a schematic cross-sectional view of a conventional polysilicon TFT process of the first double gate structure. Fig. 1D is a schematic cross-sectional view showing a conventional polysilicon TFT process of the second double gate structure. 2A to 2E are cross-sectional views showing a method of fabricating a polysilicon TFT having a double gate structure according to a first embodiment of the present invention. Fig. 3 is a cross-sectional view showing a polysilicon TFT of a double gate structure according to a second embodiment of the present invention. DESCRIPTION OF REFERENCE NUMERALS: conventional technique 4 standard glass substrate ~10; buffer layer ~12; polycrystalline germanium layer ~1 4 ; N -doped region ~1 4 a,1 4 a!,1 4 a2,1 4 a3,1 4 a4 N+ doped region ~14S, 14D, 14S/D; undoped region ~14 (^, 14C2; boron ion implantation process ~16; gate insulating layer ~1 8; gate layer ~20; first Gate layer ~ 2 0 I; second gate layer ~ 2 0 II ; lightly doped ion implantation process ~ 2 2 ; photoresist layer ~ 24, 241, 2411; heavily doped ion implantation process ~ 26. Invention technology

〇773-9592CIPTWF(Nl);P92031;cherry.ptd Page 19 1307961 Schematic description of the substrate ~3 0; buffer layer ~3 2 ; effective layer ~3 4 ; area ~341 ' 342 '343 '344 '345 ' 346 '347 '348 ' 349 ; Insulation layer ~ 3 6 ; First gate layer ~ 3 8 I ; First gate insulating layer ~ 4 0 Central area ~ 40a ; Second masking area ~ 40b2 Extended area ~ 40c ; Area ~42a; second masking area ~42 b2 extension area ~42c; photoresist layer ~4 6 ; conductive layer ~38; second gate layer ~3 8 II; first masking area ~401^; second gate Insulation layer ~ 4 2 ; first masking area ~ 421 ^ ; lightly doped ion implantation process ~ 44; heavy doping ion implantation process ~ 4 8 .

0773-9592CIPTW(Nl) ;P92031 ;cherry .ptd第20页

Claims (1)

1307961 Case No. 92134005 曰6. Patent application scope 1. Mip year/multiple gate structure thin film transistor, including V: /% substrate, an effective layer, formed on the substrate, and including: a lightly doped region as a common source/drain; a second lightly doped region and a third lightly doped region are respectively formed on both sides of the first doped region; a first channel region and a first a second channel region is formed on the second doped region and the third doped region, respectively; the second, the second, the fourth, the lightly doped region, and the fifth lightly doped region are Forming a first channel region and an outer side of the second channel region, wherein the concentration of the three lightly doped regions is greater than the concentration of the fourth and fifth lightly doped regions; and a first heavily doped region and a second weight a doped region is formed on the outer side of the fourth lightly doped region and the fifth lightly doped region, respectively; a first gate insulating layer is formed on the active layer, covering the first channel region, The fourth lightly doped region And the second lightly doped region; a second gate second channel region; the first cover-channel second gate two-channel pole insulating layer is formed on the active layer, covering the a third lightly doped region, and the fifth lightly doped region electrode layer is formed on the first gate insulating layer, and the first gate insulating layer over the overlying region; and the pole layer is formed And on the second gate insulating layer, and covering the gate insulating layer above the region. 0773-9592CIPTWF2(Nl).ptc Page 21 1307961 . _ Case No. 92134005_年月月__ VI. Patent application scope 2. The film transistor of the multi-gate structure as described in claim 1 of the patent application, Wherein the second lightly doped region and the third lightly doped region have the same doping concentration and length. 3. The thin film transistor of the multi-gate structure of claim 1, wherein the fourth lightly doped region and the fifth lightly doped region have the same doping concentration and length. 4. The thin film transistor of the multi-gate structure according to claim 1, wherein: the doping concentration of the first lightly doped region, the fourth lightly doped region, and the fifth lightly doped region 1 X 1 012 〜1 X 1 014 a tom/cm 2 ; the second lightly doped region, the third lightly doped region has a doping concentration of less than 1×10 13 atom/cm 2 ; and the first heavily doped region The doping concentration of the second lightly doped region is lx 1014~lx 1016 atom/cm2. 5. The thin film transistor of the multi-gate structure according to claim 1, further comprising an insulating extension region extending from both sides of the first and second gate insulating layers and covering the The first and second heavily doped regions of the active layer and the first lightly doped region, and the thickness of the insulating extension region is less than the thickness of the first and second gate insulating layers. 6. The thin film transistor of the multi-gate structure according to claim 1, wherein: the substrate is a transparent insulating substrate or a glass substrate; the active layer is a semiconductor germanium layer or a polysilicon layer; The first gate insulating layer is a tantalum oxide layer, a tantalum nitride layer, and a 0773-9592CIPTWF2(Nl).ptc page 22 1307961, _ case number 92134005_车月日_i±^_6, the patented range of yttria layer or a combination thereof; and the second gate insulating layer It is a stacked layer of a ruthenium oxide layer, a tantalum nitride layer, a ruthenium oxynitride layer or a combination thereof. 7. The thin film transistor of the multi-gate structure according to claim 1, further comprising a buffer layer formed between the substrate and the active layer. 8. The thin film transistor of the multi-gate structure according to claim 1, wherein the first, second, third, fourth, and fifth lightly doped regions and the first and second heavily doped The impurity regions are ion doped regions of the same conductivity type. 9. A method of fabricating a thin film transistor having a multi-gate structure, comprising the steps of: providing a substrate; forming an active layer on the substrate; forming an insulating layer on the substrate to cover the active layer; forming a conductive Laminating on the insulating layer; performing an etching process, defining the conductive layer as a first gate layer and a second gate layer, and defining the insulating layer as a first gate insulating layer and a second a gate insulating layer; wherein the first gate layer covers a central region of the first gate insulating layer and exposes a region on both sides of the first gate insulating layer; wherein the second gate layer covers the first gate layer a central region of the gate insulating layer and exposing a region on both sides of the first gate insulating layer; wherein a gap between adjacent side regions of the first and second gate insulating layers 0773-9592CIPTWF2(Nl).ptc Page 23 1307961 , _ Case No. 92134005_Yearly revision _ 6. The effective layer under the exposure of the patent application area; Perform a lightly doped ion implantation process on the active layer Forming a plurality of regions having different doping concentrations; wherein a first region and a second region are an undoped region, and are respectively formed in a central region of the first gate insulating layer and the second gate a lower portion of the central region of the insulating layer; wherein a third region and a fourth region and a fifth region and a sixth region are respectively lightly doped regions having a first doping concentration, and each Formed under the regions on both sides of the first and second gate insulating layers; wherein a seventh region is a lightly doped region having a second doping concentration, and is formed in the first gate insulating layer An outer region; wherein, an eighth region is a lightly doped region having a second doping concentration, and is formed on an outer side region of the second gate insulating layer; wherein, a ninth region is a second Light doping a region formed at a gap between adjacent side regions of the first and second gate insulating layers, and the ninth region serves as a common source/drain; forming a photoresist layer to cover the first and the first An adjacent side region of the second gate insulating layer and the ninth region at the gap thereof; and performing a heavily doped ion implantation process to make the third region and the sixth region have a third doping concentration Lightly doping the region, and making the seventh region and the eighth region a heavily doped region, wherein the first doping concentration of the fourth and fifth regions is smaller than the third doping concentration of the third and sixth regions 0 1 0. The thin film structure of the multi-gate structure as described in claim 9 0773-9592CIPTWF2(Nl).ptc Page 24 1307961 _Case No. 92334005 Patent application method, wherein the second modification 曰B is the same as the doping concentration and length. The region and the sixth region have a phase 11 - a method for fabricating the crystal of the ninth application, wherein the film of the multi-gate structure of the fourth embodiment is electrically doped with a doping concentration and a length. The region shouts and the fifth region has a plurality of gate structures of the plurality of gate structures, such as the method for fabricating the crystal of the ninth item of the patent application, wherein the third region and the sixth region are doped regions The doping concentration is 1 χ } 〇 32 is the doping concentration 1 atom/cm 2 of the ninth region having the third doping concentration; the fourth region and the fifth region are: 1 Ο 1, 1 x 1 014 at 〇m/cm2 ; atom/cm2 ; and ^ ^ The degree of agriculture is less than 1 x 1 〇i3 The seventh region 'the eighth region becomes h 1014~lx at〇ln/cm2. 3. The method of fabricating a crystal according to claim 9 wherein the etching process comprises a thin film of a germanium structure. The cross of the insulating drawer is stupid, the taste layer, a second gate insulating layer, the R layer is a region, and the insulating extends: the insulating extending region extends from the first and second portions and covers The seventh region, the eighth region, and the side region of the active layer, and the thickness of the insulating extension region is smaller than the thickness of the first and second edge layers. 1 — The gate is absolutely 曰 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0773-9592CIPTWF2(Nl).pt Page 25 1307961 Λ-_η_§正S号 92134005 VI. Scope of Application The substrate is a transparent insulating substrate or the active layer is a semiconductor layer or polycrystalline stone.夕]·' Nitrogen-the gate insulating layer is a stacked layer of mono-oxidation, day-rolled ruthenium or a combination thereof; and emulsified hair layer nitrogen, the second gate insulating layer is an oxidized yttrium oxide layer or Combined stacking layer ^ g, weathered dream layer 1 5. As in the method of making the q-th crystal of the patent scope of the application, in the form::::: The thin film of the pole structure between the soils: forming a buffer layer of the substrate ^ h刖 另 另 另 6. 6. 6. 6. 6. 6. 6. 6. 6. 6. 6. 6. 6. 6. 6. 6. 6. 6. 6. 6. 6. 6. 6. 6. 6. 6. 6. 6. 6. 6. 6. 6. 6. 6. 6. 6. 6. 6. 6. 6. 6. , the film of electricity seven? 7 2. The ionic doping of the same conductivity type by the first region is the same as the F, Q domain as described in item 9 of the patent application. The lightly doped ion implantation process in Yiyi 1; the electric brother has a gate layer, and the first and second coins '^ the first mask. The two sides of the female layer are a plurality of thin film transistors of a multi-gate structure, including: the substrate having a pair of first and second transistors disposed on the pair of transistors: An active layer is formed on the substrate; the first and second gate insulating layers are disposed on the active layer; and the first and second gate electrodes are respectively disposed on the first insulating layer And the two sides are exposed; the first and second pairs of source/drain regions are disposed on the gate, the, and the edge of the edge of the two 0773-9592 CIPTWF2 (Nl). ptc page 26 1307961 _ case number 92134005_ years曰__6. An effective area other than the patent application side, and one of the source/drain regions is shared by the first and second transistors; and the first and second pairs of lightly doped regions are respectively formed in the The inner side of the first and second pairs of sources/drain electrodes, and each of the lightly doped regions includes two impurity regions of asymmetric concentration. 1 9. A film of a multi-gate structure as described in claim 18, wherein the source of the common source and the napped regions on both sides of the polar region have the same doping concentration and length. 20. The thin film transistor of the multi-gate structure of claim 18, wherein the lightly doped regions adjacent to the source/drain regions have the same doping concentration and length. 2 1. The thin film transistor of the multi-gate structure according to claim 18, wherein: the common source/drain region, the non-common source/drain region adjacent to the lightly doped region The impurity concentration is 1 X 1 012 〜1 X 1 014 a tom/cm 2 ; the doping concentration of the lightly doped region on both sides of the shared source/drain region is less than 1×10 13 a tom/cm 2 ; and the non-common The doping concentration of the source/drain region is 1 x 1 〇 14 〜 1 x 1 Ο 16 a tom/cm 2 〇 2 2. The thin film transistor of the multi-gate structure according to claim 18, wherein The first gate insulating layer further includes an extended region extending from both sides of the first and second gate insulating layers to the first and second source/drain regions, and the thickness of the extended region is smaller than the The thickness of the gate insulating layer. 0773-9592CIPTWF2(Nl).ptc Page 27 1307961 . _ Case No. 92134005_年月日日__ VI. Patent application scope 2 3. A multi-gate structure thin film transistor as described in claim 18 Further, a buffer layer is formed between the substrate and the active layer. 2. The thin film transistor of the multi-gate structure according to claim 18, wherein the doped regions are ion doped regions of the same conductivity type. 0773-9592CIPTWF2(Nl).ptc Page 28