200915574 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種顯示裝置，特別是有關於一種 低溫多晶矽薄膜電晶體液晶顯示裝置及其製作方法。 【先前技術】 一般而言’薄膜電晶體（thin film transistor; TFT)可 以分為非晶矽（amorphous)薄膜電晶體及多晶石夕 (polysilcion)薄膜電晶體。多晶矽薄電晶體係使用低溫多 晶矽（low-temperature polysilicon; LTPS)技術製作，且與 非晶石夕（a-Si)技術所製作的非晶石夕薄膜電晶體十分的不 同。低溫多晶石夕（LTPS)電晶體具有較大的電子遷移率 (electron mobility)(>20 cm2/Vsec)，因此，LTps 電晶體具 有相對較佳的尺寸、較大的開孔率（aperture rati〇)及較低 的功率消耗(power ratmg)。此外，低溫多晶矽製程可在 同一基板同時製作驅動電路及薄膜電晶體，使得可增顯 示面板的可靠性⑽iabmty) ’及降低顯示面板的製彳^ 本。 然而’傳統之低溫多晶秒驅動電路及薄膜電 製作’需要8道或9道光罩’使得需花費較高 ： 本。此外’較多的光罩數也導致較長的製作時間 的製作良率。 民 晶石夕製 因此，亟需一種具有較少光罩數之低溫多 程，以降低製作成本。 0773-A33387TWF;P2007053 5 200915574 【發明内容】 有鑑於此，本發明一實施例係提供一種影像顯示系 統，包含·一 低溫多晶矽（1〇w_temperature 如ic〇n; LTPS)驅動電路及薄膜電晶體伸沁打如的如以叫 TFT)。此驅動電路及薄膜電晶體，包含··一基板；一主 動層，形成於該基板上；一閘極絕緣層，覆蓋該第一主 動層，’I電層，位於該閘極絕緣層上，且該介電層具有 + I伸°卩，以及一閘極電極，形成於該介電層上，且暴 露該延伸部；—包含有—上下電極的儲存電容，形成: 基板上；—躺孔，形成於間極絕緣層之巾，且此接觸 =暴：下電極與主動層鄰接的區域。上述影像顯示系 速=含複數個導線及—晝素電極，其中導線係電性 上，以電性連接曰素電極形成於基板 _ + '甩日日體上述）丨電層的延伸部可降 低薄膜電晶體的關閉電流(I〇ff)。 本發明另一實施例係提供— 方法，包含提供_低、、☆種办像#不系統的製作 此低㈤多低，血夕日日矽驅動電路及薄膜電晶體。 含：提供-基板，·形成一第―乍方法，包 該基板上；進行_ ρ+Μ㈣動層及—第二主動層於 該第二主動層之巾^ ^㈣成—源/汲極區域於 第-主動声?成—具有-延伸部的介電層於該 極電極==成—第—間極電極及-第二閉 口次矛主動層與該篦__ 茨弟―主動層上方；以及進行 〇773-A33387TWF;P2〇〇7〇53 200915574 :N+#雜製程’以同時形成—輕摻雜源/汲極區域及一源 Λ及極區域於該第—主動層之中。上述影像顯示系統的製 作方法’更包含形成複數個導線於該基板上，以電性連 接該驅動電路與該薄膜電日日日體；以及形成-晝素電極於 该基板上，且電性連接該薄膜電晶體。上述形成具有延 伸部之介電層與第—及第二雜電極的方式，包含沈積 -介電層及一金屬層，接著，圖案化金屬層，以同時形 成第一、第二間極電極及具有延伸部之介電層。 由於上述介電層的延伸部可與閘極電極同時形成， 而不需額外使用光罩，因此，可減少製程的光罩數。再 ^ ’上述_電極以及介電層的延伸部可作為遮罩，使 付可全面性地進行Ν+摻雜製程’而不需要额外的光罩， 且可於一次摻雜步驟同時形成輕摻雜源/汲極區域及源/ 〉及極區域°據此’本發明實施例之影像顯示系統的製作 方法，可減少光罩數，進而降低製作成本。 、、本發明y實施例係提供—種影像顯示系統的製作 方法’包含提供-低溫多晶⑪驅動電路及薄 此低溫多晶矽驅動電路及薄膜電晶體的製作方法，勺 含··提供-基板；形成一第一主動層及 動二 兮I 4c I· w , π —王動層於 Μ土板上，形成—具有一延伸部的介電層於該第一主 層上方，分別形成—第一一— 該第-主動層與該第二主動及以二:閘㈣ 制仿 勒膺上万，以及進仃—Ν+摻雜 於5亥第一主動層之中；進行一 Ρ+摻雜製程，以形成 :二：輕摻雜源/汲極區域及，極區域 源/ 0773-A33387TWF;P2007053 7 200915574 汲極區域於該第二主動層 伸部之介電f ㈣1料成具有延 一介電界：曰一及弟二閉極電極的方式，包含沈積 成二=-金屬層，接著，圖案化金屬層，以同時形 德顧-备 開極電極及具有延伸部之介電層。上述影 ’’Ί統的製作方法’更包含形成複數個導線於該基 板上，以電性連接該驅動電路與該薄膜電晶體；以及ς 成旦素電極於該基板上，且電性連接該薄膜電晶體。 【實施方式】 接下來，將詳細說明本發明之具體實施例及其製作 的方法°然而’可以了解的是’本發明提供許多可實施 於廣泛多樣之應用領域的發明概念。用來說明的實施 例，僅是湘本發明概念之具體實施方式的說明，並不 限制本發明的範圍。 本發明係以低溫多晶矽（LTPS)驅動電路及薄膜電晶 體(TFT)的實施例作為說明。然而，本發明的概念當然也 可以=來製作其它積體電路。第1A_m圖係顯示根據本 表月第貝細例之製作一種低溫多晶石夕驅動電路及薄膜 電aa體的σ彳面圖。苐2A-2G圖係顯示根據本發明第二實 把例之製作一種低溫多晶石夕驅動電路的剖面圖。 如第1Α圖所不，提供一上方形成有一緩衝層（buffer layer)l〇2的基板100，且此基板1〇〇可以劃分為一驅動 區域（driving area) 1 〇4 及一晝素區域(pixd area) 1 〇6。在一 貝％例中，上述基板100可以是玻璃、塑夥或其它合適 0773-A33387TWF;P2007053 8 200915574 的透明基材。 接著 $ 成半^Γ 體層（semiconductor layer) 108 於 基板100上方。在-實施例中，形成半導體層⑽的方 式’可以是藉由例如是仆 γ · &化學现相沈積（chemical vapor deposition·，CVD)法，冰往 L 積〜非晶；δ夕層（amorphous silicon layer)於上述基板100上古 t方’接著，進行一準分子雷射退 火（， her annealmg; ela)處理，使得此非晶石夕層 可結晶成為-多晶矽層(p〇lysiHc〇nlayer)。 如第1B圖所示，_电 ， 圖案化上述半導體層108,接著， 進行一摻雜製程，以形成士壬, n 双主動詹（active layer) 112、主動 層114及已推雜之半違_顺p 等祖層 115(doped semiconductor 106之部分已摻雜半導體層 電晶體（TFT)的主動層。在一實 施例中，上述摻雜製程士 〜 ,..^ 也可以在圖案化半導體層步驟之 前進行。 layer)。此外，位於晝 115也可作為後續之薄膜 ' 仅1中’也可以在進行沈積非晶矽層 時，同時進行摻雜製程，蚀& 然後，再進行雷射退火非晶矽 層，使其轉化為多晶矽饴 ^ Μ I ’再圖案化此多晶破層。上述 摻雜製程也可以稱為通道协 、捧雜製程（channel doping)。 如第1C圖所示，推〜 運仃一例如是硼離子的P+摻雜製 程12 2 ’以形成一源/访k τ™ 及極區域（source/drain region) 114b 於主動I 114之中。在〜實施例中，塗佈一光阻材料於 上述基板100上’接著，圖案化此光阻材料，以形成圖 案化光阻層118及12G。在驅動區域1Q4，圖案化光阻層 0773-A33387TWF；P2007053 9 200915574 118係遮蔽主動層112，而圖案化光阻層120係遮蔽部分 的主動層114，以暴露欲摻雜的部分。在晝素區域106， 圖案化光阻層118係遮蔽部分已摻雜之半導體層115,以 暴露欲摻雜的部分。接著，進行一摻雜製程122，以形成 源/汲極區域114b及通道區域114a，且在晝素區域106， 形成一儲存電容（storage capacitance)的下電極（low electrode)116。完成上述摻雜製程112後，移除圖案化光 阻層118及120。 如第1D圖所示，依序形成一閘極絕緣層（gate insulation layer)l24及一介電材料層125於上述基板100 上，且覆蓋上述已製作於基板100上的元件。在一實施 例中，上述介電材料層125的材質可以是氮化石夕（silicon nitride)、氮氧化石夕（silicon oxynitride)或其它合適的氛化 材料。而閘極絕緣層124的材質可以是氧化石夕（silicon oxide)。此外，上述介電材料層125的厚度係與後續的 N+摻雜製程的植入能量有關，且較佳之厚度可以是約400 埃（A)，但並不以此為限。 在另一實施例中’也可以先形成閘極絕緣層124、 介電材料層125後，接著，再進行P+摻雜製程，以形成 源/汲極區域114b於主動層114之中。 如第1E圖所示，接著，分別形成閘極電極（gate electrode)130、132及134及上電極136於介電層126、 127、128及129上。在一實施例中，形成例如是鋁/鉬合 金（aluminum/molybdenumalloy)的金屬層於基板 100 上， 0773-A33387TWF;P2007053 10 200915574 接著，形成圖案化光阻層（未顯示）於上述金屬層上，且進 行一過度蝕刻（over etching)製程，同時移除部分金屬層及 部分介電材料層。之後，移除圖案化光阻層，以形成閘 極電極130、132、234及上電極136，以及介電層126、 127 、 128 及 129 。 士 /此外，藉由上述對金屬層的過度蝕刻製程，也可同 守开/成各別具有延伸部（extending portion) 126a、127a及 128a之；丨電層126、127及128，而不需要額外形成遮罩 的步驟。據此，也可以減少製程步驟。在一實施例中， 上述介電層126、127及128之延伸部126a、127a及128a 的長度d較佳可以是介於3〇〇〇埃（A)〜5〇〇〇埃（人)之間。 如第1F圖所示，進行一磷離子的N+摻雜製程138， 以同時形成輕摻雜源/汲極Glght d〇ped drain/s〇urce; ldd) 區域140、144及源/汲極區域142、146。值得注意的是， 由於N+摻雜製程係在形成閘極電極之後進行，使得上述 問極電極130、丨32及134可作為通道區域112a、丨… 及115 a的遮罩。 此外’上述介電層126及128的延伸部126a及128a 也可作為一遮罩，在進rn+摻雜製程時，可減少穿過延 伸部126a及128a的磷離子。因此，在上方覆蓋有延伸 部伽及128a之主動層⑴及U5中的鱗離子濃度會 小於未覆蓋有延伸部126&及128a之主動層112及115 中的兩離子/辰度。據此，依據本發明第一實施例的方式， 可藉由閘極電極及介電層的延伸部作為遮罩，全面性地 0773-A33387TWF；P2〇〇7〇53 11 200915574 ΐ : : 製程，而不需額外形成遮罩的步驟，以同時 凡成輕払雜源/汲極區域及源/汲極區域的製作。 由於，延伸部126^128a可作為遮舉，因此 7雜源/沒極區域140及144的側邊大體上會分 =伸部伽及挪的侧邊。再者，由於介電層的延 “可與間極電極同時形成’而不需要額外的光罩，且 =由已形成之延伸部及閘極電極，其可作為遮罩，可同 時形成輕摻雜源/汲極區域及源/汲區域，亦不需光罩。因 此Μ友據本發明第一實施例所述的方式，可減少至少兩 運光罩數。故，可縮短製作流程及節省成本。 在完成上述步驟後，在驅動區域1〇4會形成一 Ν型 金氧半導體（metal-oxide semic〇nduct〇r; M〇s)元件⑹， f由通道區域U2a、輕摻雜源/汲極區域14〇、源/沒極區 域⑷、、閘極絕緣層124、介電層126及閘極電極13〇所 構成’以及-P型金氧半導體元件164，其由通道區域 H4a '源/汲極區域n4b、閘極絕緣層124、介電層I” 及閘極電極132所構成。同時，在畫素區域1〇6也會形 成-薄膜電晶體166，其由通道區域115 極區域⑷、源/汲極區域146、閘極絕緣層12/雜介^ 28及閘極电極丨34所構成，以及一儲存電容1。 值得一提的是，在上述1^+摻雜製程中，為了可以完 全地遮蔽通道區域114a，P型金氧半導體元件164的間 極乱極132的底部見度較佳係大於其通道區域i j如 的長度L1，使得N+摻雜製程中閘極電極132可完全地遮 0773-A33387TWF；P2〇〇7〇53 12 200915574 敝通道區域U4a。為了上述目的，在通道區域U4a的長 度L1’相似於通道區域112a之長度Li的實施例中，可以 將P型金氧半導體元件164之閘極電極132的底部寬度 L2設計為大於N型金氧半導體元件162之閘極電極 的底邠覓度L2。或者，在閘極電極132的底部寬度L2 相似於閘極電極130之底部寬度L2，的實施例中，也可以 將p型金氧半導體元件164之通道區域u4a的長度u 設計為小於N型金氧半導體元件162之通道區域⑴ 長度L1，。 Η·】口1G圖所不，依序沈積一層間介電層（interlayer nC)148及—保護層（陶i猶職layer)l5G於上述基 板100上’接著，圖案化層間介電層148BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device, and more particularly to a low temperature polycrystalline germanium thin film transistor liquid crystal display device and a method of fabricating the same. [Prior Art] In general, a thin film transistor (TFT) can be classified into an amorphous thin film transistor and a polysilcion thin film transistor. The polycrystalline thin electric crystal system is fabricated using low-temperature polysilicon (LTPS) technology and is quite different from the amorphous austenitic thin film transistor produced by amorphous a-Si technology. Low temperature polycrystalline lithotripe (LTPS) transistors have a large electron mobility (> 20 cm2/Vsec), so LTps transistors have relatively good size and large open porosity (aperture) Rati〇) and lower power ratmg. In addition, the low-temperature polysilicon process can simultaneously produce a driver circuit and a thin film transistor on the same substrate, so that the reliability (10) iabmty) of the display panel can be increased and the manufacturing of the display panel can be reduced. However, 'traditional low-temperature polycrystalline seconds drive circuits and thin film electro-productions require 8 or 9 masks' to make it costly: Ben. In addition, the larger number of masks also results in a longer production time. Fortunately, there is a need for a low temperature process with a reduced number of masks to reduce manufacturing costs. In view of the above, an embodiment of the present invention provides an image display system including a low temperature polysilicon (1〇w_temperature such as ic〇n; LTPS) driving circuit and a thin film transistor extension. It’s like calling TFT. The driving circuit and the thin film transistor comprise: a substrate; an active layer formed on the substrate; a gate insulating layer covering the first active layer, the 'I electrical layer, located on the gate insulating layer, And the dielectric layer has a +I extension, and a gate electrode is formed on the dielectric layer and exposes the extension; the storage capacitor including the upper and lower electrodes is formed on the substrate; a towel formed on the interpole insulating layer, and this contact = storm: a region where the lower electrode is adjacent to the active layer. The above image display system speed=containing a plurality of wires and a halogen electrode, wherein the wire is electrically connected, and the extension portion of the tantalum layer is formed by electrically connecting the halogen electrode to the substrate _ + '甩日日体) The off current (I〇ff) of the thin film transistor. Another embodiment of the present invention provides a method, including providing _low, ☆ kind of image #不 system production, low (five) low, blood eve day driving circuit and thin film transistor. Including: providing a substrate, forming a first method, including the substrate; performing a _ ρ + Μ (four) moving layer and - a second active layer on the second active layer of the film ^ ^ (4) into a source / drain region a dielectric layer of the first-active acoustically-having-extension portion is disposed above the pole electrode == into the first-electrode electrode and the second second-order secondary spear active layer and the 篦__ 茨 ― active layer; And performing 〇773-A33387TWF; P2〇〇7〇53 200915574: N+# miscellaneous process to simultaneously form a lightly doped source/drain region and a source and a drain region in the first active layer. The method for fabricating the image display system further includes forming a plurality of wires on the substrate to electrically connect the driving circuit and the film electric solar cell; and forming a halogen electrode on the substrate, and electrically connecting The thin film transistor. The manner of forming the dielectric layer having the extension portion and the first and second impurity electrodes comprises a deposition-dielectric layer and a metal layer, and then patterning the metal layer to simultaneously form the first and second inter-electrode electrodes and A dielectric layer having an extension. Since the extension of the dielectric layer can be formed simultaneously with the gate electrode without using an additional mask, the number of masks can be reduced. Further, the above-mentioned _electrode and the extension of the dielectric layer can be used as a mask, so that the Ν+doping process can be performed comprehensively without an additional mask, and the light doping can be simultaneously formed in one doping step. The source/drain region and the source/> and the pole region are based on the method for manufacturing the image display system according to the embodiment of the present invention, which can reduce the number of masks and further reduce the manufacturing cost. The y embodiment of the present invention provides a method for fabricating an image display system, which comprises providing a low temperature polycrystalline 11 driving circuit and a thin low temperature polysilicon driving circuit and a thin film transistor manufacturing method, the spoon containing · providing a substrate; Forming a first active layer and a moving dipole I 4c I· w , a π-wang layer on the bauxite plate, forming a dielectric layer having an extension portion above the first main layer, respectively forming a first 1 - the first active layer and the second active and two: thyristor (four) embossing tens of thousands, and the enthalpy - Ν + doping in the first active layer of 5 hai; performing a Ρ + doping process To form: two: lightly doped source/drain region and pole region source / 0773-A33387TWF; P2007053 7 200915574 The dielectric region of the second active layer of the drain region f (4) 1 material has a dielectric boundary: The method of closing the electrodes of the first and second electrodes comprises depositing a layer of two metal layers, and then patterning the metal layer to simultaneously form an open electrode and a dielectric layer having an extension. The method for fabricating the above-mentioned method further includes forming a plurality of wires on the substrate to electrically connect the driving circuit and the thin film transistor; and forming a dummy electrode on the substrate, and electrically connecting the wire Thin film transistor. [Embodiment] Next, a specific embodiment of the present invention and a method of fabricating the same will be described in detail. However, it can be understood that the present invention provides many inventive concepts that can be implemented in a wide variety of fields of application. The embodiments used for the description are merely illustrative of specific embodiments of the present invention and are not intended to limit the scope of the invention. The present invention is described by way of an embodiment of a low temperature polysilicon (LTPS) driving circuit and a thin film transistor (TFT). However, the concept of the present invention can of course also be used to make other integrated circuits. The 1st A_m diagram shows a σ彳 plane view of a low temperature polycrystalline litter circuit and a thin film aa body fabricated according to the first example of this table. The Fig. 2A-2G diagram shows a cross-sectional view of a low temperature polycrystalline litter driving circuit fabricated in accordance with a second embodiment of the present invention. As shown in FIG. 1, a substrate 100 having a buffer layer 102 is formed thereon, and the substrate 1 can be divided into a driving area 1 〇 4 and a halogen region ( Pixd area) 1 〇 6. In one example, the substrate 100 may be a transparent substrate of glass, plastic or other suitable 0773-A33387TWF; P2007053 8 200915574. Next, a semi-conductor layer 108 is over the substrate 100. In the embodiment, the manner of forming the semiconductor layer (10) may be by, for example, a servant γ · & chemical vapor deposition (CVD) method, ice to L accumulation ~ amorphous; The amorphous silicon layer is processed on the substrate 100, and then subjected to a quasi-molecular laser annealing (her annealmg; ela) treatment, so that the amorphous layer can be crystallized into a polycrystalline germanium layer (p〇lysiHc〇nlayer). . As shown in FIG. 1B, the semiconductor layer 108 is patterned, and then a doping process is performed to form a gentry, an n active active layer 112, an active layer 114, and a semi-violated An ancestor layer 115 (a portion of the doped semiconductor 106 that has been doped with an active layer of a semiconductor layer transistor (TFT). In one embodiment, the above doping process ~, .. can also be in the patterned semiconductor layer Before the step. layer). In addition, the 昼115 can also be used as the subsequent film 'only 1'. When the amorphous ruthenium layer is deposited, the doping process, etch & and then laser annealing the amorphous ruthenium layer can be performed simultaneously. Conversion to polycrystalline 矽饴^ Μ I 'repattern this polycrystalline layer. The above doping process can also be referred to as channel coordination and channel doping. As shown in Fig. 1C, a P+ doping process 12 2 ' of boron ions, for example, is formed to form a source/visit k τTM and a source/drain region 114b in the active I 114. In an embodiment, a photoresist material is applied over the substrate 100. Next, the photoresist is patterned to form patterned photoresist layers 118 and 12G. In the driving region 1Q4, the patterned photoresist layer 0773-A33387TWF; P2007053 9 200915574 118 shields the active layer 112, and the patterned photoresist layer 120 shields a portion of the active layer 114 to expose the portion to be doped. In the halogen region 106, the patterned photoresist layer 118 shields a portion of the doped semiconductor layer 115 to expose the portion to be doped. Next, a doping process 122 is performed to form the source/drain region 114b and the channel region 114a, and in the pixel region 106, a lower electrode 116 of storage capacitance is formed. After the doping process 112 is completed, the patterned photoresist layers 118 and 120 are removed. As shown in FIG. 1D, a gate insulation layer 14 and a dielectric material layer 125 are sequentially formed on the substrate 100 and cover the elements fabricated on the substrate 100. In one embodiment, the material of the dielectric material layer 125 may be silicon nitride, silicon oxynitride or other suitable tempering material. The material of the gate insulating layer 124 may be silicon oxide. In addition, the thickness of the dielectric material layer 125 is related to the implantation energy of the subsequent N+ doping process, and the thickness may be about 400 angstroms (A), but not limited thereto. In another embodiment, the gate insulating layer 124 and the dielectric material layer 125 may be formed first, and then a P+ doping process is performed to form the source/drain region 114b in the active layer 114. As shown in FIG. 1E, gate electrodes 130, 132, and 134 and upper electrode 136 are formed on dielectric layers 126, 127, 128, and 129, respectively. In one embodiment, a metal layer such as an aluminum/molybdenumalloy is formed on the substrate 100, 0773-A33387TWF; P2007053 10 200915574, followed by forming a patterned photoresist layer (not shown) on the metal layer. And performing an over etching process while removing portions of the metal layer and a portion of the dielectric material layer. Thereafter, the patterned photoresist layer is removed to form gate electrodes 130, 132, 234 and upper electrode 136, as well as dielectric layers 126, 127, 128 and 129. In addition, by the above-mentioned over-etching process for the metal layer, it is also possible to keep the same/extending portions 126a, 127a and 128a; the electric layers 126, 127 and 128 without An additional step of forming a mask. Accordingly, the process steps can also be reduced. In one embodiment, the lengths d of the extensions 126a, 127a, and 128a of the dielectric layers 126, 127, and 128 may preferably be between 3 Å (A) and 5 Å (A). between. As shown in FIG. 1F, a phosphorus-ion N+ doping process 138 is performed to simultaneously form a lightly doped source/drain Glght d〇ped drain/s〇urce; ldd) regions 140, 144 and source/drain regions. 142, 146. It is noted that since the N+ doping process is performed after the formation of the gate electrode, the above-mentioned interrogating electrode 130, 丨32 and 134 can serve as a mask for the channel regions 112a, 丨... and 115a. Further, the extensions 126a and 128a of the dielectric layers 126 and 128 can also serve as a mask to reduce phosphorus ions passing through the extensions 126a and 128a during the rn+ doping process. Therefore, the concentration of scale ions in the active layers (1) and U5 covered with the extension portion 280a above will be smaller than the two ions/offsets in the active layers 112 and 115 not covered with the extensions 126 & and 128a. Accordingly, according to the first embodiment of the present invention, the extension of the gate electrode and the dielectric layer can be used as a mask, comprehensively 0773-A33387TWF; P2〇〇7〇53 11 200915574 ΐ : : process, There is no need to additionally form a mask to simultaneously produce the light source/drain region and the source/drain region. Since the extensions 126^128a can be used as occlusions, the sides of the 7-source/no-polar regions 140 and 144 are substantially divided into the sides of the extensions. Furthermore, since the extension of the dielectric layer "can be formed simultaneously with the interpole electrode" without the need for an additional mask, and = formed by the extension and the gate electrode, it can be used as a mask to simultaneously form a light blend. The source/drain region and the source/drain region do not need a mask. Therefore, according to the method described in the first embodiment of the present invention, the number of masks can be reduced by at least two masks, thereby shortening the manufacturing process and saving. After completing the above steps, a metal-oxide semi-conductor (M〇s) element (6) is formed in the driving region 1〇4, f is from the channel region U2a, lightly doped source/ The drain region 14A, the source/drain region (4), the gate insulating layer 124, the dielectric layer 126, and the gate electrode 13A constitute 'and a P-type MOS device 164, which is sourced from the channel region H4a' The drain region n4b, the gate insulating layer 124, the dielectric layer I", and the gate electrode 132 are formed. At the same time, a thin film transistor 166 is formed in the pixel region 1〇6, which is composed of a channel region 115 pole region (4), a source/drain region 146, a gate insulating layer 12/a dielectric layer 28, and a gate electrode. 34 is constructed, and a storage capacitor 1 is provided. It is worth mentioning that in the above-mentioned 1^+ doping process, in order to completely shield the channel region 114a, the bottom visibility of the P-type MOS device 164 is preferably greater than the channel region ij. For example, the length L1 is such that the gate electrode 132 in the N+ doping process can completely cover 0773-A33387TWF; P2〇〇7〇53 12 200915574 敝 channel region U4a. For the above purpose, in the embodiment in which the length L1' of the channel region U4a is similar to the length Li of the channel region 112a, the bottom width L2 of the gate electrode 132 of the P-type MOS device 164 can be designed to be larger than the N-type gold oxide. The bottom electrode L2 of the gate electrode of the semiconductor element 162. Alternatively, in the embodiment in which the bottom width L2 of the gate electrode 132 is similar to the bottom width L2 of the gate electrode 130, the length u of the channel region u4a of the p-type MOS device 164 may be designed to be smaller than the N-type gold. The channel region (1) of the oxygen semiconductor element 162 has a length L1. Η 】 口 口 口 口 口 口 口 口 口 口 口 口 口 口 口 口 口 口 口 口 口 口 口 口 口 口 口 口 口 口 口 口 口 口 口 口 口 口 口 口 口 口 口 口 口 口 口 口 口 口 口 口 口 口 口 口
=二―,及152。於層間介電層148及 保護们50之中，且暴露源極/没極區域142、114W 在第1G ®巾，在圖案化層間介 ，及〜各接= 及心在-實施例中 =^^_域142、⑽ 導線，⑽及154c，且電性 == 膜電晶體166與驅動區域104的驅動電路 薄 值得-提的是’在畫素區域1Q 的下電極116係摻雜p型參储存笔谷168 源_物係摻㈣型二物而=^ 0773-A33387TWF;P2007053 13 200915574 接面（PN junction)的現象。在一較佳實施例中，可將接觸 孔152c設置於下電極116及源/沒極區域146之相鄰或鄰 接的位置’且將導線154c填充於接觸孔152c之中，以 導出在此所衍生出的電子與電洞。藉此，可避免PN接面 現象的發生。 如第1H圖所示，形成一平坦層156於基板 接著’圖案化此平坦層156，以形成一開口 15 8。之後， 形成一晝素電極（pixel electr〇de) 160於上述平坦層上，且 經由開口 158,電性連接薄膜電晶體166。在一實施例中， 形成例如是銦錫氧化物（1丁〇)的透明導電層於基板1〇〇， 接著，圖案化此透明導電層，以形成晝素電極16〇。 第1H圖顯示根據本發明之第一實施例之低溫多晶 矽驅動電路及薄膜電晶體的剖面圖。請參閱第丨幵圖，在 驅動區域104,顯示一具有N型及p型之金氧半導體元 件162及164的互補式金氧半導體（c〇_eme_y metal-oxide semiconductor; CM0S)元件驅動電路。上述 n 型金氧半導體元件162包含主㈣112、間極絕緣層 ⑶、具有延伸部心之介電層126、閘極電極13〇,盆 中閘極電極！30位於介電層126上，且暴露延伸部n 而，上述p型金氧半導體元件164包含 U4、源_域收的主動層114、閑極絕緣 =極電8 132,其中閘極電極⑴❸底部寬度大於 區域114的長度。 、 請再參閱第1H圖，在晝素區域1〇6，顯示一薄膜電 0773-A33387TWF;P2OO7O53 14 200915574 ^166及一儲存電容】⑽。上述薄膜電晶體166包含主 層、間極、絕緣層124、具有延伸部128a之介電層128、 ::電：134’其中閘極電極134位於介電層}二，且 二：：咖。上述主動層包含有通道區域"5a、輕 物及源/汲極區域146，其中輕換雜源/ 的側邊大體上分別對齊上= two -, and 152. Between the interlayer dielectric layer 148 and the protector 50, and the exposed source/no-polar regions 142, 114W are in the 1GG towel, between the patterned layers, and the respective connections = and in the embodiment - ^ ^_field 142, (10) wire, (10) and 154c, and electrical == thin film circuit 166 and the drive circuit of the drive region 104 are worthwhile - mention that the lower electrode 116 in the pixel region 1Q is doped with p-type parameters Storage pen 168 source _ system mixed (four) type two things = ^ 0773-A33387TWF; P2007053 13 200915574 PN junction phenomenon. In a preferred embodiment, the contact hole 152c can be disposed at the adjacent or adjacent position of the lower electrode 116 and the source/nothing region 146 and the wire 154c can be filled in the contact hole 152c for export. Derived electrons and holes. Thereby, the occurrence of the PN junction phenomenon can be avoided. As shown in Fig. 1H, a flat layer 156 is formed on the substrate to subsequently pattern the planar layer 156 to form an opening 15 8. Thereafter, a pixel electrode 160 is formed on the planar layer, and the thin film transistor 166 is electrically connected via the opening 158. In one embodiment, a transparent conductive layer such as indium tin oxide (1 butyl) is formed on the substrate 1 and then the transparent conductive layer is patterned to form a halogen electrode 16 〇. Fig. 1H is a cross-sectional view showing a low temperature polysilicon driving circuit and a thin film transistor according to a first embodiment of the present invention. Referring to the second drawing, in the driving region 104, a complementary MOSFET (c〇_eme_y metal-oxide semiconductor; CMOS) device driving circuit having N-type and p-type MOS devices 162 and 164 is shown. The n-type MOS device 162 includes a main (four) 112, an interlayer insulating layer (3), a dielectric layer 126 having an extending portion, a gate electrode 13A, and a gate electrode in the basin! 30 is located on the dielectric layer 126, and exposes the extension portion n, the p-type MOS device 164 includes U4, the source layer of the active layer 114, the idler insulation = the pole electrode 8 132, wherein the gate electrode (1) is at the bottom The width is greater than the length of the region 114. Please refer to Figure 1H again. In the pixel area 1〇6, a thin film electric 0773-A33387TWF; P2OO7O53 14 200915574 ^166 and a storage capacitor] (10) are displayed. The thin film transistor 166 includes a main layer, a via, an insulating layer 124, a dielectric layer 128 having an extension 128a, and a: 134' in which the gate electrode 134 is located in the dielectric layer, and two: The active layer includes a channel region "5a, a light object and a source/drain region 146, wherein the sides of the light-changing source/substrate are substantially aligned respectively
to； * 1H.H a $ 11連接相電晶體166及_電路。上 = ;54c經由一接觸孔同時接觸儲存電容 極U6嫌及極區域。再者，一晝素電極16〇電性連接 潯膜電晶體166 ’且對應於儲存電容168。 可寻1主罢意的是’由於介電層的延伸部在摻雜製程中 :二1 ’且介電層的延伸部可與間極電極同時形 ==此，根據本發明第—實施例的方式，可減少製程 的光罩數’進而降低製作成本。此外，上述介電層的延 伸部同時也可以降低薄膜電晶體的關閉電流(I〇ff)。 第2A-2G圖顯示根據本發明第二實施例之製作 低溫多晶料動電路及薄膜電晶體的剖面圖。相較 中，p+摻雜製程係在形成閘極 "極及N+摻雜製程之後進行。因此，相似元件的材質及 =了式可以參閱上述第一實施例的說明，在此並不再 如第2A圖所示，接徂 L …丄、丄 基板200,且此基板2。。‘分：動^^層202的 刀為一驅動區域2〇4及—書素 〇V73-A333S7TWF;P2007053 200915574 區域2〇6。接著，形成主動層208及210，以及已摻雜之 半導體層212於上述基板2〇〇上方。 、，如第2B圖所不，依序形成閘極絕緣層214、介電材 料層216於上述基板上方，且覆蓋上述已製作於基 板200上的元件。接箸，如第2c圖所示，形成間極電極 218 220及222’以及各別具有延伸部226&、228&及 ^介電層226、228及230於基板200上。相似於第—實 %例，首先，沈積一金屬層於介電材料層215上，接著， 形成圖案化光阻材料（未顯示），且進行—過度㈣製程， 以同時形成閘極電極218、22〇及222，以及各別具有延 伸部226a、228a及230a之介電層226、228及23〇，而 不需額外的遮罩步驟。在一實施例中，上述延伸部2心、 228a及230a的長度d較佳可以是介於3〇〇〇埃〜5〇〇〇埃 之間。此外，藉由上述步驟，也會形成一儲存電容於基 板200上，且此儲存電容包含有上電極224及下電極 212b(如第2D圖所示）。由於，介電層的延伸部可與問極 電極同時形成，而不需額外的光罩，因此，也可以減少 製程光罩數，進而節省製作成本。 在第2D圖中’接著，藉由上述閘極電極218、222 及延伸部226a、230a所構成的遮罩，進行一 N+摻雜製 程2 3 2，以同時形成輕摻雜源/汲極區域2 3 4及源/汲極區 域236，以及輕摻雜源/汲極區域238及源/汲極區域24〇， 而不需額外的遮罩步驟。值得注意的是，由於延伸部226a 及230a可作為遮罩，因此，上述輕摻雜源/汲極區域幻4 〇773-A33387TWF;P2007053 16 200915574 及238的侧邊係大體上對齊延伸部226a及230a的侧邊。 如第2E圖所示，進行一 P+摻雜製程244，以形成 源/汲極區域246。在一實施例中，覆蓋一光阻材料，且 圖案化此光阻材料，形成圖案化光阻層242及243，以曝 露欲摻雜的部分。接著，進行P+摻雜製程244，以形成 源/汲極區域246。值得注意的是，由於上述N+摻雜製程 係以全面性地摻雜，因此，在P+摻雜製程時，其掺雜濃 度較佳係大於上述N+摻雜製程時的摻雜濃度，以將原本 為N+的摻雜區域210b轉變為P+的源/汲極區域246。 如第2F圖所示，接著，依序形成一層間介電層248 及一保護層250於基板200上，接著，圖案化上述層間 介電層248及保護層250，以形成接觸孔252a、252b及 252c於層間介電層248及保護層250之中。形成導線 254a、254b及254c於基板200上，且分別延伸於上述接 觸孔252a、252b及252c之中，以電性連接薄膜電晶體 266與包含有N型金氧半導體元件262及P型金氧半導 體元件264的互補式金氧半導體元件驅動電路。值得一 提的是，上述接觸孔252c會暴露源/汲極區域240與下電 極212b鄰接的區域，使得後續形成的導線254c會同時 接觸源/汲極區域240及下電極212b。 如第 2G圖所示，形成一平坦層（overcoating layer)256於基板200上，接著，圖案化此平坦層256， 以形成一開口（〇pening)258。之後，形成一晝素電極260 對應於儲存電容268，且電性連接薄膜電晶體266。 0773-A33387TWF;P2007053 17 200915574 第2G圖顯示根據本發明第二實施例之低溫多晶矽 驅動電路及薄膜電晶體的剖面圖。請參閱第2G圖，在驅 動區域204,顯示一具有N型金氧半導體元件262及P 型金氧半導體元件264的互補式金氧半導體元件驅動電 路。上述N型金氧半導體元件262包含主動層208、閘 極絕緣層214、具有延伸部226a之介電層226、閘極電 極218，其中閘極電極218位於介電層226上，且暴露延 伸部226a。而，P型金氧半導體元件264包含主動層210、 閘極絕緣層214及閘極電極2 2 0。 請再參閱第2G圖，在晝素區域206，顯示一薄膜電 晶體266及一儲存電容268。上述薄膜電晶體266包含具 有通道區域212a、輕摻雜源/汲極區域238及源/汲極區域 240的主動層、閘極絕緣層214、具有延伸部230a之介 電層230及閘極電極222，其中閘極電極222設置於介電 層230上，暴露延伸部230a，且輕掺雜源/没極區域238 的側邊大體上對齊上述延伸部230a的侧邊。而，儲存電 容268係位於基板200上，且包含一上電極224及一下 電極212b。又如第2G圖所示，導線254a、254b及254c 形成於基板100上方，且電性連接薄膜電晶體266及驅 動電路。一畫素電極260對應上述儲存電容268，且電性 連接薄膜電晶體266。值得一提的是，在晝素區域206， 導線254c經由一接觸孔同時接觸儲存電容268之下電極 212b及薄膜電晶體266之源/汲極區域240。 第3圖顯示根據本發明實施例之製作低溫多晶矽驅 0773-A33387TWF;P2007053 18 200915574To; * 1H.H a $ 11 is connected to phase transistor 166 and _ circuit. Upper = ; 54c simultaneously contacts the storage capacitor pole U6 via a contact hole. Furthermore, the monolayer electrode 16 is electrically connected to the diaphragm transistor 166' and corresponds to the storage capacitor 168. What can be found is that 'because the extension of the dielectric layer is in the doping process: two 1 ' and the extension of the dielectric layer can be simultaneously formed with the interpole electrode == this, according to the first embodiment of the invention The way to reduce the number of masks in the process' and thus reduce the cost of production. Further, the extension of the dielectric layer described above can also reduce the off current (I ff) of the thin film transistor. Fig. 2A-2G is a cross-sectional view showing the fabrication of a low temperature polycrystalline material circuit and a thin film transistor in accordance with a second embodiment of the present invention. In contrast, the p+ doping process is performed after forming the gate "pole and N+ doping process. Therefore, the material of the similar element and the formula can be referred to the description of the first embodiment described above, and the substrate 2 is not connected to the substrate 200 as shown in Fig. 2A. . ‘Minute: The tool of the layer 202 is a driving area 2〇4 and a book 〇V73-A333S7TWF; P2007053 200915574 area 2〇6. Next, active layers 208 and 210 are formed, and the doped semiconductor layer 212 is over the substrate 2A. As shown in FIG. 2B, a gate insulating layer 214 and a dielectric material layer 216 are sequentially formed over the substrate and cover the elements which have been fabricated on the substrate 200. Next, as shown in Fig. 2c, inter-electrode electrodes 218 220 and 222' are formed and each has extensions 226 & 228 & and dielectric layers 226, 228 and 230 on substrate 200. Similar to the first embodiment, first, a metal layer is deposited on the dielectric material layer 215, then a patterned photoresist material (not shown) is formed, and an over-four process is performed to simultaneously form the gate electrode 218. 22 and 222, and dielectric layers 226, 228, and 23, each having extensions 226a, 228a, and 230a, without the need for an additional masking step. In one embodiment, the length d of the extensions 2, 228a, and 230a may preferably be between 3 Å and 5 Å. In addition, by the above steps, a storage capacitor is also formed on the substrate 200, and the storage capacitor includes an upper electrode 224 and a lower electrode 212b (as shown in FIG. 2D). Since the extension of the dielectric layer can be formed simultaneously with the interrogating electrode without an additional mask, the number of process masks can also be reduced, thereby saving manufacturing costs. In FIG. 2D, an N+ doping process 2 3 2 is performed by the masks formed by the gate electrodes 218 and 222 and the extension portions 226a and 230a to simultaneously form a lightly doped source/drain region. 2 3 4 and source/drain regions 236, as well as lightly doped source/drain regions 238 and source/drain regions 24, without additional masking steps. It should be noted that since the extensions 226a and 230a can serve as a mask, the lightly doped source/drain region of the above-mentioned lightly doped source/drain region is substantially aligned with the extension portion 226a and the sides of the P2007053 16 200915574 and 238 are The side of 230a. As shown in Figure 2E, a P+ doping process 244 is performed to form source/drain regions 246. In one embodiment, a photoresist material is overlaid and the photoresist material is patterned to form patterned photoresist layers 242 and 243 to expose portions to be doped. Next, a P+ doping process 244 is performed to form source/drain regions 246. It is worth noting that since the above N+ doping process is fully doped, the doping concentration in the P+ doping process is preferably greater than the doping concentration in the above N+ doping process, so that the original The doped region 210b for N+ is converted to the source/drain region 246 of P+. As shown in FIG. 2F, an interlayer dielectric layer 248 and a protective layer 250 are sequentially formed on the substrate 200. Then, the interlayer dielectric layer 248 and the protective layer 250 are patterned to form contact holes 252a and 252b. And 252c are among the interlayer dielectric layer 248 and the protective layer 250. The wires 254a, 254b, and 254c are formed on the substrate 200 and extend through the contact holes 252a, 252b, and 252c, respectively, to electrically connect the thin film transistor 266 and the N-type MOS device 262 and the P-type gold oxide. A complementary MOS device driving circuit of the semiconductor element 264. It is worth mentioning that the contact hole 252c exposes a region where the source/drain region 240 is adjacent to the lower electrode 212b, so that the subsequently formed wire 254c contacts the source/drain region 240 and the lower electrode 212b at the same time. As shown in FIG. 2G, an overcoating layer 256 is formed on the substrate 200, and then the flat layer 256 is patterned to form a via 258. Thereafter, a halogen electrode 260 is formed corresponding to the storage capacitor 268 and electrically connected to the thin film transistor 266. 0773-A33387TWF; P2007053 17 200915574 Fig. 2G is a cross-sectional view showing a low temperature polysilicon driving circuit and a thin film transistor according to a second embodiment of the present invention. Referring to Fig. 2G, in the driving region 204, a complementary MOS device driving circuit having an N-type MOS device 262 and a P-type MOS device 264 is shown. The N-type MOS device 262 includes an active layer 208, a gate insulating layer 214, a dielectric layer 226 having an extension 226a, and a gate electrode 218, wherein the gate electrode 218 is on the dielectric layer 226 and the extension is exposed. 226a. The P-type MOS device 264 includes an active layer 210, a gate insulating layer 214, and a gate electrode 220. Referring again to FIG. 2G, a thin film transistor 266 and a storage capacitor 268 are shown in the pixel region 206. The thin film transistor 266 includes an active layer having a channel region 212a, a lightly doped source/drain region 238 and a source/drain region 240, a gate insulating layer 214, a dielectric layer 230 having an extension 230a, and a gate electrode 222, wherein the gate electrode 222 is disposed on the dielectric layer 230 to expose the extension portion 230a, and the side edges of the lightly doped source/no-polar region 238 are substantially aligned with the sides of the extension portion 230a. The storage capacitor 268 is located on the substrate 200 and includes an upper electrode 224 and a lower electrode 212b. Further, as shown in Fig. 2G, wires 254a, 254b, and 254c are formed over the substrate 100, and are electrically connected to the thin film transistor 266 and the driving circuit. The pixel electrode 260 corresponds to the storage capacitor 268 and is electrically connected to the thin film transistor 266. It is worth mentioning that in the halogen region 206, the wire 254c simultaneously contacts the electrode 212b under the storage capacitor 268 and the source/drain region 240 of the thin film transistor 266 via a contact hole. Figure 3 shows the fabrication of a low temperature polysilicon flooding 0773-A33387TWF according to an embodiment of the present invention; P2007053 18 200915574
動電路及薄膜電晶體的流程圖。在第3圖中，提供一基 板一且形纟1動層於基板上(光罩”’如步驟S5及S10 所不。接著，進行一局部性地p+摻雜製程（光罩2),以形 成P型金氧半導體元件的源/汲極區域，如步驟S15所 Γ形成一間極電極於基板上（光罩3)，如步驟S20所示。 = N+摻雜製程(不需光罩)，以同時形成N ’ ¥ —兀件及薄膜電晶體的輕摻雜源/汲極區域及 ==rs25所示。沈積-保護層於基板上， /、 呆4層，以形成複數個接觸孔（光罩4)，如步 示。形成複數個導線於基板上（光罩5)，以電性 ==及薄膜電晶體，如步驟s35所示。覆蓋一 門口-曰於^上，且圖案化此平坦層（光$ 6),以形成一 带性連1 4〇所示。之後，形成—晝素電極（光罩1)， •生連接㈣電晶體，如步驟％所示。 極區= 丄::雜製程時，可同時製作輕摻雜源/没 可、、志^ 區域’而不需要額外形成遮罩。因此， 在第所"^的光罩數，進而降低製程成本。此外， 步驟S15也可以在步驟s2。及S25之後進 例揭干的；：轭例所揭示。由此可知’根據本發明實施 驅動電路僅需1道光罩，即可製作低溫多晶石夕的 助私路及溥骐電晶體。 此影二圖f示一種影像顯示系統300的示意圖，其中 動電路統则係使用包含本發明之低溫多晶石夕驅 /膜電晶體的顯示面板310，且此顯示面板310 19 1 73-A33387TWF；P2〇〇7〇53 200915574 可以是電子裝置的一部分構件。如第4圖所示，上述影 像顯示系統300包含顯示面板310及一與之耦接的控制 單元320，以傳輸訊號至顯示面板310，使得控制顯示面 板顯示影像。上述影像顯示系統300可以是行動電話 (mobile phone)、數位相機（digital camera)、個人資料助理 (personal digital assistant; PDA)、筆記型電腦（notebook computer)、桌上型電腦（desktop computer)、電視、車用 顯示器、全球定位系統（GPS)、航空用顯示器或可攜式數 位多功能光碟播放機等的電子裝置。 雖然本發明已以較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之 精神和範圍内，當可作此許之更動與潤飾，因此本發明 之保護範圍當視後附之申請專利範圍所界定為準。 【圖式簡單說明】 第1A-1H圖顯示本發明第一實施例之製作低溫多晶 ^ 矽驅動電路及薄膜電晶體的剖面圖； 第2A-2G圖顯示本發明第二實施例之製作低溫多晶 矽驅動電路及薄膜電晶體的剖面圖； 弟3圖顯不本發明貫施例之製作低溫多晶發驅動電 路及薄膜電晶體的流程圖；以及 第4圖顯示一種影像顯示系統的示意圖，其中此影 像顯示系統係使用包含本發明實施例之低溫多晶矽驅動 電路及薄膜電晶體的顯示面板。 0773-A33387TWF;P2007053 20 200915574 【主要元件符號說明】 100〜基板； 104〜驅動區域； 108〜半導體層； 112〜主動層； 114〜主動層； 114b〜源/汲極區域； 115a〜通道區域； 118〜圖案化光阻層； 122〜摻雜製程； 125〜介電材料層； 126a〜延伸部； 127a〜延伸部； 128a〜延伸部； 13 0〜閘極電極； 13 4〜閘極電極； 138〜摻雜製程； 142〜源/没極區域； 146〜源/没極區域； 150〜保護層； 152b〜接觸孔； 154a〜導線； 154c〜導線； 10 2〜緩衝層； 106〜晝素區域； 110〜摻雜製程； 112a〜通道區域； 114a〜通道區域； 115〜摻雜之半導體層； 116〜下電極； 120〜圖案化光阻層； 124〜閘極絕緣層； 126〜介電層； 127〜介電層； 128〜介電層； 129〜介電層； 132〜閘極電極； 136〜上電極； 140〜輕摻雜源/汲極區域； 144〜輕摻雜源/汲極區域； 148〜層間介電層； 15 2 a〜接觸孔； 15 2c〜接觸孔； 1Mb〜導線； 156〜平坦層； 0773-A33387TWF;P2007053 200915574 158〜開口； 162〜N型金氧半導體元件 164〜P型金氧半導體元件 16 6〜薄膜電晶體， 2 00〜基板； 204〜驅動區域； 208〜主動層； 210〜主動層； 210b〜摻雜區域； 212a〜通道區域； 214〜閘極絕緣層， 218〜閘極電極； 2 2 2〜閘極電極， 226〜介電層； 228〜介電層； 230〜介電層； 232〜摻雜製程； 236〜源/没極區域； 2 4 0〜源/>及極區域， 243〜光阻材料； 2 4 6〜源/>及極區域， 250〜保護層； 2 5 2b〜接觸孔； 254a〜導線； 16 0〜晝素電極， 168〜儲存電容； 202〜緩衝層； 206〜晝素區域； 208a〜通道區域； 210a〜通道區域； 212〜摻雜之半導體層； 212b〜下電極； 216〜介電材料， 2 20〜閘極電極， 224〜上電極； 226a〜延伸部； 228a〜延伸部； 230a〜延伸部； 23 4〜輕摻雜源/汲極區域 23 8〜輕摻雜源/没區域； 242〜光阻材料； 244〜摻雜製程； 248〜層間介電層； 252a〜接觸孔； 252c〜接觸孔； 254b〜導線； 0773-A33387TWF;P2007053 22 200915574 254c〜導線； 256〜平坦層； 25 8〜開口； 260〜晝素電極 262〜N型金氧半導體元件； 264〜P型金氧半導體元件； 266〜薄膜電晶體； 268〜儲存電容 300〜影像顯示系統； 320〜控制單元。 ; 3 10〜顯示面板 0773-A33387TWF;P2007053 23Flow chart of moving circuit and thin film transistor. In Fig. 3, a substrate is provided and the movable layer is formed on the substrate (the mask" as in steps S5 and S10. Then, a partial p+ doping process (mask 2) is performed to Forming a source/drain region of the P-type MOS device, and forming a pole electrode on the substrate (mask 3) as shown in step S15, as shown in step S20. = N+ doping process (no mask required) To form a lightly doped source/drain region of N'¥-兀 and thin film transistors and == rs25 at the same time. The deposition-protective layer is on the substrate, and 4 layers are left to form a plurality of contact holes. (Photomask 4), as shown, forming a plurality of wires on the substrate (mask 5), with electrical == and thin film transistors, as shown in step s35. Covering a door-to-door and pattern This flat layer (light $6) is formed to form a ribbon connection. Then, a halogen element (photomask 1) is formed, and a (four) transistor is formed, as shown in step %.丄:: When making a miscellaneous process, you can make a lightly doped source/no, a ^ area, without the need for additional masks. Therefore, the number of masks in the first " In addition, step S15 can also be disclosed in steps s2 and S25; yoke example is disclosed. It can be seen that 'the driving circuit according to the present invention requires only one mask to fabricate low temperature polycrystalline. Shi Xi's self-help road and electric crystal. This picture shows a schematic diagram of an image display system 300, wherein the moving circuit system uses a display panel comprising the low-temperature polycrystalline slab/membrane transistor of the present invention. 310, and the display panel 310 19 1 73-A33387TWF; P2〇〇7〇53 200915574 may be a part of the electronic device. As shown in FIG. 4, the image display system 300 includes the display panel 310 and is coupled thereto. The control unit 320 transmits a signal to the display panel 310 to control the display panel to display an image. The image display system 300 can be a mobile phone, a digital camera, a personal digital assistant (PDA). ), notebook computer, desktop computer, television, car display, global positioning system (GPS), aviation display An electronic device such as a portable digital versatile disc player, etc. Although the invention has been disclosed in the preferred embodiments as above, it is not intended to limit the invention, and those skilled in the art can devise without departing from the spirit of the invention. The scope of protection of the present invention is defined by the scope of the appended claims. [FIG. 1A-1H shows the first embodiment of the present invention. FIG. 2A-2G is a cross-sectional view showing a low temperature polysilicon driving circuit and a thin film transistor according to a second embodiment of the present invention; FIG. 3 is a schematic view showing a low temperature polycrystalline germanium driving circuit and a thin film transistor; A flowchart of a low temperature polycrystalline driving circuit and a thin film transistor produced by the present invention; and FIG. 4 is a schematic diagram of an image display system using a low temperature polysilicon driving circuit including the embodiment of the present invention and A display panel of a thin film transistor. 0773-A33387TWF;P2007053 20 200915574 [Description of main components] 100~substrate; 104~drive area; 108~semiconductor layer; 112~active layer; 114~active layer; 114b~source/drain region; 115a~channel region; 118~ patterned photoresist layer; 122~ doping process; 125~ dielectric material layer; 126a~ extension; 127a~ extension; 128a~ extension; 13 0~ gate electrode; 13 4~ gate electrode; 138~ doping process; 142~ source/no-polar region; 146~ source/no-polar region; 150~ protective layer; 152b~ contact hole; 154a~ wire; 154c~ wire; 10 2~ buffer layer; Area; 110~doping process; 112a~channel region; 114a~channel region; 115~doped semiconductor layer; 116~lower electrode; 120~patterned photoresist layer; 124~gate insulating layer; 126~dielectric Layer; 127~dielectric layer; 128~dielectric layer; 129~dielectric layer; 132~gate electrode; 136~upper electrode; 140~lightly doped source/drain region; 144~lightly doped source/汲Polar region; 148~ interlayer dielectric layer; 15 2 a~ contact hole; 15 2c~ Contact hole; 1Mb~ wire; 156~ flat layer; 0773-A33387TWF; P2007053 200915574 158~ opening; 162~N type MOS device 164~P type MOS device 16 6~ thin film transistor, 2 00~ substrate; 204~ drive region; 208~active layer; 210~ active layer; 210b~ doped region; 212a~channel region; 214~ gate insulating layer, 218~gate electrode; 2 2 2~gate electrode, 226~ Electrical layer; 228~dielectric layer; 230~dielectric layer; 232~doping process; 236~source/nothing area; 2 4 0~source/> and polar region, 243~ photoresist material; 2 4 6 ~ source / > and pole region, 250 ~ protective layer; 2 5 2b ~ contact hole; 254a ~ wire; 16 0 ~ halogen electrode, 168 ~ storage capacitor; 202 ~ buffer layer; 206 ~ halogen region; 208a ~ Channel region; 210a~channel region; 212~ doped semiconductor layer; 212b~lower electrode; 216~dielectric material, 2 20~gate electrode, 224~upper electrode; 226a~extension; 228a~extension; 230a ~ extension; 23 4 ~ lightly doped source / drain region 23 8 ~ lightly doped source / no region 242~ photoresist material; 244~ doping process; 248~ interlayer dielectric layer; 252a~ contact hole; 252c~ contact hole; 254b~ wire; 0773-A33387TWF; P2007053 22 200915574 254c~ wire; 256~ flat layer; 8 ~ opening; 260 ~ 昼 电极 electrode 262 ~ N type MOS device; 264 ~ P type MOS device; 266 ~ thin film transistor; 268 ~ storage capacitor 300 ~ image display system; 320 ~ control unit. ; 3 10 ~ display panel 0773-A33387TWF; P2007053 23