CN111244104A - SONOS memory and manufacturing method thereof - Google Patents
SONOS memory and manufacturing method thereof Download PDFInfo
- Publication number
- CN111244104A CN111244104A CN202010231443.7A CN202010231443A CN111244104A CN 111244104 A CN111244104 A CN 111244104A CN 202010231443 A CN202010231443 A CN 202010231443A CN 111244104 A CN111244104 A CN 111244104A
- Authority
- CN
- China
- Prior art keywords
- layer
- semiconductor substrate
- gate
- area
- selection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/50—EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
Abstract
The invention provides an SONOS memory and a manufacturing method thereof. The manufacturing method of the SONOS memory comprises the steps of providing a semiconductor substrate, etching an ONO layer, a gate oxide layer and a gate material layer which are sequentially formed on the semiconductor substrate to obtain a storage tube gate lamination layer and a selection tube gate lamination layer, then forming side walls on the side faces of the gate lamination layers, forming an epitaxial layer on the exposed surface of the semiconductor substrate, and then forming metal silicide layers on the surface of the epitaxial layer and the upper surfaces of the storage tube gate lamination layer and the selection tube gate lamination layer. Because the metal silicide layer is formed on the epitaxial layer and is not at the same height with the channel region under each grid laminated layer, the electric leakage of the channel region of the memory caused by the extension of the metal silicide can be avoided, the problem of memory failure caused by the electric leakage interference of the channel region can be avoided, and the reliability and the production yield of the SONOS memory can be improved. The invention also provides the SONOS memory.
Description
Technical Field
The invention relates to the field of semiconductors, in particular to an SONOS memory and a manufacturing method thereof.
Background
Flash memory (Flash memory) is a non-volatile memory developed based on erasable programmable read-only memory (EPROM) and electrically erasable programmable read-only memory (EEPROM), has the characteristics of low price, relatively simple process, and convenient and rapid multiple erasing and writing, and has been widely used in the field of storage since the past. However, the flash memory with the floating gate structure needs high-voltage operation in the processes of reading, writing and erasing, while the Complementary Metal Oxide Semiconductor (CMOS) does not need high-voltage operation, and the flash memory is a double-layer polysilicon structure with a floating gate and a control gate, and the CMOS is a single-layer polysilicon structure, so that the integration difficulty of the flash memory and the CMOS device is large and the process is complex. The SONOS (Silicon-Oxide-Nitride-Oxide-Silicon) technology can be well compatible with the CMOS process, only the SONOS memory is embedded on the basis of a logic platform, the operating voltage of the SONOS memory is low, the cost is low, and the SONOS memory is extremely competitive in manufacturing, using and cost.
Fig. 1 is a cross-sectional view of a SONOS memory device in the prior art. As shown in fig. 1, the SONOS memory includes a semiconductor substrate 101, a surface of the semiconductor substrate 101 includes a memory region 101a, a selection region 101b, and an inter-node region 101c located between the memory region 101a and the selection region 101b, a memory gate stack including an ONO (Oxide-Nitride-Oxide) layer 102 and a first gate material layer 104a is formed on the surface of the memory region 101a, a selection gate stack including a gate Oxide (IO gate Oxide)103 and a second gate material layer 104b is formed on the selection region 101b, and a metal Silicide layer (Silicide)106 is formed on the inter-node region 101 c. In the manufacturing process of the SONOS memory, since the ONO layer 102 in the memory gate stack and the gate oxide layer 103 in the select gate stack are separately formed through multiple processes, including multiple surface cleaning and etching processes, silicon on the semiconductor substrate surface of the select area 101b is consumed, so that the semiconductor substrate surface of the select area 101b is slightly lower than the semiconductor substrate surface of the memory area 101a, i.e., the uneven area of the semiconductor substrate surface of the internode area 101c, and a step shape exists. The inventor researches and discovers that due to uneven surface of the internode area, such as black circles in fig. 2a and fig. 2b, metal Silicide layer formed on the internode area is easy to generate metal Silicide extension (Silicide spiking), that is, the metal Silicide is easy to extend to the channel area under the memory tube gate stack and the select tube gate stack, PN junction formed at the edge of the channel area is damaged, so that leakage of the channel area is increased, the SONOS memory can be failed due to leakage interference, reliability of the SONOS memory is reduced, and production yield can be affected.
Disclosure of Invention
The invention provides an SONOS memory and a manufacturing method thereof, which aim to solve the problems that the drain current of a channel region of the SONOS memory is increased and the SONOS memory fails due to the drain current interference caused by the extension of metal silicide on an internode region.
In order to solve the above problems, an aspect of the present invention provides a method for manufacturing a SONOS memory, where the method for manufacturing a SONOS memory includes:
providing a semiconductor substrate, wherein the surface of the semiconductor substrate comprises a storage tube area, a selection tube area and an internode area positioned between the storage tube area and the selection tube area, an ONO layer is formed on the surface of the semiconductor substrate in the storage tube area, a gate oxide layer is formed on the surface of the semiconductor substrate in the selection tube area, the ONO layer and the gate oxide layer are connected in the internode area, a gate material layer is also formed on the surface of the semiconductor substrate, and the gate material layer covers the surfaces of the ONO layer and the gate oxide layer;
performing an etching process to etch the gate material layer, the ONO layer and the gate oxide layer until the surface of the semiconductor substrate is exposed, obtaining a storage tube gate stack in the storage tube area and a selection tube gate stack in the selection tube area;
forming side walls on the side surfaces of the storage tube grid electrode lamination and the selection tube grid electrode lamination;
performing an epitaxial process, and forming an epitaxial layer on the exposed surface of the semiconductor substrate; and
and performing a silicide process, and forming metal silicide layers on the surface of the epitaxial layer and the upper surfaces of the storage tube gate stack and the selection tube gate stack.
Optionally, the method for manufacturing the SONOS memory further includes:
before the etching process is executed, forming a hard mask layer on the surface of the grid material layer, and carrying out graphical processing on the hard mask layer; and
and after the epitaxial process is executed and before the silicide process is executed, removing the hard mask layer on the surfaces of the storage tube grid laminated layer and the selection tube grid laminated layer.
Optionally, after the silicide process is performed, the metal silicide layer is located on the upper surfaces of the gate material layers in the epitaxial layer, the storage tube gate stack and the selection tube gate stack.
Optionally, after the etching process is performed and before the side wall is formed, the method for manufacturing the SONOS memory further includes:
and performing ion implantation to form lightly doped ion implantation regions in the semiconductor substrate at two sides of the storage tube gate stack and the selection tube gate stack.
Optionally, the thickness of the epitaxial layer is 35nm to 55 nm.
Optionally, the step of performing the silicide process, and forming a metal silicide layer on the surface of the epitaxial layer and the upper surfaces of the storage tube gate stack and the selection tube gate stack includes:
depositing a patterned protective layer on the semiconductor substrate, wherein the protective layer exposes the surface of the epitaxial layer and the upper surfaces of the storage tube gate stack and the selection tube gate stack;
forming a metal material layer on the semiconductor substrate;
performing an annealing process to form the metal silicide layer; and
and removing the residual metal material layer.
Optionally, the protective layer includes a silicon oxide layer and a silicon nitride layer formed by sequentially overlapping.
Optionally, the hard mask layer is a silicon oxide layer or a silicon nitride layer.
Optionally, the metal silicide layer includes one or a combination of two or more of NiSi, TiSi, CoSi, and WSi.
Another aspect of the present invention also provides a SONOS memory device, including:
the semiconductor substrate comprises a memory area, a selection area and an internode area positioned between the memory area and the selection area;
the storage tube gate structure is positioned in the storage tube area and comprises an ONO layer, a first gate material layer and a side wall, wherein the ONO layer and the first gate material layer are sequentially formed on the surface of the semiconductor substrate in an overlapping mode, and the side wall covers the side surfaces of the ONO layer and the first gate material layer;
the grid structure of the selection tube is positioned in the selection tube area and comprises a grid oxide layer and a second grid material layer which are sequentially formed on the surface of the semiconductor substrate in an overlapping mode, and a side wall covering the side surfaces of the grid oxide layer and the second grid material layer;
the epitaxial layer is positioned in a gap between the storage tube grid structure and the selection tube grid structure and covers the surface of the semiconductor substrate in the internode area; and
and the metal silicide layer covers the surface of the epitaxial layer and the surfaces of the first grid material layer and the second grid material layer.
The manufacturing method of the SONOS memory comprises the steps of forming an epitaxial layer on the surface of a semiconductor substrate which is not covered by the storage tube grid laminated layer, the selection tube grid laminated layer and the side wall, covering the surface of the semiconductor substrate in the internode area with the epitaxial layer, and forming a metal silicide layer on the surface of the epitaxial layer. Since the epitaxial layer is formed on the surface of the semiconductor substrate, the upper surface of the epitaxial layer is higher than the surface of the semiconductor substrate, the metal silicide layer is formed on the epitaxial layer to make the metal silicide layer higher than the surface of the semiconductor substrate, because the channel regions under the gate stacks of the storage tube and the selection tube are positioned on the surface of the semiconductor substrate and in the lower region, the metal silicide layer and the channel region are not at the same height, and at the same time, because PN junction is formed at the edge of the channel region, when the metal silicide layer is not at the same height with the channel region, even if the metal silicide layer is expanded, the PN junction at the edge of the channel region can not be damaged, the problem of electric leakage of the memory channel region caused by the expansion of the metal silicide can be effectively avoided, therefore, the memory failure caused by the leakage interference of the channel region can be avoided, and the reliability and the production yield of the SONOS memory can be improved.
The invention also provides an SONOS memory, wherein an epitaxial layer of the SONOS memory is positioned in a gap between a storage tube gate structure and a selection tube gate structure, and the epitaxial layer covers the surface of a semiconductor substrate of the internode region, so that the surface of the epitaxial layer is higher than the surface of the semiconductor substrate, and meanwhile, a metal silicide layer covers the surface of the epitaxial layer, so that the metal silicide layer is higher than the surface of the semiconductor substrate, and a channel region under the storage tube gate structure and the selection tube gate structure is positioned below the surface of the semiconductor substrate, so that the metal silicide layer and the channel region are not at the same height and are higher than the channel region, and the leakage of the channel region caused by the extension of the metal silicide can be avoided, thereby avoiding the memory failure caused by the leakage interference of the channel region, and improving the reliability and the production yield of the SONOS memory.
Drawings
Fig. 1 is a cross-sectional view of a SONOS memory device in the prior art.
Fig. 2a and 2b are cross-sectional SEM images of the metal silicide layer in the SONOS memory inter-node region of fig. 1 at different magnifications.
Fig. 3a to 3d are schematic cross-sectional views of the SONOS memory device of fig. 1 during a manufacturing process.
Fig. 4 is a flowchart of a method for fabricating a SONOS memory device according to an embodiment of the invention.
Fig. 5a to 5f are schematic cross-sectional views of a SONOS memory device in a manufacturing process according to an embodiment of the invention.
Description of reference numerals:
101-a semiconductor substrate; 101 a-memory zone area; 101 b-select tube region; 101 c-internode region; 102-an ONO layer; 103-a gate oxide layer; 104-a layer of gate material; 104 a-a first gate material layer; 104 b-a second gate material layer; 105-a side wall; 106-metal silicon compound; 107-hard mask layer; 108-an epitaxial layer; 109-storage tube gate stack; 110-select tube gate stack.
Detailed Description
The SONOS memory and the method for fabricating the same according to the present invention will be described in detail with reference to the accompanying drawings and embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is provided solely for the purpose of facilitating and distinctly claiming the embodiments of the present invention. For the sake of clarity, in all the drawings for assisting the description of the embodiments of the present invention, the same components are denoted by the same reference numerals in principle, and the duplicated description thereof is omitted.
It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on, adjacent to, connected or coupled to the other elements or layers or intervening elements or layers may be present. It should be further understood that the terms "first," "second," "third," and the like in the description are used for distinguishing between various components, elements, steps, and the like, and are not intended to imply a logical or sequential relationship between various components, elements, steps, or the like, unless otherwise indicated or indicated. It must be noted that, as used in the specification and the appended claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. For example, reference to "a step" or "an apparatus" means a reference to one or more steps or apparatuses and may include sub-steps as well as sub-apparatuses. All conjunctions used should be understood in the broadest sense. And, the word "or" should be understood to have the definition of a logical "or" rather than the definition of a logical "exclusive or" unless the context clearly dictates otherwise.
Fig. 3a to 3d are schematic cross-sectional views of the SONOS memory device of fig. 1 during a manufacturing process. As shown in fig. 1 and fig. 3a to fig. 3d, in order to more clearly illustrate the characteristics and advantages of the SONOS memory and the method for fabricating the same according to the present invention, a method for fabricating a SONOS memory according to the prior art is first described below.
As shown in fig. 3a, the method for fabricating the SONOS memory device includes a first step: providing a semiconductor substrate 101, wherein the semiconductor substrate 101 comprises a memory area 101a, a selection area 101b and an internode area 101c located between the memory area 101a and the selection area 101b, an ONO layer 102 is formed on the surface of the semiconductor substrate of the memory area 101a, a gate oxide layer 103 is formed on the surface of the semiconductor substrate of the selection area 101b, the ONO layer 102 and the gate oxide layer 103 are connected in the internode area 101c, a gate material layer 104 is further formed on the surface of the semiconductor substrate 101, and the gate material layer 104 covers the surfaces of the ONO layer 102 and the gate oxide layer 103.
As shown in fig. 3b, the method for manufacturing the SONOS memory device includes the second step: coating photoresist on the surface of the gate material layer 104, performing exposure and development processes to expose a part of the gate material layer to be etched, etching the gate material layer 104 by using a dry etching process, and stopping the dry etching on the surface of the ONO layer 102 and the surface of the gate oxide layer 103 to obtain a first gate material layer 104a of the memory region 101a and a second gate material layer 104b of the selection region 101 b.
As shown in fig. 3c, the method for manufacturing the SONOS memory device includes a third step: performing cell etching (CellDrain Etch), etching the ONO layer 102 and the gate oxide layer 103 until the surface of the semiconductor substrate 101 is exposed, obtaining a storage tube gate stack 109 in the storage tube region 101a, and obtaining a selection tube gate stack 110 in the selection tube region 101 b; lightly doped ion implantation (LDD IMP) is performed to form lightly doped ion implantation regions in the semiconductor substrate at both sides of the storage transistor gate stack 109 and the selection transistor gate stack 110.
As shown in fig. 3d, the method for manufacturing the SONOS memory device includes a fourth step: side walls 105 are formed at the sides of the storage tube gate stack 109 and the selection tube gate stack 110.
As shown in fig. 1, the method for manufacturing the SONOS memory device includes a fifth step: a metal silicide layer 106 is formed on the surface of the semiconductor substrate 101 exposed between the sidewalls 105, the upper surfaces of the memory cell gate stack and the select cell gate stack, and electrically connects the first gate material layer and the second gate material layer.
The metal silicide layer between the side walls of the SONOS memory manufactured by the manufacturing method of the SONOS memory is at the same height with the channel region below the storage tube grid lamination and the selection tube grid lamination, because the surface of the semiconductor substrate of the internode region is in uneven step shape, the metal silicide layer formed on the internode region is easy to expand, namely the metal silicide is easy to diffuse and extend to the channel region under the storage tube grid lamination and the selection tube grid lamination, the PN junction formed at the edge of the channel region can be damaged by the metal silicide expansion, so that the electric leakage of the channel region is increased, the SONOS memory can be failed due to electric leakage interference, the reliability of the SONOS memory is reduced, and the production yield can be influenced.
Fig. 4 is a flowchart of a method for fabricating a SONOS memory device according to an embodiment of the invention. In order to solve the above-mentioned problems of increased channel leakage of the SONOS memory device due to extension of the metal silicide on the internode region and failure of the SONOS memory device due to leakage interference, the present embodiment provides a method for manufacturing the SONOS memory device, as shown in fig. 4, the method for manufacturing the SONOS memory device includes the following steps.
Step S1: providing a semiconductor substrate, wherein the surface of the semiconductor substrate comprises a storage tube area, a selection tube area and an internode area positioned between the storage tube area and the selection tube area, an ONO layer is formed on the surface of the semiconductor substrate of the storage tube area, a gate oxide layer is formed on the surface of the semiconductor substrate of the selection tube area, the ONO layer and the gate oxide layer are connected in the internode area, a gate material layer is also formed on the surface of the semiconductor substrate, and the gate material layer covers the surfaces of the ONO layer and the gate oxide layer.
Step S2: and performing an etching process, etching the gate material layer, the ONO layer and the gate oxide layer until the surface of the semiconductor substrate is exposed, obtaining a storage tube gate stack in the storage tube area, and obtaining a selection tube gate stack in the selection tube area.
Step S3: and forming side walls on the side surfaces of the storage tube grid laminated layer and the selection tube grid laminated layer.
Step S4: and performing an epitaxial process to form an epitaxial layer on the exposed surface of the semiconductor substrate.
Step S5: and performing a silicide process, and forming metal silicide layers on the surface of the epitaxial layer and the upper surfaces of the storage tube gate stack and the selection tube gate stack.
Fig. 5a to 5f are schematic cross-sectional views of a SONOS memory device in a manufacturing process according to an embodiment of the invention. The method for fabricating the SONOS memory device according to the present embodiment is described in detail below with reference to fig. 5a to 5 f.
In order to prevent an epitaxial layer (EPI) from being formed on the upper surface of the gate material layer, the method for manufacturing the SONOS memory device of the embodiment may further include forming a hard mask layer on the surface of the gate material layer before performing the etching process, performing patterning on the hard mask layer, and performing the etching process with the patterned hard mask layer as a mask; and after the epitaxial process is executed and before the silicide process is executed, removing the hard mask layer on the surfaces of the storage tube grid laminated layer and the selection tube grid laminated layer. In this embodiment, the gate material layer may be a polysilicon layer. The hard mask layer is formed on the upper surface of the grid material layer, so that the silicon surface of the grid material layer can be isolated and protected by the hard mask layer when an epitaxial process is executed, an epitaxial layer cannot be formed on the upper surfaces of the grid material layers in the storage tube grid lamination layer and the selection tube grid lamination layer, the problem that the performance of the grid material layer is influenced due to the epitaxial layer formed on the surface of the grid material layer can be avoided, and the good performance of a polysilicon grid in the SONOS memory can be kept.
Specifically, as shown in fig. 5a, the surface of the semiconductor substrate 101 includes a memory region 101a, a selection region 101b and an inter-node region 101c located between the memory region 101a and the selection region 101b, an ONO layer 102 is formed on the surface of the semiconductor substrate of the memory region 101a, a gate oxide layer 103 is formed on the surface of the semiconductor substrate of the selection region 101b, the ONO layer 102 and the gate oxide layer 103 are connected in the inter-node region 101c, a gate material layer 104 is further formed on the surface of the semiconductor substrate 101, the gate material layer 104 covers the surfaces of the ONO layer 102 and the gate oxide layer 103, a hard mask layer 107 is formed on the surface of the gate material layer 140, and the hard mask layer 107 covers the gate material layer 104. In the process of forming the ONO layer and the gate oxide layer in sequence, the semiconductor substrate is subjected to a plurality of cleaning and etching processes, so that a certain height difference exists between the surface of the semiconductor substrate forming the storage tube area of the ONO layer and the surface of the semiconductor substrate forming the selection tube area of the gate oxide layer, and the surface of the semiconductor substrate in the internode area is uneven and has step morphology.
In this embodiment, the semiconductor substrate may be a Silicon substrate, and may be a P-type substrate or an N-type substrate, but in other embodiments, the semiconductor substrate may also be a Silicon germanium substrate, an SOI (Silicon On insulator), and the like, and a certain amount of doped particles may be implanted into the semiconductor substrate according to design requirements to change electrical parameters. The ONO layer may be a sandwich structure of silicon oxide-silicon nitride-silicon oxide, and in other embodiments, the ONO layer may be another oxide-nitride-oxide structure, and the gate oxide layer may be a silicon oxide layer. The hard mask layer in this embodiment may be a silicon oxide layer or a silicon nitride layer, however, in other embodiments, the hard mask layer may also be another silicide or a double-layer structure in which a silicon oxide layer and a silicon nitride layer are stacked, as long as the function of preventing an epitaxial layer from being formed on the polysilicon gate material layer is achieved. The silicon oxide layer may be formed using a Low Pressure Radical Oxidation (LPRO) process, a Chemical Vapor Deposition (CVD) process, or a furnace oxidation process, which are well known to those skilled in the art, and the silicon nitride layer may be formed using an Atomic Layer Deposition (ALD) process, a Physical Vapor Deposition (PVD) process, a Chemical Vapor Deposition (CVD) process, a Low Pressure Chemical Vapor Deposition (LPCVD) process, a Plasma Enhanced Chemical Vapor Deposition (PECVD) process, or using an electron cyclotron resonance sputtering process.
In this embodiment, etching the gate material layer, the ONO layer, and the gate oxide layer by using the patterned hard mask layer as a mask may include a combination of multi-step etching and a plurality of etching processes.
Specifically, after a hard mask layer is formed by deposition and patterning is performed, as shown in fig. 5b, the gate material layer 104 is etched by using the patterned hard mask layer 107 as a mask, a dry etching process may be adopted for etching the gate material layer, the dry etching is stopped on the surface of the ONO layer 102 and the surface of the gate oxide layer 103, a first gate material layer 104a is obtained in the memory area 101a, and a second gate material layer 104b is obtained in the select area 101 b.
Continuing to etch the semiconductor substrate, as shown in fig. 5c, performing Cell drain etching (Cell drain et), etching the ONO layer 102 and the gate oxide layer 103 until the surface of the semiconductor substrate 101 is exposed, obtaining a storage tube gate stack 109 in a storage tube area, and obtaining a selection tube gate stack 110 in a selection tube area, where the storage tube gate stack 109 includes the first gate material layer 104a and the remaining ONO layer 102, and the selection tube gate stack 110 includes the second gate material layer 104b and the remaining gate oxide layer 103. In this embodiment, the silicon oxide layer and the gate oxide layer in the ONO layer, which are close to the first gate material layer, may be removed by wet etching, the silicon nitride layer in the ONO layer may be removed by dry etching, the dry etching is stopped on the silicon oxide layer in the ONO layer, which is close to the surface of the semiconductor substrate, and finally the silicon oxide layer in the ONO layer, which is close to the surface of the semiconductor substrate, and the remaining gate oxide layer may be removed by wet etching. However, in other embodiments, if the patterned hard mask layer is not used as a mask, a photoresist layer may be coated on the gate material layer, and then the photoresist layer may be patterned, the patterned photoresist layer may be used as a mask to etch the gate material layer, the ONO layer, and the gate oxide layer, and the photoresist layer may be removed after the etching is finished.
With continued reference to fig. 5c, after forming the storage tube gate stack 109 and the selection tube gate stack 110, the method for manufacturing the SONOS memory device of this embodiment may further include performing an ion implantation process to form lightly doped ion implantation regions in the semiconductor substrate at two sides of the storage tube gate stack 109 and the selection tube gate stack 110. It should be noted that forming the source region and the drain region on the semiconductor substrate may include a plurality of ion implantation processes, forming the lightly doped ion implantation regions in the semiconductor substrate at both sides of the gate stack of the storage tube and the gate stack of the selection tube, which is only a part of the processes, and then performing deep ion implantation in the source/drain formation region to form the source/drain region of the SONOS memory, and forming a PN junction at a junction of the source/drain region and the channel region.
As shown in fig. 5d, after forming the lightly doped ion implantation region, the method for fabricating the SONOS memory device of the present embodiment includes forming a sidewall 105 on the side of the storage transistor gate stack 109 and the selection transistor gate stack 110. The spacers 105 may protect each gate stack from being affected and damaged during subsequent memory fabrication processes. The side wall may be a single-layer structure, such as a single-layer silicon nitride layer, or a multi-layer structure, such as a three-layer stacked structure of silicon oxide-silicon nitride-silicon oxide.
After forming the sidewalls, as shown in fig. 5e, the method for manufacturing the SONOS memory device in this embodiment includes performing an epitaxial process to form an epitaxial layer 108 on the exposed surface of the semiconductor substrate 101. The epitaxial layer covers the exposed surface of the semiconductor substrate, so that the surface of the semiconductor substrate in the internode area is covered by the epitaxial layer, the formed epitaxial layer can not only raise the height of a metal silicide layer formed in the internode area subsequently, so that the metal silicide layer in the internode area is not at the same height as a channel area under an adjacent gate stack, but also can fill and level the internode area, so that the step shape of the surface of the semiconductor substrate in the internode area is changed into a flat surface, and the problem of metal silicide extension caused by the uneven surface of the internode area of the subsequently formed metal silicide layer can be solved.
It should be noted that, in this embodiment, the thickness of the epitaxial layer may be 35nm to 55nm, and the epitaxial layer with a certain thickness may be arranged to separate the metal silicide layer formed subsequently from the channel region to a certain distance, that is, the epitaxial layer with a certain thickness may raise the metal silicide layer by a certain height, so that the effect of the epitaxial layer in separating the metal silicide layer from the channel region is better, and it is ensured that the PN junction at the edge of the channel region is not damaged when the metal silicide layer is subjected to metal silicide extension delay. In addition, if the upper surfaces of the gate material layers in the gate stacks of the memory tube and the select tube have the isolation protection of the hard mask layer made of silicon oxide or silicon nitride, due to the difference between the material of the hard mask layer and the material of the semiconductor substrate (in this embodiment, a silicon substrate), the epitaxial process with high selectivity can be adopted, so that the epitaxial layer is only formed between the side walls, namely only on the two sides of the gate stacks of the memory tube and the select tube, and is not formed on the upper surfaces of the gate material layers in the gate stacks of the memory tube and the select tube. If there is no isolation protection of the hard mask layer during the formation of the epitaxial layer, the upper surfaces of the gate material layers in the gate stacks of the storage transistor and the selection transistor may also form the epitaxial layer, which may affect the performance of the gate material layers in the gate stacks of the storage transistor and the selection transistor.
In this embodiment, after the epitaxial layer is formed, the method for manufacturing the SONOS memory device may further include removing the hard mask layer on the surfaces of the gate stack of the storage transistor and the gate stack of the selection transistor, so that a metal silicide layer may be formed on the upper surfaces of the first gate material layer and the second gate material layer in the following step.
After removing the hard mask layer 107, as shown in fig. 5f, the method for manufacturing the SONOS memory device further includes performing a silicide process to form metal silicide layers on the surface of the epitaxial layer 108 and the upper surfaces of the storage tube gate stack and the selection tube gate stack. In this embodiment, the metal silicide layer 106 may be located on the upper surface of the gate material layer 104 in the epitaxial layer 108 and the storage tube gate stack and the selection tube gate stack, and more specifically, the metal silicide layer 106 may also be formed on the upper surfaces of the first gate material layer 104a and the second gate material layer 104b, and the metal silicide layer may electrically connect the first gate material layer and the second gate material layer. Because the metal silicon compound layer is positioned on the upper surfaces of the epitaxial layer, the storage tube gate stack and the selection tube gate stack, and the epitaxial layer is higher than the surface of the semiconductor substrate, the metal silicon compound layer is higher than the channel region under the storage tube gate stack and the selection tube gate stack, even if the silicon compound layer is extended, PN junctions at the edge of the channel region cannot be damaged, and the leakage of the channel region cannot be caused.
In this embodiment, the step S5 of the method for manufacturing the SONOS memory, that is, the step of performing the silicide process, and forming the metal silicide layer on the surface of the epitaxial layer and the upper surfaces of the storage gate stack and the selection gate stack may specifically include: depositing a patterned protective layer on a semiconductor substrate, wherein the protective layer exposes the surface of the epitaxial layer and the upper surfaces of the storage tube gate stack and the selection tube gate stack; forming a metal material layer on the semiconductor substrate; then, performing an annealing process to form a metal silicide layer; and removing the remaining metal material layer.
It should be noted that, in order to prevent the metal silicide layer from being formed at a non-predetermined position in the semiconductor substrate, i.e. to improve the isolation protection effect of the protection layer, the protection layer may have a double-layer structure, and may include a silicon oxide layer and a silicon nitride layer which are sequentially formed by stacking. The metal material layer may be formed by a physical vapor deposition process or a chemical vapor deposition process, among other deposition processes known to those skilled in the art. In the embodiment, the annealing process is performed to make the metal material layer interact with silicon on the surface of the semiconductor substrate to form a metal silicide layer. In this embodiment, the metal silicide layer may be one or a combination of two or more of NiSi, TiSi, CoSi, and WSi.
The manufacturing method of the SONOS memory comprises the steps of etching a grid material layer, an ONO layer and a grid oxide layer on the surface of a semiconductor substrate until the surface of the semiconductor substrate is exposed, forming side walls on the side faces of the obtained storage tube grid laminated layer and the selection tube grid laminated layer, forming an epitaxial layer on the exposed surface of the semiconductor substrate, covering the surface of the semiconductor substrate in the internode area with the epitaxial layer, and forming a metal silicide layer on the surface of the epitaxial layer. Since the epitaxial layer is formed on the surface of the semiconductor substrate, the upper surface of the epitaxial layer is higher than the surface of the semiconductor substrate, the metal silicide layer is formed on the epitaxial layer to make the metal silicide layer higher than the surface of the semiconductor substrate, because the channel regions under the gate stacks of the storage tube and the selection tube are positioned on the surface of the semiconductor substrate and in the lower region, the metal silicide layer and the channel region are not at the same height, and at the same time, because PN junction is formed at the edge of the channel region, when the metal silicide layer is not at the same height with the channel region, even if the metal silicide layer is expanded, the PN junction at the edge of the channel region can not be damaged, the problem of electric leakage of the memory channel region caused by the expansion of the metal silicide can be effectively avoided, therefore, the memory failure caused by the leakage interference of the channel region can be avoided, and the reliability and the production yield of the SONOS memory can be improved.
In addition, in the method for manufacturing the SONOS memory of this embodiment, preferably, before etching the gate material layer, the ONO layer, and the gate oxide layer, a hard mask layer is formed on the surface of the gate material layer, the hard mask layer is subjected to patterning, and then the patterned hard mask layer is used as a mask for etching. Because the hard mask layer which is different from the semiconductor substrate material is formed on the grid material layer, the hard mask layer can isolate and protect the grid material layer below, and the phenomenon that an epitaxial layer is formed on the grid material layer to influence the performances of the first grid material layer and the second grid material layer in the SONOS memory is avoided. Meanwhile, after the epitaxial layer is formed and before the metal silicide layer is formed, the hard mask layer on the surfaces of the storage tube gate stack and the selection tube gate stack is removed, so that the metal silicide layer can be conveniently formed on the upper surfaces of the gate material layers in the storage tube gate stack and the selection tube gate stack, and the first gate material layer and the second gate material layer are electrically connected.
As shown in fig. 5f, the SONOS memory includes a semiconductor substrate, a storage tube gate structure, a selection tube gate structure, an epitaxial layer, and a metal silicide, where the surface of the semiconductor substrate 101 includes a storage tube region 101a, a selection tube region 101b, and an internode region 101c between the storage tube region 101a and the selection tube region 101b, the storage tube gate structure is located on the surface of the semiconductor substrate of the storage tube region 101a, the storage tube gate structure includes an ONO layer 102 and a first gate material layer 104a that are sequentially formed on the surface of the semiconductor substrate 101, and a sidewall 105 that covers the side surfaces of the ONO layer 102 and the first gate material layer 104a, the selection tube gate structure is located on the semiconductor substrate of the selection tube region 101b, and the selection tube gate structure includes a gate oxide layer 103 and a second gate material layer 104b that are sequentially formed on the surface of the semiconductor substrate 101, and a gate oxide layer 103 and a gate oxide layer 104b, And a side wall 105 covering the side surfaces of the gate oxide layer 103 and the second gate material layer 104b, wherein an epitaxial layer 108 is positioned in a gap between the storage tube gate structure and the select tube gate structure and covers the surface of the semiconductor substrate of the internode region 101c, a metal silicide layer 106 covers the surface of the epitaxial layer 108 and the surfaces of the first gate material layer 104a and the second gate material layer 104b, and the metal silicide layer 106 can enable the first gate material layer 104a and the second gate material layer 104b to be electrically connected. The SONOS memory can further comprise source and drain regions formed on the semiconductor substrate on two sides of the storage tube grid structure and the selection tube grid structure, and the source and drain regions are formed through an ion implantation process.
Specifically, in order to sequentially form an ONO layer and a gate oxide layer on the surfaces of a memory tube area and a selection tube area, the surface of the semiconductor substrate in the internode area is subjected to multiple cleaning and etching processes, so that the surface of the semiconductor substrate in the internode area is uneven and may have a step shape. The ONO layer may be a sandwich structure of silicon oxide-silicon nitride-silicon oxide. The side wall can be a silicon oxide layer or a silicon nitride layer, and can also be a multilayer structure of silicon oxide-silicon nitride-silicon oxide. The epitaxial layer may be a silicon epitaxial layer. The metal silicide layer can be one or a combination of more than two of NiSi, TiSi, CoSi and WSi, and the metal silicide layer is not at the same height with the channel region below the storage tube gate structure and the selection tube gate structure.
In the SONOS memory of this embodiment, the epitaxial layer is located in the gap between the storage tube gate structure and the select tube gate structure, and the epitaxial layer covers the surface of the semiconductor substrate in the inter-node region, so the surface of the epitaxial layer is higher than the surface of the semiconductor substrate, and meanwhile, the metal silicide layer covers the surface of the epitaxial layer, so the metal silicide layer is higher than the surface of the semiconductor substrate, and the channel region under the storage tube gate stack structure and the select tube gate stack structure is located below the surface of the semiconductor substrate, so the metal silicide layer and the channel region are not at the same height and higher than the channel region, which can avoid the leakage of the channel region due to the extension of the metal silicide, thereby avoiding the memory failure caused by the leakage interference of the channel region, and improving the reliability and the production yield of the SONOS memory. In addition, the epitaxial layer can fill and level the surface of the internode area with the step shape, so that the metal silicide layer of the internode area is formed on the surface of the flat semiconductor substrate, the problem of metal silicide extension caused by the unevenness of the internode area can be effectively solved, and the reliability of the SONOS memory is further improved.
The above description is only for the purpose of describing the preferred embodiments of the present invention and is not intended to limit the scope of the claims of the present invention, and any person skilled in the art can make possible the variations and modifications of the technical solutions of the present invention using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention, and therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention belong to the protection scope of the technical solutions of the present invention.
Claims (10)
1. A method for manufacturing a SONOS memory is characterized by comprising the following steps:
providing a semiconductor substrate, wherein the surface of the semiconductor substrate comprises a storage tube area, a selection tube area and an internode area positioned between the storage tube area and the selection tube area, an ONO layer is formed on the surface of the semiconductor substrate in the storage tube area, a gate oxide layer is formed on the surface of the semiconductor substrate in the selection tube area, the ONO layer and the gate oxide layer are connected in the internode area, a gate material layer is also formed on the surface of the semiconductor substrate, and the gate material layer covers the surfaces of the ONO layer and the gate oxide layer;
performing an etching process to etch the gate material layer, the ONO layer and the gate oxide layer until the surface of the semiconductor substrate is exposed, obtaining a storage tube gate stack in the storage tube area and a selection tube gate stack in the selection tube area;
forming side walls on the side surfaces of the storage tube grid laminated layer and the selection tube grid laminated layer;
performing an epitaxial process, and forming an epitaxial layer on the exposed surface of the semiconductor substrate; and
and performing a silicide process, and forming metal silicide layers on the surface of the epitaxial layer and the upper surfaces of the storage tube gate stack and the selection tube gate stack.
2. The method of fabricating the SONOS memory device of claim 1, wherein the method of fabricating further comprises:
before the etching process is executed, forming a hard mask layer on the surface of the grid material layer, and carrying out graphical processing on the hard mask layer; and
and after the epitaxial process is executed and before the silicide process is executed, removing the hard mask layer on the surfaces of the storage tube grid laminated layer and the selection tube grid laminated layer.
3. The method of fabricating the SONOS memory device of claim 2, wherein after the silicide process is performed, the metal silicide layer is on the epitaxial layer and on top of the gate material layers in the memory cell gate stack and the select cell gate stack.
4. The method of fabricating the SONOS memory device of claim 1, wherein after the performing the etching process and before the forming the sidewall spacers, further comprising:
and performing ion implantation to form lightly doped ion implantation regions in the semiconductor substrate at two sides of the storage tube gate stack and the selection tube gate stack.
5. The method of one of claims 1 to 4, wherein the epitaxial layer has a thickness of 35nm to 55 nm.
6. The method of one of claims 1 to 4, wherein the step of performing the silicide process to form a metal silicide layer on the surface of the epitaxial layer and on the upper surfaces of the storage tube gate stack and the selection tube gate stack comprises:
depositing a patterned protective layer on the semiconductor substrate, wherein the protective layer exposes the surface of the epitaxial layer and the upper surfaces of the storage tube gate stack and the selection tube gate stack;
forming a metal material layer on the semiconductor substrate;
performing an annealing process to form the metal silicide layer; and
and removing the residual metal material layer.
7. The method of claim 6, wherein the protection layer comprises a silicon oxide layer and a silicon nitride layer sequentially stacked.
8. The method of one of claims 2 or 3, wherein the hard mask layer is a silicon oxide layer or a silicon nitride layer.
9. The method of fabricating the SONOS memory device of any one of claims 1 to 4, wherein the metal silicide layer comprises one or a combination of two or more of NiSi, TiSi, CoSi, and WSi.
10. A SONOS memory, comprising:
the semiconductor substrate comprises a memory area, a selection area and an internode area positioned between the memory area and the selection area;
the storage tube gate structure is positioned in the storage tube area and comprises an ONO layer, a first gate material layer and a side wall, wherein the ONO layer and the first gate material layer are sequentially formed on the surface of the semiconductor substrate in an overlapping mode, and the side wall covers the side surfaces of the ONO layer and the first gate material layer;
the grid structure of the selection tube is positioned in the selection tube area and comprises a grid oxide layer and a second grid material layer which are sequentially formed on the surface of the semiconductor substrate in an overlapping mode, and a side wall covering the side surfaces of the grid oxide layer and the second grid material layer;
the epitaxial layer is positioned in a gap between the storage tube grid structure and the selection tube grid structure and covers the surface of the semiconductor substrate in the internode area; and
and the metal silicide layer covers the surface of the epitaxial layer and the surfaces of the first grid material layer and the second grid material layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010231443.7A CN111244104B (en) | 2020-03-27 | 2020-03-27 | SONOS memory and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010231443.7A CN111244104B (en) | 2020-03-27 | 2020-03-27 | SONOS memory and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111244104A true CN111244104A (en) | 2020-06-05 |
| CN111244104B CN111244104B (en) | 2023-09-15 |
Family
ID=70869787
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010231443.7A Active CN111244104B (en) | 2020-03-27 | 2020-03-27 | SONOS memory and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111244104B (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111863943A (en) * | 2020-07-31 | 2020-10-30 | 上海华力微电子有限公司 | SONOS memory and manufacturing method thereof |
| CN113643969A (en) * | 2021-07-27 | 2021-11-12 | 上海华力集成电路制造有限公司 | Method for improving corrosion of high-K dielectric gate by optimizing polysilicon etching |
| CN114464526A (en) * | 2022-04-12 | 2022-05-10 | 晶芯成(北京)科技有限公司 | Multi-time programmable memory and preparation method thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108091562A (en) * | 2017-12-21 | 2018-05-29 | 上海华力微电子有限公司 | The ONO lithographic methods of SONOS memories |
| CN108172581A (en) * | 2017-12-26 | 2018-06-15 | 上海华力微电子有限公司 | A kind of transistor and its manufacturing method of band SONOS structures |
| CN110277399A (en) * | 2019-05-15 | 2019-09-24 | 上海华力集成电路制造有限公司 | SONOS memory and its manufacturing method |
-
2020
- 2020-03-27 CN CN202010231443.7A patent/CN111244104B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108091562A (en) * | 2017-12-21 | 2018-05-29 | 上海华力微电子有限公司 | The ONO lithographic methods of SONOS memories |
| CN108172581A (en) * | 2017-12-26 | 2018-06-15 | 上海华力微电子有限公司 | A kind of transistor and its manufacturing method of band SONOS structures |
| CN110277399A (en) * | 2019-05-15 | 2019-09-24 | 上海华力集成电路制造有限公司 | SONOS memory and its manufacturing method |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111863943A (en) * | 2020-07-31 | 2020-10-30 | 上海华力微电子有限公司 | SONOS memory and manufacturing method thereof |
| CN113643969A (en) * | 2021-07-27 | 2021-11-12 | 上海华力集成电路制造有限公司 | Method for improving corrosion of high-K dielectric gate by optimizing polysilicon etching |
| CN113643969B (en) * | 2021-07-27 | 2024-01-19 | 上海华力集成电路制造有限公司 | Method for improving corrosion of high-K dielectric gate by optimizing polysilicon etching |
| CN114464526A (en) * | 2022-04-12 | 2022-05-10 | 晶芯成(北京)科技有限公司 | Multi-time programmable memory and preparation method thereof |
| CN114464526B (en) * | 2022-04-12 | 2022-06-17 | 晶芯成(北京)科技有限公司 | Multi-time programmable memory and preparation method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN111244104B (en) | 2023-09-15 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8022464B2 (en) | Semiconductor memory device and manufacturing method thereof | |
| JP4703669B2 (en) | Semiconductor memory device and manufacturing method thereof | |
| JP4923078B2 (en) | Semiconductor memory device and method of manufacturing the semiconductor memory device | |
| US9711657B2 (en) | Silicide process using OD spacers | |
| JP2009212218A (en) | Semiconductor storage device and method for manufacturing the same | |
| JP2002359308A (en) | Semiconductor memory and its fabricating method | |
| CN111244104B (en) | SONOS memory and manufacturing method thereof | |
| US9431256B2 (en) | Semiconductor device and manufacturing method thereof | |
| US8187952B2 (en) | Method for fabricating semiconductor device | |
| US7382054B2 (en) | Method for forming self-aligned contacts and local interconnects simultaneously | |
| US7595239B2 (en) | Method of fabricating flash memory device | |
| JP5454543B2 (en) | Manufacturing method of semiconductor device | |
| JP4290548B2 (en) | Manufacturing method of semiconductor device including nonvolatile memory including memory cell having access gate, control gate, and charge storage region | |
| JP2009231300A (en) | Semiconductor memory and fabrication method therefor | |
| US7807577B2 (en) | Fabrication of integrated circuits with isolation trenches | |
| JP2011066052A (en) | Semiconductor device manufacturing method, and the semiconductor device | |
| JP3622741B2 (en) | Manufacturing method of semiconductor device | |
| TWI539557B (en) | Self-aligned method of forming a semiconductor memory array of floating gate memory cells with single poly layer | |
| US20080305595A1 (en) | Methods of forming a semiconductor device including openings | |
| US20050236660A1 (en) | Semiconductor device and method of fabricating the same | |
| US7651912B2 (en) | Semiconductor device and method of fabricating the same | |
| JP5525695B2 (en) | Semiconductor device and manufacturing method thereof | |
| US9666588B2 (en) | Damascene non-volatile memory cells and methods for forming the same | |
| JP2014187132A (en) | Semiconductor device | |
| TWI451533B (en) | Method of forming embedded flash memory |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |