TWI451533B - Method of forming embedded flash memory - Google Patents

Description

Embedded flash memory manufacturing method

The present invention relates to a method of fabricating a semiconductor device, and more particularly to a method of fabricating an embedded flash memory.

In order to reduce the cost and simplify the process steps of semiconductor components, it has become a trend to integrate components of the memory cell and the peripheral cell on the same wafer, such as flash memory and logic components. Integrated on the same chip, it is called embedded flash memory.

In general, logic components use a cobalt-cobalt process to reduce resistance and improve component performance. As the design criteria are gradually reduced due to the shrinking size of the semiconductor component, the distance from the word line to the source/drain of the flash memory is also reduced. At this time, if a cobalt telluride process is used, a word line to source may occur. Leakage of pole/bungee. Therefore, there is currently no way to create an embedded flash memory that takes into account both performances.

In view of the above, the present invention provides a method for fabricating an embedded flash memory, which can avoid the leakage phenomenon of the word line to the source/drain of the flash memory while maintaining the performance of the logic element.

The invention provides a method for manufacturing a word line of an embedded flash memory. A substrate having a cell region and a peripheral region is provided, and the plurality of isolation structures are disposed in the substrate and respectively have a plurality of protrusions protruding from the substrate, and a dielectric pattern is disposed between the adjacent protrusions. A portion of the dielectric pattern on the cell region is removed to form a first opening between adjacent protrusions. A first conductor layer is formed between the first openings of the unit cell region. The dielectric pattern on the peripheral region is removed to form a second opening between adjacent protrusions. An insulating layer and a second conductor layer are sequentially formed on the substrate of the peripheral region to fill the second opening. A portion of each protrusion of the cell region is removed. An insulating material layer, a third conductive material layer, a first metal telluride material layer, and a mask material layer are sequentially formed on the substrate of the unit cell region and the peripheral region. At least one patterning process is performed to form a plurality of first gate structures on the cell region and at least one second gate structure on the peripheral region. A second metal telluride layer is formed on the substrate between the first gate structures, the top surface of the second gate structure, and the substrates on both sides of the second gate structure.

In an embodiment of the invention, each of the first gate structures includes a tunneling oxide layer, a floating gate, an insulating layer, a control gate, a first metal telluride layer, and a mask layer sequentially disposed on the substrate. And the second gate structure includes a gate oxide layer and a gate electrode sequentially disposed on the substrate.

Based on the above, in the embedded flash memory of the present invention, since the upper portion of the gate structure of the cell region is the mask layer, the cobalt halide process for the peripheral region does not occur at the top of the gate structure. Therefore, the leakage from the word line to the source/drain of the cell region does not occur and the performance of the flash memory is lowered. On the other hand, the use of a cobalt antimonide process in the logic elements of the peripheral region reduces the resistance and improves component performance.

The above described features and advantages of the present invention will be more apparent from the following description.

1A to 1H are schematic cross-sectional views of an embedded flash memory according to an embodiment of the invention.

First, referring to FIG. 1A, a substrate 100 is provided. The substrate 100 is, for example, a germanium substrate having a cell region 100a and a peripheral region 100b. The plurality of isolation structures 101 are disposed in the substrate 100 and have a plurality of protrusions 101a protruding from the substrate 100, respectively. The isolation structure 101 is, for example, a shallow trench isolation (STI) structure. A dielectric pattern 102 is disposed between adjacent protrusions 101a. Each of the dielectric patterns 102 includes an oxide pattern 103 and a nitride pattern 105 on the oxide pattern. The material of the oxide pattern 103 is, for example, cerium oxide. The material of the nitride pattern 105 is, for example, tantalum nitride. The method of forming the above structure includes forming a plurality of dielectric patterns 102 on the substrate 100. Then, a portion of the substrate 100 is removed with the dielectric pattern 102 as a mask to form a plurality of trenches in the substrate 100. Next, a ruthenium oxide layer is formed on the substrate 100 to fill the trench. Thereafter, a portion of the hafnium oxide layer is removed until the surface of the dielectric pattern 102 is exposed.

Next, referring to FIG. 1B, a portion of the dielectric pattern 102 on the cell region 100a is removed to form a first opening 104 between adjacent protrusions 101a. Specifically, the partial dielectric pattern 102 on the cell region 100a is removed to remove the nitride pattern 105 on the cell region 100a. The removing step includes forming a patterned photoresist layer on the substrate 100. Then, the patterned photoresist layer is a mask, and an etching process is performed to remove the nitride pattern 105 on the cell region 100a, and the oxide pattern 103 on the cell region 100a is left. Thereafter, a first conductor material layer 107 is formed on the substrate 100 of the cell region 100a and the peripheral region 100b. The first conductor material layer 107 covers the cell region 100a and the peripheral region 100b and is filled in the first opening 104. The material of the first conductive material layer 107 is, for example, polycrystalline germanium, and the method of forming the same includes performing a chemical vapor deposition process.

Next, referring to FIG. 1C, the first conductive material layer 107 on the peripheral region 100b is removed, and a portion of the first conductive material layer 107 on the cell region 100a is removed until the top surface of the protrusion 101a is exposed. Therefore, the first conductor layer 106 is formed between the first openings 104 of the cell region 100a. The above removal step is, for example, an etching process or a chemical mechanical polishing process.

Thereafter, referring to FIG. 1D, the dielectric pattern 102 on the peripheral region 100b is removed to form a second opening 108 between the adjacent protrusions 101a. The second opening 108 exposes a portion of the substrate 100 of the perimeter region 100b. The removing step includes forming a patterned photoresist layer covering only the cell region 100a on the substrate 100. Then, using the patterned photoresist layer as a mask, an etching process is performed to remove the dielectric pattern 102 on the peripheral region 100b.

Then, the insulating layer 110 and the second conductor layer 112 are sequentially formed on the substrate 100 of the peripheral region 100b to be filled in the second opening 108. The method of forming the insulating layer 110 and the second conductor layer 112 includes forming a tantalum nitride layer covering only the cell region 100a. Then, a thermal oxidation method is performed to form the insulating layer 110 on the exposed substrate 100 of the peripheral region 100b. The insulating layer 110 is, for example, a ruthenium oxide layer. Next, a second conductive material layer and a patterned photoresist layer are sequentially formed on the substrate 100 of the cell region 100a and the peripheral region 100b. The second conductive material layer is, for example, a polycrystalline germanium layer, and the method of forming the same includes performing a chemical vapor deposition process. Thereafter, the second conductive material layer on the cell region 100a is removed by using the patterned photoresist layer as a mask. Next, the tantalum nitride layer covering the cell region 100a is removed.

Then, referring to FIG. 1E, a portion of each of the protrusions 101a of the cell region 100a is removed. The removing step includes selectively forming a patterned photoresist layer covering the peripheral region 100b on the substrate 100. Then, an etch back process is performed to remove a portion of each of the protrusions 101a of the cell region 100a. Therefore, the isolation structure 101 having the protrusions 101b is formed on the unit cell region 100a.

Next, an insulating material layer 114, a third conductive material layer 116, a first metal telluride material layer 118, and a mask material layer 120 are sequentially formed on the substrate 100 of the cell region 100a and the peripheral region 100b. The insulating material layer 114 is, for example, an ONO composite layer. The third conductor layer 116 is, for example, a polysilicon layer. The first metal halide material layer 118 is, for example, a tungsten germanium layer. The mask material layer 120 is, for example, a tantalum nitride layer. The method of forming the above stacked layers includes performing a chemical vapor deposition process each.

Thereafter, referring to FIG. 1F, at least one patterning process is performed to form a plurality of first gate structures 122 on the cell region 100a and at least one second gate structure 124 on the peripheral region 100b. Each of the first gate structures 122 includes a tunneling oxide layer 103a, a floating gate 106a, an insulating layer 114a, a control gate 116a, a first metal telluride layer 118a, and a mask layer 120a. The second gate structure 124 includes a gate oxide layer 110a and a gate 112a sequentially disposed on the substrate 100. Since the cell layer 100a is different from the stacked film layer formed on the peripheral region 100b, at least one patterning process is required to form the first gate structure 122 and the second gate structure 124. For example, the first patterning process may remove the insulating material layer 114, the third conductive material layer 116, the first metal telluride material layer 118, and the mask material layer 120 on the peripheral region 100b; the second patterning The process can pattern the stacked film layers on the cell region 100a; and the third patterning process can pattern the stacked film layers on the peripheral region 100b.

2 is a top view of FIG. 1F, having an I-I' hatching line and a II-II' hatching line, FIG. IF is taken along the line I-I' of FIG. 2, and FIG. 1F-1 is along the figure. The II-II' hatching of 2 is shown. For clarity of illustration, FIG. 2 only shows the floating gate 106a of the cell region 100a and the control gate 116a, and the gate 112a of the peripheral region 100b. In particular, in FIG. 1F-1, a second gate structure 124 is formed on the peripheral region 100b as an example, but the invention is not limited thereto. It should be understood by those of ordinary skill in the art that the peripheral region 100b can have a high voltage device region and a low voltage device region, and the gate oxide layers formed on the high voltage device region and the low voltage device region can have different thicknesses.

1A to 1F are shown in cross-section along the line I-I', and the following description will be made by referring to Figs. 1F-1, 1G to 1H according to the II-II' hatching.

Referring to FIG. 1G, a first spacer 126 and a second spacer 128 are formed on sidewalls of each of the first gate structure 122 and the second gate structure 124, respectively. The thickness of each of the first spacers 126 and the second spacers 128 is different. In an embodiment, the thickness of the second spacer 128 is greater than the thickness of each of the first spacers 126. Each of the first spacers 126 and the second spacers 128 may each be a single layer structure or a multilayer structure formed of a plurality of different materials. The method of forming the first spacer 126 and the second spacer 128 is well known to those of ordinary skill in the art and will not be described again.

Then, a second metal germanide layer 130 is formed on the substrate 100 between the first gate structures 122, the top surface of the second gate structure 124, and the substrate 100 on both sides of the second gate structure 124. The second metal telluride layer 130 is formed by sputtering a metal layer on the substrate 100. The material of the metal layer is, for example, cobalt. Subsequently, an annealing treatment is performed to cause a portion of the cobalt layer to react with the ruthenium to form the second metal ruthenide layer 130. Thereafter, the unreacted metal layer is removed.

The material of the first metal telluride layer 118a of the present invention includes tungsten telluride, and the material of the second metal telluride layer 130 includes cobalt telluride. The use of a cobalt antimonide process in the logic elements of the peripheral region 100a reduces the resistance and improves component performance. At this time, since the upper portion of the first gate structure 122 of the cell region 100a is the mask layer 120a, the cobalt telluride process does not occur at the top of the first gate structure 122. Therefore, the leakage from the word line to the source/drain of the cell region 100a does not occur in the subsequent self-aligned contect process and affects the reliability of the flash memory. Further, in the cell region 102a, the first metal germanide layer 118a is disposed above the control gate 116a, and the resistance of the control gate 116a as the word line can be lowered.

Next, a plurality of semiconductor processes including deposition, lithography, etching, and the like are performed to complete the embedded flash memory of the present invention, as shown in FIG. 1H. The steps not described in the middle of Figures 1G to 1H are well known to those of ordinary skill in the art and will not be described again.

Referring to FIG. 1H, a tantalum nitride pattern 132 is formed on the top surface of each of the first gate structures 122 of the cell region 100a. A dielectric layer 134 is formed on the substrate 100 of the peripheral region 100b. Dielectric layer 134 can be a single layer or a multilayer structure. The dielectric layer 134 covers the second gate structure 124 and has an opening 136 that exposes a portion of the substrate 100 on one side of the second gate structure 124. A metal layer 138 is further formed on the substrate 100 to fill the gap between the first gate structures 122 and the openings 136, and the metal layer 138 is electrically connected to the second metal telluride layer 130. The metal layer 138 is, for example, a tungsten layer. Further, on the cell region 100a, the top surface of the metal layer 138 is substantially coplanar with the top surface of the tantalum nitride pattern 132. The metal layer 138 on the cell region 100a serves as a bit line layer. The metal layer 138 on the peripheral region 102b serves as a conductive plug. So far, the fabrication of the embedded flash memory of the present invention has been completed.

In summary, in the embedded flash memory of the present invention, since the upper portion of the gate structure of the cell region is a mask layer, the cobalt telluride process for the peripheral region does not occur in the gate structure. top. Therefore, the leakage from the word line to the source/drain of the cell region does not occur and the performance of the flash memory is lowered. On the other hand, the use of a cobalt antimonide process in the logic elements of the peripheral region reduces the resistance and improves component performance.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

100. . . Base

100a. . . Cell area

100b. . . Surrounding area

101. . . Isolation structure

101a, 101b. . . Protrusion

102. . . Dielectric pattern

103. . . Oxide pattern

103a. . . Tunneling oxide layer

104. . . First opening

105. . . Nitride pattern

106. . . First conductor layer

106a. . . Floating gate

107. . . First conductor material layer

108. . . Second opening

110. . . Insulation

110a. . . Gate oxide layer

112. . . Second conductor layer

112a. . . Gate

114. . . Insulating material layer

114a. . . Insulation

116‧‧‧ Third conductor material layer

116a‧‧‧Control gate

118‧‧‧First metal telluride material layer

118a‧‧‧First metal telluride layer

120‧‧‧ Cover material layer

120a‧‧‧ Cover layer

122‧‧‧First gate structure

124‧‧‧Second gate structure

126‧‧‧ first gap

128‧‧‧Second gap

130‧‧‧Second metal telluride layer

132‧‧‧ nitride pattern

134‧‧‧ dielectric layer

136‧‧‧ openings

138‧‧‧metal layer

1A to 1H are schematic cross-sectional views of an embedded flash memory according to an embodiment of the invention.

Figure 2 is a top plan view of Figure 1F.

100. . . Base

100a. . . Cell area

100b. . . Surrounding area

103a. . . Tunneling oxide layer

106a. . . Floating gate

110a. . . Gate oxide layer

112a. . . Gate

114a. . . Insulation

116a. . . Control gate

118a. . . First metal telluride layer

120a. . . Mask layer

122. . . First gate structure

124. . . Second gate structure

126. . . First spacer

128. . . Second spacer

130. . . Second metal telluride layer

Claims (9)

A method of fabricating an embedded flash memory, comprising: providing a substrate having a cell region and a peripheral region, wherein a plurality of isolation structures are disposed in the substrate and respectively having a plurality of protrusions protruding from the substrate, adjacent a dielectric pattern is disposed between the protrusions; a portion of the dielectric patterns on the cell region are removed to form a first opening between adjacent protrusions; and the cell region and the peripheral region Forming a first conductive material layer on the substrate; removing the first conductive material layer on the peripheral region, and removing a portion of the first conductive material layer on the cell region until a top surface of the protrusions is exposed Forming a first conductor layer between the first openings of the cell region; removing the dielectric patterns on the peripheral region to form a second opening between adjacent protrusions; An insulating layer and a second conductor layer are sequentially formed on the substrate of the peripheral region to fill the second openings; a portion of each protrusion of the cell region is removed; and the cell region is Forming an insulating material layer on the substrate of the peripheral region, a third a bulk material layer, a first metal telluride material layer and a mask material layer; performing at least one patterning process to form a plurality of first gate structures on the cell region and forming at least one on the peripheral region Second gate structure; A second metal telluride layer is formed on the substrate between the first gate structures, the top surface of the second gate structure, and the substrate on both sides of the second gate structure. The method of fabricating an embedded flash memory according to claim 1, wherein the first metal telluride material layer is different from the second metal germanide layer. The method of manufacturing an embedded flash memory according to claim 2, wherein the material of the first metal halide material layer comprises tungsten telluride. The method of manufacturing an embedded flash memory according to claim 2, wherein the material of the second metal telluride layer comprises cobalt telluride. The method of fabricating an embedded flash memory according to claim 1, wherein each of the dielectric patterns includes an oxide pattern and a nitride pattern on the oxide pattern, and the unit cell region is removed. The upper portion of the dielectric patterns removes the nitride patterns on the cell region. The method for manufacturing an embedded flash memory according to claim 1, wherein each of the first gate structures comprises a tunneling oxide layer, a floating gate, and an insulating layer sequentially disposed on the substrate. a layer, a control gate, a first metal telluride layer and a mask layer, and the second gate structure comprises a gate oxide layer and a gate sequentially disposed on the substrate. The method for manufacturing an embedded flash memory according to claim 1, wherein after the patterning process and before forming the second metal germanide layer, each of the first gate structures and the first A first spacer and a second spacer are respectively formed on the sidewalls of the two gate structures. The method of manufacturing an embedded flash memory according to claim 7, wherein each of the first spacers and the second spacer has a different thickness. The method for manufacturing an embedded flash memory according to the first aspect of the invention, after forming the second metal germanide layer, further comprising a gap between the first gate structures of the cell region. A metal layer is formed in the metal layer, and the metal layer is electrically connected to the second metal halide layer.