TW200917422A - Non-volatile memory cell, NAND-type non-volatile memory and method of manufacturing thereof - Google Patents

Abstract

A method of manufacturing a non-volatile memory cell is provided. An insulating layer, a first conductive layer, an inter-gates insulating layer, a second conductive layer and a hard mask layer are sequentially formed on a substrate. The hard mask layer, the second conductive layer, the inter-gates insulating layer and the first conductive layer are patterned in order to form a stacked gate structure. A portion of the insulating layer disposed at the sides of the stacked gate structure on the substrate is removed until a surface of the substrate is exposed. An epitaxial material layer is formed on the substrate. Next, an ion implant process is performed to form a doping region in the substrate and the epitaxial material layer is converted into a doped epitaxial layer.

Description

200917422 _ 'twf.doc/p IX. DESCRIPTION OF THE INVENTION: TECHNICAL FIELD The present invention relates to a memory and a method of fabricating the same, and more particularly to a non-volatile memory cell, a NAND type non-volatile memory Body and its manufacturing method. [Prior Art] Among various memory products, there are non-volatile § which can perform the operations of depositing, reading, erasing, etc., and the stored data will not disappear after power-off. Recalling 'has become a memory component widely used in personal computers and electronic devices. 〃 On the other hand, the non-volatile memory arrays currently used in the industry include reverse OR gate (NOR) array structures and reverse gate (NAND) array structures. Since the non-volatile memory structure of the NAND type array is such that the memory cells are connected in series, the degree of integration and area utilization is better than that of the non-volatile memory of the gate (NOR) type array. , has been widely used in; electronic products. However, with the development of the integrated circuit, the lateral size of the memory is shrinking, and therefore the length of the channel in the memory is also small. In this way, when operating non-volatile memory, under different bias voltages, it is more likely to cause program disturb, and the memory is written incorrectly, which leads to the reliability of the § memory. Reliability) lower. In general, by implanting a high concentration of dopants in the source/drain regions of the sigma memory, the hot carrier injection (HCI) problem can be reduced, and the memory cells can be improved in programming. The interference problem at the time. 200917422 >twf.doc/p However, 'the method of extracting the concentration of the dopant in the electrode/no-polar region makes it easy for the source/no-polar region to pass through, which will seriously affect the memory of the memory device. Sexual performance of electrical breakdown problems 'Typical traitors need to carry out ring implants (four) 〇impianta-) and other anti-penetration procedures. Lin's is that when ring-shaped implant technology is used to build a ship, the reliability of the component is relatively reduced. From this, it is known that in the current trend of miniaturization of components, how to balance the degree of component accumulation and component reliability in the space of η u is one of the focuses. In view of the above, the present invention provides a non-volatile memory cell, a NAND-type non-volatile memory, and a method of fabricating the same, which can achieve a shallow junction depth and avoid various conventional problems and Improve component reliability. The invention provides a method for preparing a non-volatile memory cell. First, an insulating layer, a first conductor layer, an inter-gate insulating layer, a two-conductor layer, and a hard mask layer are sequentially formed on the substrate. Then, the hard mask layer, the dummy layer, the inter-gate insulating layer and the first conductor layer are patterned to form a stacked drain structure. The insulating layer on the substrate on both sides of the stacked gate structure is then removed until the substrate surface is exposed. Subsequently, a layer of epitaxial material is formed on the exposed substrate. Next, an ion implantation process is performed to form a doped region in the substrate: and to transform the layer of the germanic material into a layer of doped house material. The method for forming the non-volatile memory cell according to the embodiment of the present invention is, for example, a method of forming an epitaxial material layer by performing a selective epitaxial growth process. The method for fabricating a non-volatile memory cell according to an embodiment of the present invention, wherein the method of removing a portion of the insulating layer until the surface of the substrate is exposed is, for example, performing an etch back. Process. The method for producing a non-volatile memory cell according to an embodiment of the present invention is as follows. A method of forming the above-mentioned oxide layer is, for example, performing a reoxidation process. The method for fabricating a non-volatile memory cell according to an embodiment of the present invention, after forming the gate structure, and before removing a portion of the insulating layer, further comprises forming a sidewall on the sidewall of the stacked gate structure. Oxide layer. The method for fabricating a non-volatile memory cell according to an embodiment of the present invention further includes performing a pre-cleaning step after removing a portion of the insulating layer and before forming the layer of the epitaxial material. According to a method of fabricating a non-volatile memory cell according to an embodiment of the present invention, the material of the first conductor layer is, for example, doped polysilicon. According to a method of fabricating a non-volatile memory cell according to an embodiment of the invention, the material of the second conductor layer is, for example, doped polysilicon.

According to a method of fabricating a non-volatile memory cell according to an embodiment of the present invention, the second conductor layer is composed of, for example, a conductor material layer and a metal ceramsite layer. The present invention further provides a non-volatile memory cell comprising a substrate, a stack 3: a gate structure, an insulating layer, and a doped material layer. Wherein, the stacked gate structure is disposed on the substrate. The stacked gate structure is composed of, for example, a first conductor layer, an inter-gate insulating layer, a second conductor layer and a hard mask layer from the substrate upward. Further, the insulating layer is disposed between the substrate, the oxide layer, and the stacked gate structure. A layer of doped epitaxial material is disposed on the substrate on both sides of the stacked gate structure 200917422 2twf.doc/p. The swap region is disposed in the substrate underlying the layer of doped epitaxial material. The non-volatile memory cell according to an embodiment of the invention further includes an oxide layer disposed on the sidewall of the stacked gate structure. According to the non-volatile memory cell of the embodiment of the present invention, the material of the first conductor layer is, for example, doped polycrystalline. According to the non-volatile memory cell of the embodiment of the present invention, the material of the first conductor layer is, for example, doped polysilicon.

In addition to the non-volatile memory cell according to the embodiment of the present invention, the second conductor layer is composed of, for example, a layer of a conductor material and a layer of a metal material. This book also mentions the production of NAND type non-volatile memory. First, a substrate is provided, the substrate having a selective gate region. Then, an insulating layer, a first conductor layer, and an inter-gate insulating layer are sequentially formed on the surface. Connect: at least part of the open dielectric layer of the pole region to expose

And: set the body layer. Then, the portion of the second conductor layer exposed on the substrate is sequentially exposed to cover the dielectric layer and the conductive layer. Subsequently, the hard mask layer, the second structure, the == layer and the first conductor layer are patterned to form a plurality of stacked gates. After that, shift = two sides of the side pole structure to select the gate 'two phases. The material layer is formed on each of the stacked gate structures and the substrate. Selecting the gate poles into the private, forming the -axis region on both sides of the stacked gate structure and the bottom of the shell 1 and transforming the layer of the telecrystalline material -twf.d〇c/p 200917422 into a doped epitaxial Material layer. According to the method for fabricating a NAND-type non-volatile body according to an embodiment of the present invention, the above-mentioned 四(4) layer age 彡 ^ ^ 二 选择性 选择性 选择性 选择性 选择性 选择性 选择性 选择性 选择性 选择性 选择性 选择性 选择性 选择性 选择性 选择性 选择性The NAND type non-volatile memory method described in the embodiment of the present invention is, for example, a nand-type non-volatile memory gasification process in which the edge layer is exposed to the surface of the substrate. The method for forming the above-mentioned oxide layer is, for example, a NAND type non-volatile memory insulating layer described in the embodiment of the present invention. After the conversion, the second part is removed. Included in the sidewall of the stacked gate structure - oxidized reed. Before the NAND-type non-volatile recording of the body described in the example of the moon, the (10) after the partial insulation layer is formed, the layer of the suspension material is formed. - Pre-cleaning step. The body of the invention is a non-volatile memory of the NAND type described in the example. The material of the first conductor layer is, for example, the surface of the doped polycrystal. The material of the second conductor layer is, for example, a NAND-type non-volatile memory of doped polycrystals; the second conductor layer of L is, for example, a layer of conductive material and 200917422 -twf.doc/p The present invention further proposes a NAND type non-volatile bribe, an I substrate, a plurality of stack (four) pole structures, a selection structure, and an insulating layer as a layer of a parasitic material. The substrate has a "selective gate region". Multiple gate gate structures are arranged in series on the substrate The gate structure is disposed on the substrate of the selection_region on both sides of the stacked gate structure. The stack structure is, for example, sequentially from the substrate to the first conductor layer, the gate region, and the second conductor layer. The hard mask layer is mixed. In addition, the insulating layer is disposed between the stack gate structure, the substrate and the oxide layer, and is disposed between the selected gate and the substrate. The doped epitaxial material layer is disposed in each of the stacked gates. The pole structure is on the side and the substrate on both sides of the selected gate structure. The doped region is disposed in the substrate on both sides of the stacked gate structure and on both sides of the selected gate structure. The NAND type non-destruction according to the embodiment of the present invention The volatile memory further includes an oxide layer disposed on the sidewall of the stacked gate structure. In the second embodiment, the 'oxide layer further includes sidewalls disposed at the same time to select the gate structure. According to an embodiment of the present invention The NAND type non-volatile memory, the material of the above-mentioned conductor layer is, for example, doped polycrystalline stone. The NAND type non-volatile carrier according to the embodiment of the present invention, the second conductor layer The material is, for example, more doped X ° According to the NAND type non-volatile memory of the embodiment of the present invention, the second conductor layer is composed of a conductor material layer and a metal halide layer, for example. The method of the present invention is to form a doped region. Previously, a layer of insect crystal material was formed on the substrate by a selective stupid growth process. The structure of the present invention is provided with an epitaxial material layer above the doping 200917422, twf.doc/p region. Therefore, the memory device can be further reduced. Source/drain junction (source/drajn juncti〇n, s/d juncti〇n) depth to improve the reliability of the component. In order to make the above features and advantages of the present invention more obvious, the following is a special The preferred embodiment, in conjunction with the drawings, is described in detail below. [Embodiment] Hereinafter, the production of non-volatile memory will be taken as an example.

The invention is not intended to limit the scope of the invention. FIG. 1A to FIG. 1H are schematic diagrams showing a manufacturing process of a non-volatile memory according to an embodiment of the present invention. The non-volatile memory manufacturing process of the present invention includes the non-volatile memory cell of the present invention and a NAND type. A method of making non-volatile memory. First, referring to FIG. 1A, a substrate 100 is provided, such as a substrate or other suitable semiconductor substrate. The substrate 1 has a memory cell region 101 and a peripheral circuit region 103, and the memory cell region 101 has a gate region 105. Thereafter, an insulating layer is formed on the substrate 100 of the memory cell region to form the gate dielectric layer 102, and a gate dielectric layer is formed on the substrate (10) of the peripheral circuit region 1 () 3. The t-material which is carried by the dielectric layer and the gate dielectric layer 1〇4 is, for example, oxidized chopping, and the formation methods of the two are well known to those skilled in the art and will not be described herein. In addition, the thickness of the pass-through dielectric layer 102 is not the same as the thickness of the gate dielectric layer 1〇4. Next, a conductor layer 106 is formed on the substrate 100. The material of the conductor layer 1 〇 6 is, for example, doped polycrystalline dicing. The method for forming the conductor layer 1〇6 is, for example, a chemical vapor deposition process to form an undoped polysilicon layer, which is formed by 200917422 丄itwf.doc/p; or a chemical vapor deposition process may be used. After the formation, the ion implantation process is performed, and the method of implanting the dopant is in-situ.

Subsequent to the substrate (10), an M insulating layer is turned into an open dielectric layer (10). The material of the dielectric layer (10) is, for example, ZnO. The method for forming the dielectric layer 1G8 is, for example, first forming a first layer of oxygen (four) layer on the conductor layer (10) by thermal oxidation, and then performing a chemical vapor deposition process to form a layer of nitrogen nitride on the oxygen layer. Then, a second layer of oxygen cut layer is formed on the nitrogen cut layer. #然, (4) of the dielectric layer (10) of the gate is also an oxygen-cut, oxygen-like material other dielectric material. Thereafter, referring to Fig. 1B, a patterned mask layer 11G is formed on the substrate 1 of the memory cell region 1〇1. The patterned mask layer 11() is, for example, a patterned photoresist layer that exposes at least a portion of the gate layer (10) of the selected gate region 1〇5 in the memory cell region 1〇1 and the gate of the peripheral circuit region (10). Inter-dielectric layer 108.

Then, the patterned mask layer H is used as a mask to perform the engraving process, and the exposed inter-gate dielectric layer 1〇8 is removed to expose the conductor layer 1〇6. Next, referring to FIG. 1C, the patterned mask layer 110 is removed. The method of removing the patterned mask layer 110 is, for example, a patterning of the mask layer 110 by oxygen plasma ashing, followed by a wet cleaning process. Next, a conductor layer 112 is formed on the substrate 100, and the conductor layer ι12 covers the inter-gate dielectric layer 108 and the exposed portion of the conductor layer 1〇6. Similarly, the material of the conductor layer 112 and the formation method are the same as, for example, the conductor layer ι 6 12 . itwf.doc/p. Subsequently, a hard mask layer 116 is formed on the substrate 100. The material of the hard mask layer 116 is, for example, oxidized stone, which is formed, for example, by chemical vapor deposition using tetraethyl oxalate (TEOS) as a reaction gas. In one embodiment, a metal telluride layer 114 may also be selectively formed over the conductor layer 112 to reduce the resistance of the component. The material of the metal telluride layer 114 is, for example, tungsten telluride, titanium telluride, cobalt telluride, antimony telluride, nickel telluride, platinum telluride or palladium telluride. The method of forming the metal telluride layer 114 is, for example, a chemical vapor deposition process.

200917422 Next, referring to FIG. 1D, a patterning process is performed to form the hard mask layer 116, the metal telluride layer 114, the conductor layer 112, the inter-gate dielectric layer 108, and the conductor layer i〇6ffi of the memory cell region 101. The selection gate structure 120 is formed on the substrate 1A on which the plurality of inter-stack structures 118 are formed and on the gate region 1〇5. The stacked gate structure 118 is formed by the conductor layer 106, the inter-gate dielectric layer, the conductor layer 112, the metal-lithium layer 1U and the hard mask layer 116 from the substrate 1 in this order. Wherein, the conductor layer acts as a floating gate, and the conductor layer 112 forms a control gate with the metal telluride layer ΐ4. In addition, the selective gate structure 12〇 located in the positive electrode region is used as the selection gate (4) sinking (4). The above-mentioned stacked gate structure 118 and the dielectric layer 1〇2 and the optional dielectric layer 12〇 and the dielectric layer 1〇2 constitute a non-volatile memory in the non-volatile memory. In addition, when the upper speed patterning process is advanced, the hard mask layer 116 of the road area 103, the whole genus β 9 U, and the body layer 114 of the tomb 1 and the body layer of the conductor layer 11 are patterned. To form a stacked gate 13 200917422 !twf.doc / p pole structure 122 and gate dielectric layer 104 constitute a transistor in the peripheral circuit region of the non-volatile memory. It should be noted that, in this embodiment, the selective gate structure 120 illustrated in FIG. 1D is taken as an example for illustration and is not intended to limit the present invention. In other embodiments, the select gate structure can also have different configurations and methods. For example, in the step of Fig. 2B, the select gate region of the selected gate region 1〇5 can be removed. The select gate structure formed by the entire gate dielectric layer does not include the gate dielectric layer. Next, please continue to refer to FIG. 1E to FIG. 1H. In these figures, only the memory cell region 1G1 is explained, and the money is shown to show the peripheral circuit region 103. Next, please refer to 1E' in the stacked gate structure. Ιΐ8 and select the pole::I20 domain, then 'the material that forms the oxide layer 124 at the gate of the stacked gate structure 118, for example, is oxidized and chopped, and the formed square 4 screen is oxidized by the order ((4).) )Process. The above-mentioned oxygen rhyme is that (4) the stacked gate structure 118 does not follow the dielectric ί 1F ' removes both sides of the stacked gate structure 118 in the subsequent process until the substrate is exposed. The above removal process. The method of this ^_^ is, for example, to carry out the _ing back) layer without damage. Selecting the gate region 105 of the heart °α 01 to buckle the film, please refer to FIG. 1G to form an epitaxial material on the substrate 100 exposed on the sides of the stacked gate structure 118 200917422 ▲ ltwf.doc/p Layer 126. The material of the epitaxial material layer 126 is, for example, an epitaxial germanium, and the formation method thereof is, for example, a selective epitaxial growth process (SEG process). The selective epitaxial growth process techniques herein are well known to those of ordinary skill in the art and will not be described again. In addition, in the uranium forming the epitaxial material layer 126, impurities in the surface of the substrate 100 may be removed by performing a pre-cleaning step η to improve the film quality of the epitaxial material layer 126. + Then, referring to FIG. 1H, after forming the epitaxial material layer 26, an ion implantation process 128' is performed to form the doping region 130 in the substrate germanium (8). At this time, the ion implantation process 128 also implants a dopant in the epitaxial material layer i26 to be converted into a doped epitaxial material layer 132. Subsequent revisiting of the component requirements is followed by a generally familiar process step, which is well known in the art and will not be described again.

In other embodiments, in the steps of FIG. 1E to FIG. 1 (3), when the oxide layer 丨 24 is formed on the sidewalls of the stacked gates and the structures 118, the side walls of the pole structure 12 〇 may also be formed at the same time. Oxide layer 124. Next, when the dielectric layer 1〇2 on both sides of the stack structure 118 is removed, the pass-through dielectric layer 1〇2 on both sides of the selection structure 120 can also be removed at the same time. Then, on the stack When the base 100 on both sides of the jm is formed into the layer 126 of the remote crystal material, the formation of the stray crystal material on the substrate on both sides of the gate structure 12G may be particularly important for the source/drain region. The doped region 'the memory element of the present embodiment is formed into a layer of epitaxial material on the substrate of 15 200917422 * itwf.doc/p by using a selective stray growth process. Therefore, the memory device can be deepened. The shallower source/drain junction (s〇urce/drain junction, S/D juncti〇n) can more effectively avoid the problem of electrical punching, without the conventional ring implant (hai〇impiantati〇n) and other anti-breakdown implant processes, and can improve the reliability of the component. Next, take Figure 1H The non-volatile memory cell and the NAND-type non-volatile memory of the present invention will be described below. The description of the materials and the like of the respective components of the device may be omitted as follows. Referring again to FIG. 1H, the component structure of the present invention includes a substrate. a plurality of stacked gate structures H8, a selected gate structure 120, an oxide layer 124, an insulating layer 102, a doped epitaxial material layer 132, and a doped region 130. The substrate 100 has a selected gate region 1〇5. A plurality of stacked gate structures 118 are disposed in series on the substrate 1 , and a gate structure 12 is disposed on the substrate 1 选择 of the selected gate regions 1 〇 5 on both sides of the stacked gate structures 118. The stacked gate structure 118 is sequentially provided from the substrate 1 to the conductor layer 106, the inter-gate insulating layer 108, the conductor layer 112, the metal telluride layer 114 and the hard mask layer U6. The oxide layer 124 of this embodiment is configured. The sidewalls of the gate structure 118 are stacked. The insulating layer 102 is disposed between the stacked gate structure 118, the substrate 1 and the oxide layer 124, and is disposed between the selected gate structure 12A and the substrate 1? Epitaxial material layer 132 is disposed in the stack The substrate is stacked on both sides of the gate structure 118. The doped regions 130 are disposed on both sides of the stacked gate structure 118 and in the substrate on both sides of the gate structure 120. In addition, in other embodiments, the oxide layer 124 It can also be disposed at the side wall of the 16 200917422 itwf.doc/p pole structure m. Moreover, the layer of the impurity crystal material m is also 5% disposed on the substrate 丨(8) on both sides of the gate structure 〗2 。. As described above, the method of the present invention and the (4) element can further reduce the depth of the source-level junction by using the crystal layer (four) layer of the crystal crystal material to achieve the integration of the components and improve the reliability of the component. The purpose. </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; The scope of protection of the present invention is therefore defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A to FIG. 1H are schematic diagrams showing a manufacturing process of a non-volatile simon memory according to an embodiment of the present invention. [Main component symbol description] 100 · Substrate 101 : Memory cell region 103 : Peripheral circuit region 105 : Select gate region 102 : Tunneling dielectric layer 104 : Gate dielectric layer 106 , 112 : Conductor layer 108 : Gate device Electrical layer 110: patterned mask layer 1H: metal telluride layer 17 !twf.doc/p 200917422 116: hard mask layer 118, 122: stacked gate structure 120: selective gate structure 124: oxide layer 126 · remote Crystal material layer 128: ion implantation process 130: doped region 13 2 . replacement of the remote crystal material layer

18

Claims (1)

!twf.doc/p 直Οu to 200917422 X. Patent application scope: 1. A method for fabricating non-volatile memory cells, including: sequentially forming on-substrate-insulation layer,------- An insulating layer, a second conductor 35 and a hard mask layer; 3 the first layer of the mask layer, the first conductor layer, the insulating layer and the cold layer to form a stacked gate structure; The insulating layer on the substrate on both sides of the exposed structure forms a layer of epitaxial material on the exposed substrate; and an ion implantation process is formed in the substrate - and the layer of the german crystal material is converted into - Doping the layer of crystalline material. The method for forming the non-volatile memory cell of the non-volatile memory cell described in the above-mentioned patent specification (4), includes the non-volatile memory cell of the first aspect of the patent range. The method of removing the portion of the insulating layer until the surface of the substrate is exposed includes performing an etching process. The method for producing non-volatile memory cells according to item 1 of the patent scope of the invention, the method of forming the oxide layer includes performing a reoxidation process. You are ancient, 5. If you want to use the method of non-window memory cells, which is included in the side of the stacked gate structure after the stacked gate structure and before removing part of the insulating layer The wall forms an oxide layer. The 乍 method is performed after the impurity portion of the opaque layer, before the eutectic material 19 &gt; twf.doc/p 200917422 layer, and further includes a pre-cleaning step. 7. The method according to claim i, wherein the material of the first conductor layer comprises doping: 肊眺 8. The method according to claim i of claim i, wherein The material of the second conductor layer comprises a doped cell coating. The material of the second conductor layer comprises a guide. It consists of a 衣 脃 Ο Ο 夕 化物 layer. I include a layer of a conductor material and a metal-type non-volatile memory cell, comprising: a substrate; a stacking gate subtraction, arranged in a silk red, the towel structure including the substrate up to the order is the first _ ° ° layer, the second conductor layer and the hard mask i layer layer, the gate insulating structure of the insulating layer, disposed on the substrate, the oxide layer and the stacked gate junction base mi crystal material The middle of the stack (four) pole structure. The one impurity region is disposed on the substrate under the layer of doped insect crystal material to further encapsulate the non-volatile memory cell described in the item _ ig, and the germanium layer is disposed on the sidewall of the stacked gate structure. In the non-volatile memory cell described in item 1G of the patent scope, the material of the ', ° conductor layer includes doped polysilicon. The non-volatile memory cell according to the first aspect of the patent application, 20 itwf.doc/p 200917422 wherein the material of the second conductor layer comprises doped polysilicon. The first memory layer of the group 1G includes a conductive material layer and a metal lithium layer 15. The NANDH transmissive memory is provided by the substrate, and the substrate has a substrate. Selecting a gate region; · Ο 基底 a substrate is formed to form a ray, a first-conductor layer, and a region (four) is a dielectric layer, and the substrate is covered with a dielectric layer (4) and a layer covering the gate dielectric layer and Exposed: 兮 the first hard mask layer, the second conductor layer, the inter-gate insulating layer and the second to form a plurality of stacked gate structures, and at the same time, the selection gate is shouting-surface idle structure; The method of making a memory of the NAND type non-volatile 21 2 twf.doc/p 200917422 memory as described in claim 15 of the patent application, wherein the stupid one Selective epitaxial growth process. a method of forming a layer of crystalline material includes A non-volatile &amp; method of claim 15, wherein the method of removing a portion of the rim layer until the surface of the substrate is exposed comprises a smear- (10) engraving process. ^ μ. The method for forming a non-volatile hexa-L-body of the NANDs as described in claim 15 of the invention, the method for forming the oxide layer, is a reoxidation process.仃 19. The method for manufacturing a non-memory type according to claim 15, wherein the towel is included in each of the stalks after the smashing of the lion red, and before removing the insulating layer. The sidewalls of the stacked interrogation structure form an oxide layer. σ二20. The method for fabricating a NAND type non-volatile C memory material according to claim 15 of the patent application, wherein the towel comprises a pre-preparation after the edge portion (10) is removed and the epitaxial material layer is formed. Cleaning steps. 21. The method of fabricating a NAND type non-volatile read body according to claim 15 of the invention, wherein the material f of the first conductor layer comprises doped polycrystalline stone. The method for fabricating the NAND type non-volatile memory of the present invention is characterized in that the material f of the second conductor layer comprises a bonded polycrystalline bite. 2. The method of fabricating a NAN D-type non-volatile k' body as described in claim 15 wherein the second conductor layer comprises a layer of a conductive material and a layer of a metal halide. 24. A NAND type non-volatile memory comprising: 22 2twf.doc/p 200917422 a substrate having a select gate region; a plurality of stacked gate structures and a select gate structure, wherein the stacks The gate structure is disposed in series on the substrate, the select gate structure is disposed on the substrate of the select gate region on both sides of the stacked gate structures, and each of the stacked gate structures comprises the substrate Upwardly, a first 'body layer, a gate insulating layer, a second conductor layer and a hard mask layer; = an insulating layer disposed on each of the stacked gate structures, the substrate and the Between the oxide layers, and between the selected gate structure and the substrate; a doped epitaxial material layer disposed on both sides of each of the stacked gate structures and the substrate on both sides of the selected gate structure And a doped region disposed in the substrate on both sides of each of the stacked gate structures and on both sides of the k-gate structure.士立25· NAND type non-volatile Si as described in claim 24 of the patent application. Further comprising an oxide layer disposed in each of the stacked gate structures Record the non-volatile wall of the _° type described in item 25 of the patent application. The material of the NAND type non-volatile &quot;78 k first conductor layer described in item 24 of the memory structure of the selected gate structure includes the doped polysilicon. Memory, Fan Lai-Shun NA_Non-Volatile The material of the body layer consists of doped polysilicon. Memory, the item is similar to _ non-volatile, the layer of stone, and the layer of the conductor (four) and the metal 23