CN111244104B - SONOS memory and manufacturing method thereof - Google Patents
SONOS memory and manufacturing method thereof Download PDFInfo
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- CN111244104B CN111244104B CN202010231443.7A CN202010231443A CN111244104B CN 111244104 B CN111244104 B CN 111244104B CN 202010231443 A CN202010231443 A CN 202010231443A CN 111244104 B CN111244104 B CN 111244104B
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/50—EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
Abstract
The invention provides a SONOS memory and a manufacturing method thereof. The manufacturing method of the SONOS memory comprises the steps of providing a semiconductor substrate, etching an ONO layer, a gate oxide layer and a gate material layer which are sequentially formed on the semiconductor substrate to obtain a storage tube gate stack and a selection tube gate stack, forming side walls on the side surfaces of the gate stacks, forming an epitaxial layer on the surface of the exposed semiconductor substrate, and forming a metal silicide layer on the surface of the epitaxial layer and the upper surfaces of the storage tube gate stack and the selection tube gate stack. Because the metal silicide layer is formed on the epitaxial layer, the metal silicide layer and the channel region under each grid electrode lamination are not in the same height, the electric leakage of the channel region of the memory caused by the expansion of the metal silicide can be avoided, the problem of memory failure caused by the electric leakage interference of the channel region can be avoided, and the reliability and the production yield of the SONOS memory can be improved. The invention also provides a SONOS memory.
Description
Technical Field
The invention relates to the field of semiconductors, in particular to a SONOS memory and a manufacturing method thereof.
Background
Flash memory (Flash memory) is a non-volatile memory developed based on erasable programmable read-only memory (EPROM) and electrically erasable programmable read-only memory (EEPROM), and has the characteristics of low price, relatively simple process, convenience and rapidness in performing multiple erasures, and has been widely used in the memory field since the advent of the Flash memory. However, since the flash memory having the floating gate structure requires high voltage operation during the read-write and erase processes, the Complementary Metal Oxide Semiconductor (CMOS) does not require high voltage operation, and the flash memory has a double-layer polysilicon structure having a floating gate and a control gate, and the CMOS has a single-layer polysilicon structure, the integration of the flash memory and the CMOS device is difficult and the process is complicated. The SONOS (Silicon-Oxide-Nitride-Oxide-Silicon) technology can be well compatible with the CMOS technology, so long as the SONOS memory is embedded on the basis of a logic platform, the operation voltage of the SONOS memory is low, the cost is low, and the SONOS memory has great competitiveness in the aspects of manufacturing, use and cost.
Fig. 1 is a schematic cross-sectional view of a SONOS memory device. As shown in fig. 1, the SONOS memory includes a semiconductor substrate 101, a surface of the semiconductor substrate 101 includes a memory region 101a, a selection region 101b, and an inter-node region 101c between the memory region 101a and the selection region 101b, a memory tube gate stack including an ONO (Oxide-Nitride-Oxide) layer 102 and a first gate material layer 104a is formed on the surface of the memory region 101a, a selection tube gate stack including a gate Oxide (IO gate Oxide) 103 and a second gate material layer 104b is formed on the selection region 101b, and a metal Silicide layer (silicon) 106 is formed on the inter-node region 101 c. In the SONOS memory manufacturing process, the ONO layer 102 in the memory tube gate stack and the gate oxide layer 103 in the select tube gate stack are separately formed through a plurality of processes, including a plurality of surface cleaning and etching processes, the silicon on the semiconductor substrate surface of the select tube region 101b is consumed, so that the semiconductor substrate surface of the select tube region 101b is slightly lower than the semiconductor substrate surface of the memory tube region 101a, i.e., the semiconductor substrate surface uneven region of the internode region 101c, and a step shape exists. The inventor researches and discovers that, due to uneven surface of the internode region, such as black circle position in fig. 2a and 2b, the metal Silicide layer formed on the internode region is easy to generate metal Silicide extension (Silicide pinning), namely, the metal Silicide is easy to diffuse and extend to the channel region under the storage tube gate stack and the selection tube gate stack, the PN junction formed at the edge of the channel region is damaged, so that the electric leakage of the channel region is increased, the SONOS memory can fail due to electric leakage interference, the reliability of the SONOS memory is reduced, and the production yield is also affected.
Disclosure of Invention
The invention provides a SONOS memory and a manufacturing method thereof, which are used for solving the problem that the SONOS memory fails due to leakage interference because of the increase of leakage of a channel region of the SONOS memory caused by the expansion of metal silicide on an internode region.
In order to solve the above problems, an aspect of the present invention provides a method for manufacturing a SONOS memory, where the method for manufacturing a SONOS memory includes:
providing a semiconductor substrate, wherein the surface of the semiconductor substrate comprises a storage area, a selection area and an internode area positioned between the storage area and the selection area, an ONO layer is formed on the surface of the semiconductor substrate in the storage area, a gate oxide layer is formed on the surface of the semiconductor substrate in the selection area, the ONO layer is connected with the gate oxide layer in the internode area, a gate material layer is further formed on the surface of the semiconductor substrate, and the gate material layer covers the surfaces of the ONO layer and the gate oxide layer;
etching the grid material layer, the ONO layer and the grid oxide layer until the surface of the semiconductor substrate is exposed, obtaining a storage tube grid stack in the storage tube region, and obtaining a selection tube grid stack in the selection tube region;
forming side walls on the side surfaces of the storage tube grid electrode lamination and the selection tube grid electrode lamination;
performing an epitaxial process, and forming an epitaxial layer on the exposed surface of the semiconductor substrate; and
and performing a silicide process, and forming a metal silicide layer on the surface of the epitaxial layer and the upper surfaces of the storage tube gate stack and the selection tube gate stack.
Optionally, the manufacturing method of the SONOS memory further includes:
before the etching process is executed, a hard mask layer is formed on the surface of the grid electrode material layer, and graphical treatment is carried out on the hard mask layer; and
the hard mask layer on the surfaces of the memory tube gate stack and the select tube gate stack is removed after the epitaxial process is performed and before the silicide process is performed.
Optionally, after the silicide process is performed, the metal silicide layer is located on the epitaxial layer and upper surfaces of the gate material layers in the memory tube gate stack and the select tube gate stack.
Optionally, after the etching process is performed and before the side wall is formed, the method for manufacturing the SONOS memory further includes:
and performing ion implantation to form shallow doped ion implantation areas in the semiconductor substrate at two sides of the storage tube gate stack and the selection tube gate stack.
Optionally, the thickness of the epitaxial layer is 35 nm-55 nm.
Optionally, the step of performing the silicide process to form a metal silicide layer on the surface of the epitaxial layer and the upper surfaces of the memory tube gate stack and the select tube gate stack includes:
depositing a patterned protective layer on the semiconductor substrate, wherein the protective layer exposes the surface of the epitaxial layer and the upper surfaces of the storage tube gate stack and the selection tube gate stack;
forming a metal material layer on the semiconductor substrate;
performing an annealing process to form the metal silicide layer; and
and removing the remaining metal material layer.
Optionally, the protective layer includes a silicon oxide layer and a silicon nitride layer formed by sequentially stacking.
Optionally, the hard mask layer is a silicon oxide layer or a silicon nitride layer.
Optionally, the metal silicide layer includes one or a combination of more than two of NiSi, tiSi, coSi and WSi.
Another aspect of the present invention also provides a SONOS memory device, the SONOS memory device comprising:
the semiconductor substrate comprises a storage tube region, a selection tube region and an internode region positioned between the storage tube region and the selection tube region;
the storage tube grid structure is positioned in the storage tube region and comprises an ONO layer, a first grid material layer and a side wall, wherein the ONO layer and the first grid material layer are sequentially overlapped on the surface of the semiconductor substrate, and the side wall covers the side surfaces of the ONO layer and the first grid material layer;
the selective tube grid structure is positioned in the selective tube region and comprises a grid oxide layer and a second grid material layer which are sequentially overlapped on the surface of the semiconductor substrate, and a side wall covering the side surfaces of the grid oxide layer and the second grid material layer;
an epitaxial layer, which is positioned in a gap between the storage tube grid structure and the selection tube grid structure and covers the surface of the semiconductor substrate of the internode region; and
and the metal silicide layer covers the surface of the epitaxial layer and the surfaces of the first gate material layer and the second gate material layer.
The manufacturing method of the SONOS memory comprises the steps of forming an epitaxial layer on the surface of a semiconductor substrate which is not covered by a storage tube grid electrode lamination, a selection tube grid electrode lamination and a side wall, wherein the epitaxial layer covers the surface of the semiconductor substrate of the internode region, and then forming a metal silicide layer on the surface of the epitaxial layer. Because the epitaxial layer is formed on the surface of the semiconductor substrate, the upper surface of the epitaxial layer is higher than the surface of the semiconductor substrate, and the metal silicide layer is formed on the epitaxial layer, so that the metal silicide layer is higher than the surface of the semiconductor substrate, meanwhile, because the channel region under the storage tube grid lamination and the selection tube grid lamination is positioned on the surface of the semiconductor substrate and below the surface of the semiconductor substrate, the metal silicide layer and the channel region are not at the same height, and meanwhile, because the PN junction is formed at the edge of the channel region, the PN junction at the edge of the channel region is not damaged even if the metal silicide layer is expanded, the problem of leakage of the channel region of the memory caused by expansion of the metal silicide can be effectively avoided, so that the memory failure caused by interference of leakage of the channel region can be avoided, and the reliability and the production yield of the SONOS memory can be improved.
In addition, the epitaxial layer of the SONOS memory provided by the invention is positioned in the gap between the memory tube grid structure and the selective tube grid structure, and the epitaxial layer covers the surface of the semiconductor substrate of the internode region, so that the surface of the epitaxial layer is higher than the surface of the semiconductor substrate, and meanwhile, the metal silicide layer covers the surface of the epitaxial layer, so that the metal silicide layer is higher than the surface of the semiconductor substrate, and the channel region under the memory tube grid structure and the selective tube grid structure is positioned below the surface of the semiconductor substrate, so that the metal silicide layer and the channel region are not positioned at the same height and higher than the channel region, the electric leakage of the channel region caused by the expansion of the metal silicide can be avoided, the memory failure caused by the leakage interference of the channel region can be avoided, and the reliability and the production yield of the SONOS memory are improved.
Drawings
Fig. 1 is a schematic cross-sectional view of a SONOS memory device.
Fig. 2a and 2b are cross-sectional SEM images of the metal silicide layer of the SONOS memory device internode region of fig. 1 at different magnifications.
Fig. 3a to 3d are schematic cross-sectional views of the SONOS memory device of fig. 1 during fabrication.
Fig. 4 is a flowchart of a method for fabricating a SONOS memory device according to an embodiment of the present invention.
Fig. 5a to 5f are schematic cross-sectional views of a SONOS memory device according to an embodiment of the present invention during fabrication.
Reference numerals illustrate:
a semiconductor substrate; 101 a-a memory cell region; 101 b-select tube region; 101 c-internode; 102-ONO layer; 103-gate oxide; 104-a layer of gate material; 104 a-a first gate material layer; 104 b-a second gate material layer; 105-side walls; 106-a metal silicon compound; 107-a hard mask layer; 108-an epitaxial layer; 109-a memory tube gate stack; 110-select tube gate stack.
Detailed Description
The SONOS memory device and the method for fabricating the same according to the present invention are described in further detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention. For clarity, in all the drawings for assisting in the description of the embodiments of the present invention, the same reference numerals are given to the same components in principle, and the repetitive description thereof will be omitted.
It will be understood that when an element or layer is referred to as being "on," "adjacent," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent, connected, or coupled to the other element or layer, or intervening elements or layers may be present. It should be further understood that the terms "first," "second," "third," and the like in this specification are used merely for distinguishing between various components, elements, steps, etc. in the specification and not for indicating a logical or sequential relationship between the various components, elements, steps, etc., unless otherwise indicated. It must be noted that, as used in the specification and the appended claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. For example, reference to "a step" or "an apparatus" means a reference to one or more steps or apparatuses, and may include sub-steps as well as sub-apparatuses. All conjunctions used should be understood in the broadest sense. And, the word "or" should be understood as having the definition of a logical "or" rather than a logical "exclusive or" unless the context clearly indicates the contrary.
Fig. 3a to 3d are schematic cross-sectional views of the SONOS memory device of fig. 1 during fabrication. As shown in fig. 1 and fig. 3a to fig. 3d, in order to more clearly illustrate the characteristics and advantages of the SONOS memory device and the method for manufacturing the same, the following description first describes a conventional method for manufacturing a SONOS memory device.
As shown in fig. 3a, the fabrication method of the SONOS memory device includes the first steps of: a semiconductor substrate 101 is provided, the semiconductor substrate 101 includes a memory region 101a, a selection region 101b, and an inter-node region 101c located between the memory region 101a and the selection region 101b, an ONO layer 102 is formed on a semiconductor substrate surface of the memory region 101a, a gate oxide layer 103 is formed on a semiconductor substrate surface of the selection region 101b, the ONO layer 102 and the gate oxide layer 103 are in contact with each other at the inter-node region 101c, a gate material layer 104 is further formed on a surface of the semiconductor substrate 101, and the gate material layer 104 covers surfaces of the ONO layer 102 and the gate oxide layer 103.
As shown in fig. 3b, the fabrication method of the SONOS memory device includes the second steps of: and coating photoresist on the surface of the gate material layer 104, exposing the part of the gate material layer to be etched by performing exposure and development processes, etching the gate material layer 104 by adopting a dry etching process, and stopping dry etching on the surface of the ONO layer 102 and the surface of the gate oxide layer 103 to obtain a first gate material layer 104a of the memory area 101a and a second gate material layer 104b of the selective area 101 b.
As shown in fig. 3c, the fabrication method of the SONOS memory device includes a third step: performing memory Cell etching (Cell Drain Etch), etching the ONO layer 102 and the gate oxide layer 103 until the surface of the semiconductor substrate 101 is exposed, obtaining a memory tube gate stack 109 in the memory tube region 101a, and obtaining a select tube gate stack 110 in the select tube region 101 b; a lightly doped ion implantation (LDD IMP) is performed to form lightly doped ion implanted regions in the semiconductor substrate on both sides of the memory Guan Shanji stack 109 and the select tube gate stack 110.
As shown in fig. 3d, the fabrication method of the SONOS memory device includes a fourth step: side walls 105 are formed on the sides of the memory tube gate stack 109 and the select tube gate stack 110.
As shown in fig. 1, the method for manufacturing the SONOS memory device includes a fifth step: a metal silicide layer 106 is formed on the surface of the semiconductor substrate 101, the memory tube gate stack and the upper surface of the select tube gate stack exposed between the sidewalls 105, the metal silicide layer electrically connecting the first gate material layer and the second gate material layer.
The metal silicide layer between the side walls of the SONOS memory manufactured by the manufacturing method of the SONOS memory is at the same height as the storage tube grid layer stack and the channel region below the selection tube grid layer stack, and because the surface of the semiconductor substrate of the internode region is of uneven step morphology, the metal silicide layer formed on the internode region is easy to spread, namely, the metal silicide is easy to spread and extend to the channel region below the storage tube grid layer stack and the selection tube grid layer stack, and the metal silicide spreading can damage PN junctions formed at the edges of the channel region, so that the leakage of the channel region is increased, the SONOS memory can fail due to leakage interference, the reliability of the SONOS memory is reduced, and the production yield is also affected.
Fig. 4 is a flowchart of a method for fabricating a SONOS memory device according to an embodiment of the present invention. In order to solve the problem that the channel region of the SONOS memory is increased due to the extension of the metal silicide on the internode region and the SONOS memory is failed due to leakage interference, the embodiment provides a method for manufacturing the SONOS memory, as shown in fig. 4, which includes the following steps.
Step S1: providing a semiconductor substrate, wherein the surface of the semiconductor substrate comprises a storage area, a selection area and an internode area positioned between the storage area and the selection area, an ONO layer is formed on the surface of the semiconductor substrate in the storage area, a gate oxide layer is formed on the surface of the semiconductor substrate in the selection area, the ONO layer is connected with the gate oxide layer in the internode area, a gate material layer is further formed on the surface of the semiconductor substrate, and the gate material layer covers the surfaces of the ONO layer and the gate oxide layer.
Step S2: and executing an etching process, namely etching the grid material layer, the ONO layer and the grid oxide layer until the surface of the semiconductor substrate is exposed, obtaining a storage tube grid stack in the storage tube region, and obtaining a selection tube grid stack in the selection tube region.
Step S3: and forming side walls on the side surfaces of the storage tube grid electrode lamination and the selection tube grid electrode lamination.
Step S4: and performing an epitaxial process, and forming an epitaxial layer on the exposed surface of the semiconductor substrate.
Step S5: and performing a silicide process, and forming a metal silicide layer on the surface of the epitaxial layer and the upper surfaces of the storage tube gate stack and the selection tube gate stack.
Fig. 5a to 5f are schematic cross-sectional views of a SONOS memory device according to an embodiment of the present invention during fabrication. The following describes the fabrication method of the SONOS memory device of the present embodiment in detail with reference to fig. 5a to 5 f.
In order to prevent an epitaxial layer (EPI) from being formed on the upper surface of the gate material layer, the fabrication method of the SONOS memory of the present embodiment may further include forming a hard mask layer on the surface of the gate material layer before the etching process is performed, performing a patterning process on the hard mask layer, and performing the etching process with the patterned hard mask layer as a mask; the hard mask layer on the surfaces of the memory tube gate stack and the select tube gate stack is removed after the epitaxial process is performed and before the silicide process is performed. In this embodiment, the gate material layer may be a polysilicon layer. Because the hard mask layer is formed on the upper surface of the gate material layer, when the epitaxial process is executed, the hard mask layer can isolate and protect the silicon surface of the gate material layer, an epitaxial layer can not be formed on the upper surface of the gate material layer in the storage tube gate stack and the selection tube gate stack, the problem that the performance of the gate material layer is affected due to the formation of the epitaxial layer on the surface of the gate material layer can be avoided, and the good performance of the polysilicon gate in the SONOS memory can be maintained.
Specifically, as shown in fig. 5a, the surface of the semiconductor substrate 101 includes a memory region 101a, a selection region 101b, and an inter-node region 101c between the memory region 101a and the selection region 101b, the ONO layer 102 is formed on the semiconductor substrate surface of the memory region 101a, the gate oxide layer 103 is formed on the semiconductor substrate surface of the selection region 101b, the ONO layer 102 and the gate oxide layer 103 are in contact with each other at the inter-node region 101c, the gate material layer 104 is further formed on the semiconductor substrate 101, the surfaces of the ONO layer 102 and the gate oxide layer 103 are covered by the gate material layer 104, the hard mask layer 107 is formed on the surface of the gate material layer 140, and the gate material layer 104 is covered by the hard mask layer 107. In the process of forming the ONO layer and the gate oxide layer, the semiconductor substrate is subjected to a plurality of cleaning and etching processes, so that a certain height difference exists between the surface of the semiconductor substrate in the memory area forming the ONO layer and the surface of the semiconductor substrate in the selective area forming the gate oxide layer, and therefore the surface of the semiconductor substrate in the internode area is uneven and has a step shape.
In this embodiment, the semiconductor substrate may be a silicon substrate, and may be a P-type substrate or an N-type substrate, however, in other embodiments, the semiconductor substrate may also be a sige substrate, an SOI (silicon on insulator ) substrate, or the like, and certain doped particles may be implanted into the semiconductor substrate according to design requirements to change electrical parameters. The ONO layer may be a sandwich structure of silicon oxide-silicon nitride-silicon oxide, and the ONO layer may be another oxide-nitride-oxide structure in other embodiments, and the gate oxide layer may be a silicon oxide layer. The hard mask layer in this embodiment may be a silicon oxide layer or a silicon nitride layer, however, in other embodiments, the hard mask layer may be another silicide or a dual-layer structure formed by stacking a silicon oxide layer and a silicon nitride layer, so long as the formation of an epitaxial layer on the polysilicon gate material layer is prevented. The silicon oxide layer may be formed using a Low Pressure Radical Oxidation (LPRO) process, a Chemical Vapor Deposition (CVD) process, or a furnace tube oxidation process, which are well known to those skilled in the art, and the silicon nitride layer may be formed using an Atomic Layer Deposition (ALD) process, a Physical Vapor Deposition (PVD) process, a Chemical Vapor Deposition (CVD) process, a Low Pressure Chemical Vapor Deposition (LPCVD) process, a plasma-assisted chemical vapor deposition (PECVD) process, or using an electron cyclotron resonance sputtering process.
In this embodiment, etching the gate material layer, the ONO layer and the gate oxide layer with the patterned hard mask layer as a mask may include multi-step etching and a combination of multiple etching processes.
Specifically, after the hard mask layer is deposited and patterned, as shown in fig. 5b, the patterned hard mask layer 107 is used as a mask to etch the gate material layer 104, and a dry etching process may be used to etch the gate material layer, where the dry etching is stopped on the surface of the ONO layer 102 and the surface of the gate oxide layer 103, so as to obtain a first gate material layer 104a in the storage area 101a and obtain a second gate material layer 104b in the selection area 101 b.
Continuing to etch the semiconductor substrate, as shown in fig. 5c, performing a memory Cell etch (Cell Drain ET), and etching the ONO layer 102 and the gate oxide layer 103 until the surface of the semiconductor substrate 101 is exposed, obtaining a memory tube gate stack 109 in a memory tube region, and obtaining a selection tube gate stack 110 in a selection tube region, where the memory tube gate stack 109 includes a first gate material layer 104a and a remaining ONO layer 102, and the selection tube gate stack 110 includes a second gate material layer 104b and a remaining gate oxide layer 103. In this embodiment, the oxide layer close to the first gate material layer and the gate oxide layer with partial thickness in the ONO layer may be removed by wet etching, then the silicon nitride layer in the ONO layer is removed by dry etching, the dry etching is stopped on the oxide layer close to the surface of the semiconductor substrate in the ONO layer, and finally the oxide layer close to the surface of the semiconductor substrate in the ONO layer and the remaining gate oxide layer may be removed by wet etching. However, in other embodiments, if the patterned hard mask layer is not used as a mask, a photoresist layer may be coated on the gate material layer, then the photoresist layer is patterned, the patterned photoresist layer is used as a mask to etch the gate material layer, the ONO layer and the gate oxide layer, and then the photoresist layer is removed after etching.
With continued reference to fig. 5c, after forming the memory tube gate stack 109 and the select tube gate stack 110, the method for fabricating a SONOS memory device of the present embodiment may further include performing an ion implantation process to form lightly doped ion implantation regions in the semiconductor substrate on both sides of the memory tube gate stack 109 and the select tube gate stack 110. It should be noted that, forming the source region and the drain region on the semiconductor substrate may include multiple ion implantation processes, where the formation of the shallow doped ion implantation regions in the semiconductor substrate at both sides of the storage Guan Shanji stack and the select tube gate stack is only a part of the processes, and further, deep ion implantation may be performed in the source/drain formation region to form the source/drain region of the SONOS memory, and a PN junction may be formed at the interface between the source/drain region and the channel region.
As shown in fig. 5d, after forming the lightly doped ion implantation region, the fabrication method of the SONOS memory device of the present embodiment includes forming the sidewall 105 on the sides of the storage tube gate stack 109 and the select tube gate stack 110. The sidewall 105 may protect the respective gate stack from impact and damage during subsequent memory fabrication. The side wall may be a single-layer structure, such as a single-layer silicon nitride layer, or a multi-layer structure, such as a three-layer stacked structure of silicon oxide-silicon nitride-silicon oxide.
After forming the side wall, as shown in fig. 5e, the fabrication method of the SONOS memory device of the present embodiment includes performing an epitaxial process, and forming an epitaxial layer 108 on the exposed surface of the semiconductor substrate 101. The epitaxial layer covers the exposed surface of the semiconductor substrate, so that the surface of the semiconductor substrate of the internode region is covered by the epitaxial layer, the formed epitaxial layer can not only raise the height of a metal silicide layer formed in the internode region, so that the metal silicide layer of the internode region and a channel region under an adjacent gate stack are not at the same height, but also fill the internode region, the step morphology of the surface of the semiconductor substrate of the internode region is changed into a flat surface, and the problem that the metal silicide is expanded due to uneven surface of the internode region in the subsequently formed metal silicide layer can be solved.
It should be noted that, in this embodiment, the thickness of the epitaxial layer may be 35 nm-55 nm, and the setting of the epitaxial layer with a certain thickness may separate the position of the subsequently formed metal silicide layer and the position of the channel region to a certain distance, that is, the epitaxial layer with a certain thickness may raise the metal silicide layer by a certain height, so that the effect of separating the metal silicide layer from the channel region by the epitaxial layer is better, and it is ensured that the PN junction at the edge of the channel region will not be damaged when the metal silicide layer expands. In addition, if the upper surfaces of the gate material layers in the memory tube gate stack and the select tube gate stack are protected by isolation using a hard mask layer made of silicon oxide or silicon nitride, the epitaxial layer can be formed only between the sidewalls, i.e., only on both sides of the memory tube gate stack and the select tube gate stack, but not on the upper surfaces of the gate material layers in the memory Guan Shanji stack and the select tube gate stack, due to the difference in the material of the hard mask layer and the material of the semiconductor substrate (silicon substrate in this embodiment). Without isolation protection of the hard mask layer when forming the epitaxial layer, the upper surfaces of the gate material layers in the memory tube gate stack and the select tube gate stack may also form an epitaxial layer, which may affect the performance of the gate material layers in the memory tube gate stack and the select tube gate stack.
In this embodiment, after the epitaxial layer is formed, the method for manufacturing the SONOS memory may further include removing the hard mask layer on the surfaces of the memory tube gate stack and the select tube gate stack, so that a metal silicide layer may be formed on the upper surfaces of the first gate material layer and the second gate material layer.
After removing the hard mask layer 107, as shown in fig. 5f, the fabrication method of the SONOS memory device further includes performing a silicide process to form a metal silicide layer on the surface of the epi layer 108 and the upper surfaces of the memory tube gate stack and the select tube gate stack. In this embodiment, the metal silicide layer 106 may be located on the epitaxial layer 108 and the upper surfaces of the gate material layer 104 in the memory tube gate stack and the select tube gate stack, and more specifically, the upper surfaces of the first gate material layer 104a and the second gate material layer 104b may also be formed with the metal silicide layer 106, and the metal silicide layer may electrically connect the first gate material layer and the second gate material layer. Because the metal silicon compound layer is positioned on the upper surfaces of the epitaxial layer, the storage tube gate stack and the selection tube gate stack and the epitaxial layer is higher than the surface of the semiconductor substrate, the metal silicon compound layer is higher than the channel region under the storage tube gate stack and the selection tube gate stack, PN junctions at the edges of the channel region are not damaged even if the silicon compound layer is expanded, and electric leakage of the channel region is not caused.
In this embodiment, the step S5 of the method for manufacturing a SONOS memory device, that is, executing the silicide process, forming a metal silicide layer on the surface of the epitaxial layer and the upper surfaces of the storage tube gate stack and the select tube gate stack may specifically include: depositing a patterned protective layer on the semiconductor substrate, wherein the protective layer exposes the surface of the epitaxial layer and the upper surfaces of the storage tube gate stack and the selection tube gate stack; forming a metal material layer on the semiconductor substrate; then, an annealing process is carried out to form a metal silicide layer; and removing the remaining metal material layer.
It should be noted that, in order to prevent the metal silicide layer from being formed at a non-predetermined position in the semiconductor substrate, that is, in order to enhance the isolation protection effect of the protection layer, the protection layer may have a double-layer structure and may include a silicon oxide layer and a silicon nitride layer which are sequentially stacked. The metal material layer may be formed by physical vapor deposition or chemical vapor deposition, among other deposition processes known to those skilled in the art. The annealing process is performed in this embodiment to form a metal silicide layer by the interaction of the metal material layer and silicon on the surface of the semiconductor substrate. In this embodiment, the metal silicide layer may be one or a combination of two or more of NiSi, tiSi, coSi and WSi.
The manufacturing method of the SONOS memory comprises the steps of etching a grid material layer, an ONO layer and a grid oxide layer on the surface of a semiconductor substrate until the surface of the semiconductor substrate is exposed, forming side walls on the side surfaces of the obtained storage tube grid stack and the obtained selection tube grid stack, forming an epitaxial layer on the exposed surface of the semiconductor substrate, wherein the epitaxial layer covers the surface of the semiconductor substrate of the internode region, and forming a metal silicide layer on the surface of the epitaxial layer. Because the epitaxial layer is formed on the surface of the semiconductor substrate, the upper surface of the epitaxial layer is higher than the surface of the semiconductor substrate, and the metal silicide layer is formed on the epitaxial layer, so that the metal silicide layer is also higher than the surface of the semiconductor substrate, meanwhile, because the channel region under the storage tube grid lamination and the selection tube grid lamination is positioned on the surface of the semiconductor substrate and below the surface of the semiconductor substrate, the metal silicide layer and the channel region are not at the same height, and meanwhile, when the PN junction is formed at the edge of the channel region, the PN junction at the edge of the channel region is not damaged even if the metal silicide layer is expanded, the problem of leakage of the channel region of the memory caused by the expansion of the metal silicide can be effectively avoided, thereby avoiding the memory failure caused by the interference of the leakage of the channel region, and improving the reliability and the production yield of the SONOS memory.
In addition, in the method for manufacturing the SONOS memory of the embodiment, before etching the gate material layer, the ONO layer and the gate oxide layer, a hard mask layer is preferably formed on the surface of the gate material layer, the hard mask layer is subjected to patterning treatment, and then the patterned hard mask layer is used as a mask for etching. Because the hard mask layer which is different from the semiconductor substrate material is formed on the gate material layer, the hard mask layer can isolate and protect the underlying gate material layer, and the epitaxial layer is prevented from being formed on the gate material layer, so that the performances of the first gate material layer and the second gate material layer in the SONOS memory are prevented from being influenced. Meanwhile, after the epitaxial layer is formed and before the metal silicide layer is formed, the hard mask layer on the surfaces of the storage tube gate stack and the selection tube gate stack is removed, so that the metal silicide layer can be formed on the upper surfaces of the gate material layers in the storage tube gate stack and the selection tube gate stack, and the first gate material layer and the second gate material layer are electrically connected.
The embodiment further provides a SONOS memory, as shown in fig. 5f, where the SONOS memory includes a semiconductor substrate, a memory tube gate structure, a selection tube gate structure, an epitaxial layer, and a metal silicide, the surface of the semiconductor substrate 101 includes a memory tube region 101a, a selection tube region 101b, and an internode region 101c located between the memory tube region 101a and the selection tube region 101b, the memory tube gate structure is located on the surface of the semiconductor substrate 101a, the memory tube gate structure includes an ONO layer 102 and a first gate material layer 104a formed by sequentially overlapping the surface of the semiconductor substrate 101, and a sidewall 105 covering the ONO layer 102 and the first gate material layer 104a, the selection tube gate structure is located on the semiconductor substrate of the selection tube region 101b, the selection tube gate structure includes a gate oxide layer 103 and a second gate material layer 104b formed by sequentially overlapping the surface of the semiconductor substrate 101, and a sidewall 105 covering the surface of the gate oxide layer 103 and the second gate material layer 104b, the memory tube gate structure includes a sidewall 108 located between the memory tube gate structure and the second gate material layer 104a and the semiconductor substrate layer 104a, and the metal silicide layer 106 a is formed by overlapping the surface of the semiconductor substrate layer 106 a and the second gate material layer 104b. The SONOS memory can further comprise source and drain regions formed on the semiconductor substrate at two sides of the storage tube grid structure and the selection tube grid structure, wherein the source and drain regions are formed through an ion implantation process.
Specifically, in order to sequentially form the ONO layer and the gate oxide layer on the surfaces of the storage area and the selection area, the surface of the semiconductor substrate in the internode area is subjected to multiple cleaning and etching, so that the surface of the semiconductor substrate in the internode area is uneven and may have a step shape. The ONO layer may be a silicon oxide-silicon nitride-silicon oxide sandwich structure. The side wall can be a silicon oxide layer or a silicon nitride layer, and can also be a multi-layer structure of silicon oxide-silicon nitride-silicon oxide. The epitaxial layer may be a silicon epitaxial layer. The metal silicide layer may be one or a combination of more than two of NiSi, tiSi, coSi and WSi, and is not at the same height as the channel region under the memory tube gate structure and the select tube gate structure.
In the SONOS memory of this embodiment, the epitaxial layer is located in the gap between the memory tube gate structure and the select tube gate structure, and the epitaxial layer covers the semiconductor substrate surface of the internode region, so that the surface of the epitaxial layer is higher than the semiconductor substrate surface, and meanwhile, the metal silicide layer covers the surface of the epitaxial layer, so that the metal silicide layer is higher than the semiconductor substrate surface, and the channel region under the memory tube gate stack structure and the select tube gate stack structure is located below the semiconductor substrate surface, so that the metal silicide layer and the channel region are not located at the same height and are higher than the channel region, so that leakage of the channel region due to expansion of the metal silicide can be avoided, memory failure caused by leakage interference of the channel region can be avoided, and reliability and production yield of the SONOS memory are improved. In addition, the epitaxial layer can fill up the surface of the internode region with the step morphology, so that a metal silicide layer of the internode region is formed on the surface of the flat semiconductor substrate, the problem of metal silicide extension caused by uneven internode region can be effectively solved, and the reliability of the SONOS memory is further improved.
The foregoing description is only illustrative of the preferred embodiments of the present invention, and is not intended to limit the scope of the claims, and any person skilled in the art may make any possible variations and modifications to the technical solution of the present invention using the method and technical content disclosed above without departing from the spirit and scope of the invention, so any simple modification, equivalent variation and modification made to the above embodiments according to the technical matter of the present invention fall within the scope of the technical solution of the present invention.
Claims (10)
1. A method for fabricating a SONOS memory device, comprising:
providing a semiconductor substrate, wherein the surface of the semiconductor substrate comprises a storage area, a selection area and an internode area positioned between the storage area and the selection area, an ONO layer is formed on the surface of the semiconductor substrate in the storage area, a gate oxide layer is formed on the surface of the semiconductor substrate in the selection area, the ONO layer is connected with the gate oxide layer in the internode area, a gate material layer is further formed on the surface of the semiconductor substrate, and the gate material layer covers the surfaces of the ONO layer and the gate oxide layer;
etching the grid material layer, the ONO layer and the grid oxide layer until the surface of the semiconductor substrate is exposed, obtaining a storage tube grid stack in the storage tube region, and obtaining a selection tube grid stack in the selection tube region;
forming side walls on the side surfaces of the storage tube grid electrode lamination and the selection tube grid electrode lamination;
performing an epitaxial process, and forming an epitaxial layer on the exposed surface of the semiconductor substrate; and
and performing a silicide process, and forming a metal silicide layer on the surface of the epitaxial layer and the upper surfaces of the storage tube gate stack and the selection tube gate stack, wherein the metal silicide layer is higher than channel regions under the storage tube gate stack and the selection tube gate stack.
2. The method of fabricating a SONOS memory device of claim 1, further comprising:
before the etching process is executed, a hard mask layer is formed on the surface of the grid electrode material layer, and graphical treatment is carried out on the hard mask layer; and
the hard mask layer on the surfaces of the memory tube gate stack and the select tube gate stack is removed after the epitaxial process is performed and before the silicide process is performed.
3. The method of claim 2, wherein after performing the silicide process, the metal silicide layer is on the epi layer and on upper surfaces of the gate material layers in the memory tube gate stack and the select tube gate stack.
4. The method of fabricating a SONOS memory device of claim 1, after performing the etching process and before forming the sidewall, further comprising:
and performing ion implantation to form shallow doped ion implantation areas in the semiconductor substrate at two sides of the storage tube gate stack and the selection tube gate stack.
5. The method of any one of claims 1 to 4, wherein the epitaxial layer has a thickness of 35nm to 55nm.
6. The method of any one of claims 1 to 4, wherein performing the silicide process to form a metal silicide layer on the surface of the epitaxial layer and the upper surfaces of the memory tube gate stack and the select tube gate stack comprises:
depositing a patterned protective layer on the semiconductor substrate, wherein the protective layer exposes the surface of the epitaxial layer and the upper surfaces of the storage tube gate stack and the selection tube gate stack;
forming a metal material layer on the semiconductor substrate;
performing an annealing process to form the metal silicide layer; and
and removing the remaining metal material layer.
7. The method of claim 6, wherein the protective layer comprises a silicon oxide layer and a silicon nitride layer sequentially stacked.
8. The method of claim 2 or 3, wherein the hard mask layer is a silicon oxide layer or a silicon nitride layer.
9. The method of any one of claims 1 to 4, wherein the metal silicide layer comprises one or a combination of more than two of NiSi, tiSi, coSi and WSi.
10. A SONOS memory device, the SONOS memory device comprising:
the semiconductor substrate comprises a storage tube region, a selection tube region and an internode region positioned between the storage tube region and the selection tube region;
the storage tube grid structure is positioned in the storage tube region and comprises an ONO layer, a first grid material layer and a side wall, wherein the ONO layer and the first grid material layer are sequentially overlapped on the surface of the semiconductor substrate, and the side wall covers the side surfaces of the ONO layer and the first grid material layer;
the selective tube grid structure is positioned in the selective tube region and comprises a grid oxide layer and a second grid material layer which are sequentially overlapped on the surface of the semiconductor substrate, and a side wall covering the side surfaces of the grid oxide layer and the second grid material layer;
an epitaxial layer, which is positioned in a gap between the storage tube grid structure and the selection tube grid structure and covers the surface of the semiconductor substrate of the internode region; and
and the metal silicide layer covers the surface of the epitaxial layer and the surfaces of the first gate material layer and the second gate material layer, and is higher than the channel region under the storage tube gate structure and the selection tube gate structure.
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| CN108091562A (en) * | 2017-12-21 | 2018-05-29 | 上海华力微电子有限公司 | The ONO lithographic methods of SONOS memories |
| CN108172581A (en) * | 2017-12-26 | 2018-06-15 | 上海华力微电子有限公司 | A kind of transistor and its manufacturing method of band SONOS structures |
| CN110277399A (en) * | 2019-05-15 | 2019-09-24 | 上海华力集成电路制造有限公司 | SONOS memory and its manufacturing method |
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| CN108091562A (en) * | 2017-12-21 | 2018-05-29 | 上海华力微电子有限公司 | The ONO lithographic methods of SONOS memories |
| CN108172581A (en) * | 2017-12-26 | 2018-06-15 | 上海华力微电子有限公司 | A kind of transistor and its manufacturing method of band SONOS structures |
| CN110277399A (en) * | 2019-05-15 | 2019-09-24 | 上海华力集成电路制造有限公司 | SONOS memory and its manufacturing method |
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