KR100725477B1 - Semiconductor device and method for manufacturing semiconductor device - Google Patents

Abstract

The present invention provides a semiconductor device having an insulating film sidewall spacer having barrier properties. The semiconductor device includes a gate oxide film and a gate electrode formed on the semiconductor substrate; Source / drain regions formed in the semiconductor substrate; A laminated sidewall spacer of two or more layers formed on the sidewall of the gate electrode, the nitride layer being formed as a layer other than the outermost layer, and the outermost layer is formed of an oxide film or an oxynitride film, and a lower surface thereof is other side than the semiconductor substrate or the gate oxide film or nitride film. A first laminated sidewall spacer in contact with the wall spacer layer; Has A stacked gate electrode structure of the nonvolatile memory; It is also possible to have three or more second laminated sidewall spacers formed on the sidewalls of the laminated gate electrode structure and including a nitride film which is not in contact with the semiconductor substrate as an intermediate layer.

Description

Semiconductor device and manufacturing method of semiconductor device {SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device, and more particularly, to a highly integrated semiconductor device and a method for manufacturing a semiconductor device having sidewall spacers having barrier properties.

Recently, in order to use self-aligned contacts (SACs) from the demand for miniaturization, sidewall spacers using silicon nitride films have been used. The silicon nitride film is a barrier insulating film that can function as an etching stopper having selectivity for etching between interlayer insulating films formed of a silicon oxide film.

Device sizes are shrinking along with higher integration and miniaturization of MOSFETs. The pn junction depth of the source / drain regions also becomes shallow, and the resistance value tends to be large. In order to reduce the resistance of the source / drain regions, it is effective to form a silicide layer over the source / drain regions.

7A to 7E are cross-sectional views showing main steps of the conventional method for manufacturing a semiconductor device.

As shown in Fig. 7A, an element isolation groove is formed on the surface of the silicon substrate 11 by etching, and an insulating material is embedded to form a shallow trench isolation (STI) 12. Alternatively, local oxidation (LOCOS) may be used instead of STI. The gate oxide layer 13 is formed by thermally oxidizing the surface of the active region defined in the device isolation region. A polycrystalline silicon film is deposited on the gate oxide film 13 by chemical vapor deposition (CVD), and the gate electrode 14 is formed by etching using a resist pattern.

In the etching of the gate electrode 14, a mixed gas composed of HBr and C1 ₂ is used as the etching gas to perform reactive ion etching with a high selectivity ratio in which the etching rates between silicon and the silicon oxide film are greatly different. Since the etching rate of the silicon oxide film is very slow compared to the etching rate for silicon, the gate oxide film 13 is barely etched when the polysilicon is etched, and the etching can be stopped. The etching of the polycrystalline silicon film is terminated while leaving the gate oxide film 13 on the active region surface. For this reason, damage by etching hardly occurs on the surface of the active region.

By using the patterned gate electrode 14 as a mask, for example, by implanting n-type impurities, the extension region 15 of the source / drain is formed. The extension region 15 is formed to have a shallow junction depth in order to prevent punch through.

As shown in Fig. 7B, a silicon nitride film is deposited by CVD to cover the gate electrode 14, and then etched back to remove the silicon nitride film on the flat surface. Only the sidewall spacers 16 of the silicon nitride film remain on the sidewalls of the gate electrodes 14. CHF ₃ By making gas the main etching gas, the etching can be terminated in a state in which the gate oxide film 13 is left. For this reason, damage can be prevented from etching on the surface of the active region.

As shown in Fig. 7C, the gate oxide film 13 exposed on both sides of the sidewall spacers is removed using a dilute hydrofluoric acid aqueous solution. The side wall spacers 16 of silicon nitride are not etched. At this time, not only the exposed gate oxide film 13 is etched, but also the gate oxide film 13 under the side wall spacer 16 is etched from the side and retreats toward the gate electrode. For this reason, the side wall spacer 16 becomes an overhang shape.

As shown in Fig. 7D, the gate electrode 14 and the side wall spacer 16 are used as a mask, for example, to implant ions of n-type impurities, thereby forming a source / drain region 17 having a deep junction. In this way, the basic structure of the MOSFET is formed.

As shown in Fig. 7E, after forming the source / drain regions 17, silicideable metals such as Ti, Co, etc. are deposited on the substrate surface by sputtering. After the first silicideation reaction is performed to remove the unreacted metal, the second silicide reaction is performed to form the silicide layer 18 on the source / drain region and the gate electrode surface.

An interlayer insulating film 21 such as silicon oxide is deposited on the substrate surface by covering the gate electrode by CVD. A contact hole penetrating through the interlayer insulating film 21 is formed, and a Ti layer, a TiN layer, and the like are formed by sputtering, and a W layer is deposited by CVD to bury the metal layer in the contact hole and to remove unnecessary portions to form the conductive plug 22. Form.

Here, as shown in FIG. 7C, undercuts are generated under the silicon nitride sidewall spacer 16 during the dilute hydrofluoric acid aqueous solution treatment. In a later process, if the metal enters the undercut and is not removed, it causes short. In addition, when a silicide layer is formed in an undercut part, the side wall spacer 16 may be stressed by volume expansion.

Japanese Laid-Open Patent Publication No. 9-162396 teaches a method of forming a source / drain region, which is a stacked side of a nitride film sidewall covering sidewalls of a gate electrode and a gate insulating film as sidewall spacers of a gate electrode and an oxide sidewall formed thereon. Start the month configuration. Since the oxide film sidewalls are formed on the entire surface of the nitride film sidewalls, it is considered that such undercut does not occur. However, since the nitride film sidewall is in contact with the substrate surface, it is difficult to avoid the stress of the nitride film sidewall on the substrate. In the dry etching of the gate electrode pattern, if the gate insulating film is also removed, the substrate surface may be etched and damage may occur.

The flash memory device is a nonvolatile semiconductor memory device that stores information in the form of electric charge in the floating gate electrode. Since the flash memory device has a simple device configuration, it is suitable for constructing a large scale integrated circuit device.

In the flash memory device, the writing and erasing of information is performed by the injection of hot carriers into the floating gate electrode and the release by the Fowler-Nordheim type tunnel effect. A high voltage is required for the write and erase operations of the flash memory device, and a booster circuit for boosting a power supply voltage is provided in a peripheral circuit. The transistors in the boost circuit must operate at high voltages.

In recent years, integrating a flash memory device on the same substrate as a high speed logic circuit has been performed to form a semiconductor integrated circuit having a complex function. Transistors constituting the high speed logic circuit must operate at high speed with low voltage. For high speed operation, it is preferable to thin the gate insulating film even if a leakage current occurs. In addition, a circuit that operates with low power consumption may be required. In order to reduce the power consumption, it is preferable to thicken the gate insulating film to some extent in order to reduce the leakage current. In order to satisfy this demand, it is required to form a plurality of transistors having different thicknesses of the gate insulating film by operating with a plurality of power supply voltages on the same semiconductor substrate.

The retention characteristic of the flash memory cell depends on the charge retention performance of the floating gate electrode. In order to improve the retention characteristics, it is preferable to surround the floating gate electrode with a high quality insulating film. Usually, the lower surface of the floating gate electrode formed of the silicon film is covered with the tunnel insulating layer and the upper surface is covered with the ONO film, and a thermal oxide film is also formed on the sidewall. It is also preferable to form a high quality silicon nitride film thereon. The thermal oxide film is a barrier insulating film which prevents leakage of accumulated charges, and the silicon nitride film is a barrier insulating film which prevents intrusion of SiH groups or moisture from the outside.

Japanese Laid-Open Patent Publication No. 2003-23114 discloses a method of forming a flash memory cell, a low voltage operation transistor, and a high voltage operation transistor on the same semiconductor substrate. Side wall spacers are simultaneously formed on the sidewalls of the stacked gate electrodes of the flash memory cells and on the gate electrode sidewalls of the other transistors.

8A to 8D schematically show an example of a method of manufacturing a semiconductor device for simultaneously creating a flash memory cell, a low voltage operation transistor, and a high voltage operation transistor.

As shown in Fig. 8A, the surface of the silicon substrate 11 having the element isolation region is thermally oxidized to form the tunnel oxide film 25. As shown in Figs. An amorphous silicon film 26 for forming a floating gate electrode is deposited on the tunnel oxide film 25. On the amorphous silicon film 26, a so-called ONO film 27 composed of an oxide film 27a, a nitride film 27b, and an oxide film 27c is formed. In addition, the amorphous silicon film becomes a polycrystalline silicon film by subsequent heat treatment.

The resist pattern is used to pattern the ONO film 27 and the silicon film 26 to form a floating gate of the flash memory and an ONO film thereon. At this time, the ONO film and the silicon film of the low voltage operation transistor region and the high voltage operation transistor region are all removed.

The flash memory cell region is covered with a resist mask, and the tunnel oxide film formed on the surface of the transistor region is removed with a dilute hydrofluoric acid aqueous solution. The resist pattern is removed and the substrate surface is thermally oxidized to form a thick gate oxide film 13a for high voltage transistors.

The flash memory cell region and the high voltage operation transistor region are covered with a resist mask, and the gate oxide film formed on the surface of the low voltage transistor region is removed. After the resist pattern is removed, the thin gate oxide film 13b for the low voltage operation transistor is grown by thermal oxidation. In this manner, a thick gate oxide film and a thin gate oxide film are formed in the transistor region. When forming three or more types of gate oxide films, the same process is repeated to form thin gate oxide films sequentially from thick gate oxide films.

Thereafter, the polycrystalline silicon film 28 is deposited on the entire surface of the substrate and patterned using a resist mask, thereby forming the control gate electrode 28c and forming the gate electrodes 28a and 28b in the transistor region. The thermal oxide film 29 is formed by thermally oxidizing the surfaces of the silicon films 26 and 28.

Ion implantation of the source / drain regions is performed using the gate electrode thus formed as at least part of the mask. In the flash memory cell region, for example, n-type regions 31, 32, 33 are formed, and in the transistor region, an extension region 15 is formed.

As shown in Fig. 8B, the silicon nitride film is deposited and etched on the entire surface of the substrate by reduced pressure (LP) CVD to leave the sidewall spacers 16 only on the sidewalls of the gate electrode and the laminated gate electrode.

As shown in FIG. 8C, the source / drain region 17 having a deep junction is formed by covering the flash memory cell region with the photoresist pattern PR and implanting ions into the transistor region. Further, the high voltage transistor and the low voltage transistor may be separated by a resist mask, and ion implantation may be performed separately in each region.

As shown in Fig. 8D, an interlayer insulating film 21 such as silicon oxide is deposited on the substrate on which the gate electrode and the stacked gate electrode are formed, and the contact hole is opened. The conductive plug 22 is formed by filling the conductive layer in the contact hole and removing unnecessary portions.

In this manner, a plurality of transistors having different operating voltages having different thicknesses of the flash memory cell and the gate insulating film can be formed.

In a flash memory cell, it is required to form a high quality thermal oxide film on the sidewalls of the stacked gate electrodes, and to cover the high quality silicon nitride film 16 by LPCVD thereon. In order to form a fine silicon nitride film of high quality, it is required to perform LPCVD at a film formation temperature of 700 ° C or higher, for example.

In the transistor region, an extension region 15 having a shallow junction depth is formed before formation of an insulating film having a barrier property such as a silicon nitride film by LPCVD. If heat treatment is performed at 700 ° C. or higher for the extension region, impurities may be thermally diffused and the desired shape may not be maintained.

In order to reduce the resistance of the source / drain regions in the logic circuit, it is required to form a silicide layer on the silicon surface as shown in Fig. 7E. Prior to silicide layer formation, the substrate surface must be cleaned by dilute HF aqueous solution. Then, as described about the manufacturing process of FIGS. 7A-7E, the space | gap side-etched below the sidewall spacer generate | occur | produces and a sidewall spacer becomes overhang shape. If an overhang occurs, it may cause a short or the like.

As described above, when plural kinds of semiconductor elements are formed on the same semiconductor substrate to optimize the characteristics of each semiconductor element, there may be a case where other semiconductor elements have an unexpected advantage.

Patent Literature

Japanese Patent Laid-Open No. 9-162396

Japanese Patent Publication No. 2003-23114

(Initiation of invention)

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device having sidewall spacers formed of an insulating film having barrier properties and which does not cause a problem due to sidewall spacers.

Another object of the present invention is to provide a semiconductor device integrating a flash memory cell with a low voltage operation transistor or a high voltage operation transistor, and which does not cause a problem by mixing heterogeneous transistors.

It is still another object of the present invention to provide a method for manufacturing a semiconductor device suitable for manufacturing these semiconductor devices.

According to one aspect of the invention, a semiconductor substrate; A first gate oxide film formed on the semiconductor substrate; A first gate electrode formed on the first gate oxide film; First source / drain regions formed in the semiconductor substrate on both sides of the first gate electrode; Two or more laminated sidewall spacers formed on the sidewalls of the first gate electrode, the nitride layer being formed as a layer other than the outermost layer, and the outermost layer is formed of an oxide film or an oxynitride film, and a lower surface thereof is formed of the semiconductor substrate or the first gate oxide film. Or a semiconductor device having a first laminated sidewall spacer in contact with a sidewall spacer layer other than a nitride film.

According to another aspect of the invention, (a) forming a gate insulating film on a semiconductor substrate; (b) forming a conductive film on the gate insulating film; (c) etching the conductive film to form a gate electrode and exposing the gate insulating film; (d) depositing a first insulating film having an etching selectivity with respect to the gate insulating film on the entire surface, and leaving a first sidewall spacer layer on the gate electrode sidewall by anisotropic etching; (e) etching the gate insulating film to expose a surface of the semiconductor substrate; (f) depositing a second insulating film on the entire surface of the semiconductor substrate, and leaving a second sidewall spacer layer on the sidewall of the first sidewall spacer by anisotropic etching; (g) implanting ions through the first and second sidewall spacers to form source / drain regions; (h) exposing the surface of the semiconductor substrate with a dilute hydrofluoric acid aqueous solution; (i) forming a silicide layer on the exposed semiconductor substrate surface; There is provided a method of manufacturing a semiconductor device comprising a.

1A to 1E are cross-sectional views of a semiconductor substrate schematically showing a manufacturing process of the semiconductor device according to the first embodiment of the present invention.

2A to 2E are cross-sectional views of a semiconductor substrate schematically showing a manufacturing process of the semiconductor device according to the second embodiment of the present invention.

3A to 3E are cross-sectional views of a semiconductor substrate schematically showing a manufacturing process of the semiconductor device according to the third embodiment of the present invention.

4A to 4E are cross-sectional views of a semiconductor substrate schematically showing a manufacturing process of the semiconductor device according to the fourth embodiment of the present invention.

5A to 5D are plan views and equivalent circuit diagrams schematically illustrating the configuration of flash memory cells.

6A to 6U are cross-sectional views of a semiconductor substrate schematically showing a manufacturing process of a semiconductor device in which a flash memory cell and another transistor are mixed according to the fifth embodiment of the present invention.

7A to 7E are cross-sectional views of a semiconductor substrate schematically showing a manufacturing process of the semiconductor device according to the prior art.

8A to 8D are cross-sectional views of a semiconductor substrate schematically showing a manufacturing process of a semiconductor device in which a conventional flash memory cell and another transistor are mixed.

(The best mode for carrying out the invention)

Hereinafter, embodiments of the present invention will be described with reference to the drawings. 1A to 1E are cross-sectional views schematically showing a method for manufacturing a semiconductor device according to the first embodiment of the present invention.

As shown in Fig. 1A, for example, an isolation layer is formed on the surface of a p-type semiconductor substrate 11 to fill an insulating film, and unnecessary parts are removed by chemical mechanical polishing (CMP) to remove the STI type isolation region ( 12) form. The surface of the active region defined as the device isolation region 12 is thermally oxidized at 800 占 폚 to 1100 占 폚 to form the gate oxide film 13. A polycrystalline silicon film is deposited on the surface of the semiconductor substrate so as to cover the gate oxide film 13. The gate electrode 14 is patterned by etching the polycrystalline silicon film using the photoresist pattern as a mask.

At this time, a high selectivity reactive ion etching (RIE) having a large difference in etching rate between silicon and a silicon oxide film is performed using a mixed gas composed of HBr and C1 ₂ as the etching gas. Since the etching rate of the silicon oxide film with respect to Si is very slow, the etching can only stop the gate oxide film 13 only when the polysilicon is etched. The resist pattern is then removed. Using the formed gate electrode as a mask, for example, n-type impurities are shallowly implanted to form the extension region 15 of the source / drain.

As shown in Fig. 1B, a silicon nitride film is deposited to cover the gate electrode, and then etched back to leave the sidewall spacers 16 of the silicon nitride film only on the sidewalls of the gate electrode 14. As shown in FIG. This etching is performed by reactive ion etching (RIE) using CHF ₃ as the main etching gas to leave the gate oxide film 13. If the damage to the substrate does not become a problem, the gate oxide film 13 may be etched away.

As shown in Fig. 1C, when the remaining gate oxide film 13 or gate oxide film has already been removed, isotropic etching of silicon oxide is performed to remove the native oxide film formed on the substrate surface. Isotropic etching can be performed by an etching method with little damage, for example, by dilute hydrofluoric acid aqueous solution or downstream method dry etching. In the isotropic etching, the etching proceeds laterally, so that the gate oxide film 13 under the sidewall spacer 16 retreats. In this way, undercut occurs under the sidewall spacer 16.

As shown in Fig. 1D, silicon oxide film 23 is deposited on the entire surface of the substrate using tetraethylorthosilicate (TEOS). The silicon oxide film 23 is also embedded in the entire surface by embedding the undercut. For example, anisotropic etching is performed using RIE using CF ₄ as the main etching gas. The silicon oxide film on the flat portion is removed to form sidewall spacers 23 of the silicon oxide film covering the sidewall spacers 16 side of the silicon nitride film and filling the undercut portions.

Prior to the silicide reaction, the silicon oxide film on the surface of the semiconductor substrate 11 and the surface of the gate electrode 14 is removed using a dilute hydrofluoric acid aqueous solution to expose a clean surface. Since the sidewall spacer is formed entirely from the TEOS silicon oxide film, the etching rate is uniform and no undercut occurs. As a result, unpredictable shorts and distortions can be prevented.

As shown in Fig. 1E, a silicideable metal such as Co or Ti layer is formed on the semiconductor substrate surface by sputtering, for example, about 30 nm thick. The primary silicided reaction is carried out, for example, by rapid thermal annealing (RTA) at 550 ° C. for 30 seconds to give rise to a primary silicided reaction of Si and metal. After removing the unreacted metal layer, the secondary silicide reaction is performed by RTA, for example, at 800 ° C. for 30 seconds to form the silicide layer 18.

Since a silicide layer can be formed without undercut and the sidewall spacer containing a silicon nitride film is formed, a SAC process as shown in FIG. 7E can also be performed.

2A-2E are cross-sectional views schematically showing a method for manufacturing a semiconductor device according to the second embodiment of the present invention.

2A and 2B have the same configuration as that of FIGS. 1A and 1B and can be manufactured by the same process.

As shown in Fig. 2C, the sidewall spacers 23 of TEOS silicon oxide are formed to cover the sidewall spacers 16 of silicon nitride. The TEOS silicon oxide film has a higher etching rate than the thermal oxide film. In forming the sidewall spacers 23, control etching is performed to leave the gate oxide film 13.

As shown in FIG. 2D, the surface of the substrate 11 and the surface of the gate electrode 14 are exposed using a dilute hydrofluoric acid aqueous solution for the silicideation reaction. In this etching, since the TEOS silicon oxide film 23 has a higher etching rate than the thermally oxidized gate oxide film 13, when the gate oxide film 13 and the TEOS silicon oxide film 23 are simultaneously etched, the gate oxide film ( Even if the etching of 13) is delayed and the protrusion is formed, the undercut is not formed.

As shown in Fig. 2E, the silicide layer 18 is formed on the exposed silicon surface as in the first embodiment.

According to this embodiment, the gate oxide film is exposed below the sidewall spacer, but since the outermost layer of the sidewall spacer is formed of a silicon oxide film whose etching rate is faster than that of the gate oxide film, no undercut occurs. The side wall spacer may include a silicon nitride film to perform a SAC process. The silicon nitride film does not come into contact with the substrate surface to prevent excessive distortion.

3A-3E are cross-sectional views schematically showing a method for manufacturing a semiconductor device according to the third embodiment of the present invention.

FIG. 3A is the same as that of FIG. 1A, and can be created by the same process.

As shown in FIG. 3B, a silicon oxide film formed by TEOS and a silicon nitride film formed by TEOS are successively deposited and etched back to cover the gate electrode 14, and the silicon oxide film 24 covering the sidewalls of the gate electrode 14. A laminated sidewall spacer of the silicon nitride film 16 is formed. Instead of the TEOS silicon oxide film, a silicon oxide film by thermal oxidation may be used. CHF _{3 is used to} etch the silicon nitride film when forming the sidewall spacers. The etching gas mainly used as a gas is used, and CF ₄ is used for etching the silicon oxide film. An etching gas mainly used for gas is used. When leaving the gate oxide film 2, time-limited control etching is performed.

As shown in FIG. 3C, the gate oxide film or the native oxide film on the silicon surface is removed with dilute hydrofluoric acid solution so as to expose the active region surface. Since the silicon oxide film on the substrate surface is removed, the gate oxide film 13 and the silicon oxide film 24 of the side wall spacer are also etched, so that an undercut occurs under the silicon nitride film side wall spacer 16.

As shown in FIG. 3D, the sidewall spacers 23 are formed by depositing and etching back a silicon oxide film using TEOS. The sidewall spacers 23 fill the undercut portions under the sidewall spacers of the silicon nitride film to form an outer surface without an undercut.

As shown in Fig. 3E, the silicide layer 18 is formed on the exposed silicon surface as in the above-described embodiment.

According to this embodiment, since the side wall spacer is formed of three layers of a silicon oxide film, a silicon nitride film, and a silicon oxide film, and the outermost side wall spacer 23 reaches the surface of the substrate, dilute fluorine prior to silicide layer formation. Undercut can be prevented from occurring in the washing process of the acid aqueous solution. The side wall spacer may include a silicon nitride film to perform a SAC process. The silicon nitride film does not come into contact with the substrate surface to prevent excessive distortion.

4A-4E are cross-sectional views schematically showing a method for manufacturing a semiconductor device according to the fourth embodiment of the present invention.

FIG. 4A has the same configuration as FIG. 1A and can be produced by the same process.

As shown in FIG. 4B, a stack of silicon oxide film 24 and silicon nitride film 16 is deposited so as to cover the gate electrode 14 as in the third embodiment, and the silicon nitride film 16 is etched back. do. By selectively performing RIE having CHF ₃ as the main etching gas, the side wall spacers of the silicon nitride film 16 are formed, and the silicon oxide film 24 below remains.

As shown in Fig. 4C, the silicon oxide film 23 is deposited on the entire surface of the substrate and etched back to remove the silicon oxide films 23 and 24 on the flat portion. On the sidewall of the gate electrode 14, side wall spacers having a laminated structure of three layers of a silicon oxide film 24, a silicon nitride film l6, and a silicon oxide film 23 are formed. The first silicon oxide film 24 is formed in a bent shape on the upper surface of the gate oxide film 13 and on the side surface of the gate electrode 14, and the silicon nitride film 16 and the silicon oxide film 23 are stacked thereon. The side wall spacer formed is formed. In this step, ion implantation for forming the source / drain regions 17 is performed.

As shown in FIG. 4D, the gate oxide film and the natural oxide film which may exist on the surface of the silicon substrate are removed using a dilute hydrofluoric acid aqueous solution to expose a clean silicon surface. Although the gate oxide film side surface is exposed, since the etching speed is slower than that of the silicon oxide film 23, undercut does not occur.

As shown in Fig. 4E, the same silicide reaction as in Fig. 1E is performed to form the silicide layer 18 on the silicon surface. A low resistance silicide layer is formed on the silicon surface without undercut to reduce the resistance of the electrode region.

In this embodiment, the gate oxide film and the silicon oxide film thereon are exposed on the sidewall side, but the etching rate of the gate oxide film is lower than the etching rate of the silicon oxide film thereon, and the side etching is suppressed, so that the undercut is prevented from occurring. The side wall spacer includes a silicon nitride film which is an insulating film having barrier property against etching of the interlayer insulating film, and can perform a SAC process. The silicon nitride film does not come into contact with the substrate surface to prevent excessive distortion.

An embodiment of a semiconductor device in which a flash memory, a logic circuit memory, a flash memory driving high voltage transistor, and the like are mixed will be described below.

5A and 5B are a plan view and an equivalent circuit diagram showing the configuration of a NOR type flash memory. As shown in Fig. 5A, an isolation region ISO is formed on a semiconductor substrate and the active region AR is defined. A tunnel oxide film is formed on the active region AR to deposit an amorphous silicon film and an ONO film serving as a floating gate on the entire surface, and are patterned in a shape corresponding to the shape of the active region AR. Thereafter, an ONO film is deposited, a polycrystalline silicon film serving as a control gate is deposited and patterned in a direction orthogonal to the floating gate, and the exposed ONO film and floating gate are also patterned. Ion implantation of the source and drain regions is performed to create a basic structure of the flash memory. The source line SL is formed in the direction crossing the active region AR through the interlayer insulating layer and connected to the source region. In addition, the bit line BL is formed in the direction along the active region through the interlayer insulating layer and connected to the drain region.

As shown in FIG. 5B, each of the flash memory cells MC including the floating gate FG and the control gate CG is connected to a common bit line BL and is connected to a separate source line. It is possible to read them individually.

5C and 5D are plan views and equivalent circuit diagrams showing the configuration of a NAND type flash memory. As shown in FIG. 5C, the device isolation region ISO is formed to define the active region AR as shown in FIG. 5A in the vertical direction in the drawing. The floating gate FG is formed in the direction corresponding to each active region AR, the control gate CG is formed in the crossing direction, and the lower floating gate FG is also patterned.

As shown in FIG. 5D, a plurality of flash memory cells MC are connected in series and connected to a read circuit through the selection gate SG. An on voltage is applied to the selection gate SG, a read voltage that is turned on / off according to the accumulated charge is applied to the read target cell, and an on voltage that is forcibly turned on is applied to the other flash memory cells MC. do. The memory state of the memory cell MC to be read is read out through the plurality of transistor structures.

Hereinafter, the cross section of the flash memory cell along the line X-X 'shown in FIG. 5A will be described as an example, but it will be apparent that the NAND type flash memory cell can be created by the same process.

As shown in FIG. 6A, a tunnel oxide film 25 having a thickness of 8 nm to 10 nm is formed by thermal oxidation at 800 ° C to 1000 ° C on the surface of the active region of the semiconductor substrate 11. In the figure, a memory region for forming a flash memory cell on the left side, a logic circuit region for forming a low voltage operation transistor in the center, and a peripheral circuit region for forming a high voltage transistor on the right side are shown. A plurality of transistors having different gate oxide film thicknesses may be formed in the logic circuit region. Each region is defined by an element isolation region such as STI. It is not necessary to form the tunnel oxide film in the transistor region, but it is formed at the same time by thermal oxidation of the substrate surface.

As shown in FIG. 6B, a doped amorphous silicon film having a thickness of 80 nm-120 nm and a P concentration of 5E19 (5 × 10 ¹⁹ ) cm ⁻³ on the tunnel oxide film 25 was deposited by CVD at about 500 ° C. An ONO film 27 is formed thereon. In addition, the doped amorphous silicon film is converted into a polycrystalline silicon film by subsequent heat treatment.

As shown in Fig. 6C, the ONO film is formed by laminating a silicon oxide film 27a, a silicon nitride film 27b, and a silicon oxide film 27c. First, a silicon oxide film 27a having a thickness of 5 nm-10 nm is deposited on the amorphous silicon film 26 by high temperature CVD at a substrate temperature of 750 ° C or higher, for example, 800 ° C. On the silicon oxide film 27a, a silicon nitride film 27b having a thickness of 5 nm-10 nm is formed by, for example, reduced pressure CVD at 700 ° C or higher. The surface of the silicon nitride film 27b is thermally oxidized at 950 ° C to form a thermal silicon oxide film 27c having a thickness of 3 nm-10 nm.

The ONO film 27 thus formed has an excellent leakage current prevention function. Although the film formation temperature of 70O degreeC or more is employ | adopted, a diffusion region is not yet formed in a transistor region, and a problem does not arise.

As shown in Fig. 6D, the flash memory cell region is covered with a resist pattern PR1, and the ONO film 27, silicon film 26, and tunnel oxide film 25 in the low voltage operation transistor region, the high voltage operation transistor region are removed. do. These films on the device isolation region are also removed. The tunnel oxide film 25 is removed by wet etching with dilute HF aqueous solution so as not to damage the substrate surface.

As shown in Fig. 6E, a thermal oxide film 13a having a thickness of 10 nm-50 nm suitable for the gate oxide film of the high voltage transistor is formed on the surface of the substrate 11 by thermal oxidation at 800 占 폚 -1100 占 폚. The same silicon oxide film is formed in the low voltage operation transistor region. Since the flash memory cell area is covered with the ONO film 27, oxidation does not proceed.

As shown in Fig. 6F, a resist mask PR2 covering the flash memory cell region and the high voltage operation transistor region is formed to remove the silicon oxide film 13a in the low voltage transistor region with a dilute hydrofluoric acid aqueous solution.

As shown in Fig. 6G, a gate oxide film 13b having a thickness of 1 nm-10 nm is formed on the surface of the low voltage operation transistor region by thermal oxidation at 800 ° C-1100 ° C. In this manner, a thin gate oxide film is formed in the low voltage operation transistor region and a thick gate oxide film in the high voltage operation transistor region. Further, the gate oxide film of the transistor may be formed of silicon oxynitride instead of silicon oxide.

As shown in Fig. 6H, a polycrystalline silicon film 28 is deposited on the substrate surface at a substrate temperature of 620 DEG C, for example, by 80 nm-250 nm in thickness by CVD. This polycrystalline silicon film 28 is then patterned to form the control gate electrode in the flash memory cell and the gate electrode in the transistor region.

A silicon nitride film 34 is formed on the polycrystalline silicon film 28 by, for example, plasma CVD at a substrate temperature of 400 ° C. with a thickness of 10 nm to 25 nm. It is also possible to form a thermal silicon nitride film or a silicon oxynitride film by plasma CVD. The silicon nitride film may function as an etch stopper or a mask for ion implantation during thermal oxidation, and does not require very dense and high quality.

As shown in FIG. 6I, a resist pattern PR3 is formed on the silicon nitride film 34 having a pattern of a stacked gate structure of a flash memory cell and covering a low voltage operation transistor region and a high voltage operation transistor region. Plasma silicon nitride film 34, polycrystalline silicon film 28, ONO film 27, and silicon film 26 are etched using this resist pattern PR3 as a mask. In the flash memory cell region, the floating gate electrode 26 of the silicon film, the ONO film 27 thereon, the control gate electrode 28c, and the plasma silicon nitride film 34 are patterned. Thereafter, resist pattern PR3 is removed.

As shown in Fig. 6J, the protective oxide film 35 is formed with a thickness of 1 nm-5 nm by thermal oxidation at 800 ° C-900 ° C on the silicon film side surface of the flash memory cell. The thermal oxide film is an insulating film having a high barrier property against leakage of carriers. In the low voltage operation transistor region and the high voltage operation transistor region, thermal oxidation is not performed because the silicon nitride film 34 covers the polycrystalline silicon film 28.

As shown in Fig. 6K, a resist pattern PR4 covering one side of the gate electrode of the flash memory cell, the low voltage operation transistor region, and the high voltage operation transistor region is formed. With respect to the area exposed to the opening of the resist pattern (PR4), for example P ⁺ ions at an acceleration energy of 50 keV-80 keV, dose ^{1 × 10 14 cm -2 -5 ×} 1O 14 cm - ion implantation, and a ^second drain The citation n-type region 31 is formed. In addition, the As ⁺ ion acceleration energy of 30 keV-50 keV, dose 1 × 10 ¹⁵ cm ^-2 - by ion implantation with 6 × 1O ¹⁵ cm ^-2 to form a diffusion region (32). Thereafter, resist mask PR4 is removed.

As shown in Fig. 6L, a resist pattern PR5 covering the low voltage operation transistor region and the high voltage operation transistor region is created. In the flash memory cell region, As ⁺ ions are implanted with an acceleration energy of 20 keV-60 keV and a dose amount of 5 × 10 ¹⁴ cm ^-2 -3 × 10 ¹⁵ cm ^-2 to increase the impurity concentration of the diffusion region 32. On the other side, a source diffusion region 33 is formed. Thereafter, resist pattern PR5 is removed.

As shown in FIG. 6M, the TEOS silicon oxide film 36 is deposited at a substrate temperature of 600 ° C., and then the silicon nitride film 37 is deposited by a reduced pressure (LP) CVD at a substrate temperature of 800 ° C. and 0.8 torr. . The silicon nitride film by LP-CVD is a dense and high quality insulating film having high barrier property against invasion of moisture, SiH groups and the like. Anisotropic etching is performed to remove the LP-CVD silicon nitride film and the TEOS silicon oxide film on the flat surface by anisotropic etching with CHF ₃ as the main etching gas and anisotropic etching with CF ₄ as the main etching gas, respectively. A side wall spacer made of a stack of a silicon oxide film 36 and a silicon nitride film 37 is formed. The TEOS silicon oxide film 36 may be omitted.

As shown in FIG. 6N, anisotropic etching is further performed using CF ₄ as the main etching gas to etch the silicon nitride film 34. The upper sidewall spacers 37 of silicon nitride are also etched. The silicon nitride film 34 in the transistor region is also removed to expose the silicon film 28.

When the silicon oxide film 36 is not formed, the silicon nitride film 37 and the silicon nitride film 34 may be etched continuously.

As shown in Fig. 6O, a resist pattern PR6 is formed having a pattern of a gate electrode in a transistor region and covering a flash memory region. Using the resist pattern PR6 as a mask, the polycrystalline silicon film 28 is etched to form the gate electrodes 28a and 28b. Since the silicon nitride film 34 is removed, only the etching target layer is silicon, and high-precision etching becomes easy. Thereafter, resist pattern PR6 is removed.

As shown in FIG. 6P, a resist pattern PR7 covering the flash memory cell region and the high voltage operation transistor region is formed and n-type impurities are implanted into the low voltage transistor region to form the extension region 41 of the source / drain. . Thereafter, resist pattern PR7 is removed.

As shown in Fig. 6Q, a resist pattern PR8 covering the flash memory cell region and the low voltage operation transistor region is formed. N-type impurities are ion-implanted into the high voltage operation transistor region to form a low concentration drain (LDD) region 42. Thereafter, resist pattern PR8 is removed. If the conditions are allowed, the extension region and the LDD region may be ion implanted in the same process without separating the low voltage operation transistor region and the high voltage operation transistor.

As shown in Fig. 6R, a TEOS silicon oxide film 44 is deposited on the entire surface of the substrate at a substrate temperature of 600 DEG C and a thickness of 80 nm to 150 nm and etched back to remove the silicon oxide film on the flat surface. Sidewall spacers 44c of a silicon oxide film are formed on the sidewalls of the stacked gate electrodes of the flash memory cell region, and sidewall spacers 44b of silicon oxide are formed on the sidewalls of the gate electrodes 28b and 28a in the low voltage operation transistor region and the high voltage transistor region. , 44a).

As shown in Fig. 6S, n-type impurities are ion-implanted with respect to all active regions to form a high concentration source / drain region 46.

In the case of forming the CM0S circuit, the p-channel region and the n-channel region are separated by a resist pattern and ion implantation is performed for n-type impurities and p-type impurities, respectively.

As shown in Fig. 6T, the substrate surface and the gate electrode surface are washed with a dilute hydrofluoric acid solution to remove the native oxide film and the like, and then a silicideable metal layer such as Ti and Co is deposited by sputtering at a thickness of about 30 nm. A TiN layer is further deposited as needed, and annealing, such as 500 degreeC and 30 second, is formed and a primary silicide layer is formed. After removing the unreacted metal layer or the like, secondary annealing is performed, for example, at 800 ° C. for 30 seconds to form the silicide layer 18 having low resistance.

Since the silicon nitride film is not exposed on the sidewall spacer surface, and the gate oxide film and the TEOS silicon oxide film are exposed to be in contact with the substrate, no undercut is formed and no problems such as shorting and distortion occur.

As shown in Fig. 6U, an interlayer insulating film 21 is deposited to cover each gate electrode structure, and the surface is planarized as necessary. A contact hole penetrating through the interlayer insulating film 21 is formed, a Ti layer, a TiN layer, and the like are formed, and then a W layer is embedded to form a W plug 22 by removing unnecessary portions. In this way, a semiconductor device in which a plurality of kinds of semiconductor elements are mixed is formed. An upper layer wiring is formed as needed, and a multilayer wiring structure is formed. As for the general technique of the semiconductor device, various known techniques can be employed (see, for example, US Pat. Nos. 6,492,734, 6,500,710, which are incorporated by reference in their entirety).

Although the present invention has been described in accordance with the above embodiments, the present invention is not limited thereto. For example, it will be apparent to those skilled in the art that various modifications, improvements, and combinations are possible.

It can be used for highly integrated semiconductor devices. It can be used for the semiconductor integrated circuit device which mixed several types of semiconductor elements.

Claims (21)

Semiconductor substrate A first gate oxide film formed on the semiconductor substrate; A first gate electrode formed on the first gate oxide film and having a narrower width than the first gate oxide film; First source / drain regions formed in the semiconductor substrate on both sides of the first gate electrode; A laminated sidewall spacer formed on the sidewall of the first gate electrode and including a nitride film as a layer other than the outermost layer, wherein the outermost layer is formed of an oxide film or an oxynitride film, The outermost layer has a bottom surface in contact with the semiconductor substrate and an inner wall surface in contact with a side surface of the nitride film and a side surface of the first gate oxide film as layers other than the outermost layer, or a bottom surface thereof contacts the first gate oxide film. A semiconductor device in contact with and in contact with a side surface of the nitride film as a layer other than the outermost layer. The semiconductor device of claim 1, further comprising a first silicide layer formed on the first source / drain region. delete delete delete delete delete delete delete delete delete Semiconductor substrates; A first gate oxide film formed on the semiconductor substrate; A first gate electrode formed on the first gate oxide film; First source / drain regions formed in the semiconductor substrate on both sides of the first gate electrode; First side wall spacers formed on sidewalls of the first gate electrode; As a stacked gate electrode structure formed on the semiconductor substrate, A tunnel insulating film formed on the semiconductor substrate; A floating gate electrode formed on the tunnel insulating film; An insulating film formed on the floating electrode; Control gate electrode formed on the insulating film A stacked gate electrode structure comprising a; Second source / drain regions formed in the semiconductor substrate on both sides of the stacked gate electrode structure; And A second laminated sidewall spacer of at least three layers formed on the sidewalls of the stacked gate electrode structure, the second stacked sidewall spacer including a nitride film not in contact with the semiconductor substrate as an intermediate layer, and the outermost sidewall spacer layer directly contacting the semiconductor substrate; Sidewall spacer A semiconductor device having a. The semiconductor device according to claim 12, wherein the first sidewall spacer is formed of the same layer as the outermost sidewall spacer layer of the second laminated sidewall spacer. delete delete (a) forming a gate insulating film on the semiconductor substrate; (b) forming a conductive film on the gate insulating film; (c) etching the conductive film to form a gate electrode and simultaneously exposing the gate insulating film; (d) depositing a first insulating film having an etching selectivity with respect to the gate insulating film on the entire surface, and leaving a first sidewall spacer layer on the gate electrode sidewall by anisotropic etching; (e) etching the gate insulating film to expose a surface of the semiconductor substrate; (f) depositing a second insulating film on the entire surface of the semiconductor substrate, and leaving a second sidewall spacer layer on the sidewall of the first sidewall spacer by anisotropic etching; (g) implanting ions through the first and second sidewall spacers and forming source / drain regions; (h) exposing the surface of the semiconductor substrate with an aqueous dilute hydrofluoric acid solution; And (i) forming a silicide layer on the exposed semiconductor substrate surface Method for manufacturing a semiconductor device comprising a. The method of claim 16, (j) depositing a third insulating layer on the entire surface of the semiconductor substrate between steps (c) and (d) The method of claim 10, wherein the step (d) is to anisotropically etch the first and third insulating layers. (a) forming a gate insulating film on the semiconductor substrate; (b) forming a conductive film on the gate insulating film; (c) etching the conductive film to form a gate electrode and simultaneously exposing the gate insulating film; (d) depositing a first insulating film having an etching selectivity with respect to the gate insulating film on the entire surface, and leaving a first sidewall spacer layer on the gate electrode sidewall by anisotropic etching; (e) depositing a second insulating film having an etching rate higher than that of the gate insulating film on the entire surface of the semiconductor substrate, and leaving a second sidewall spacer layer on the sidewall of the first sidewall spacer by anisotropic etching; (f) etching the gate insulating film to expose a surface of the semiconductor substrate; (g) implanting ions through the first and second sidewall spacers and forming source / drain regions; (h) exposing the surface of the semiconductor substrate with an aqueous dilute hydrofluoric acid solution; And (i) forming a silicide layer on the exposed semiconductor substrate surface Method for manufacturing a semiconductor device comprising a. The method of claim 18, (j) further comprising depositing a third insulating layer on the entire surface of the semiconductor substrate between steps (c) and (d), wherein step (d) anisotropically etches the first and third insulating layers. The manufacturing method of a semiconductor device. (a) depositing and patterning a tunnel insulating film, a floating gate electrode film, and an insulating film on a semiconductor substrate to form a floating gate electrode structure; (b) forming a gate insulating film in another region of the semiconductor substrate; (c) depositing a conductive film and an etch stopper film covering the floating gate electrode structure and the gate insulating film; (d) etching the etch stopper film and the conductive film to form a stacked gate electrode structure of a nonvolatile memory; (e) forming a first insulating film for preventing leakage on sidewalls of the stacked gate electrode structure; (f) covering the first insulating film for preventing leakage and depositing a silicon nitride film by LP-CVD, and leaving a first sidewall spacer layer on the sidewall of the stacked gate electrode by anisotropic etching; (g) removing the etch stopper layer; (h) patterning the conductive layer in the other region to form a gate electrode structure; (i) depositing a second insulating film on the entire surface of the semiconductor substrate and leaving a second sidewall spacer on the sidewall of the stacked gate electrode structure and the gate electrode structure by anisotropic etching; (j) exposing the surface of the semiconductor substrate with an aqueous dilute hydrofluoric acid solution; And (k) forming a silicide layer on the exposed surface of the semiconductor substrate Method for manufacturing a semiconductor device comprising a. 21. The method of manufacturing a semiconductor device according to claim 20, wherein said step (i) forms a laminated sidewall spacer comprising a silicon nitride film as an intermediate layer.

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