CN114464526A - Multi-time programmable memory and preparation method thereof - Google Patents
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- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
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- H—ELECTRICITY
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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Abstract
The invention provides a multi-time programmable memory and a preparation method thereof. In the invention, part of the grid structure is arranged in the first groove to form a stepped grid structure, so that the contact area between the first well region and the grid structure is increased, the distance of electrons entering the grid structure is shortened, the programming and erasing efficiency of the device is improved, the working voltage is reduced, and the energy consumption of the device is reduced. And part of the grid structure is positioned in the second groove, compared with a planar structure, the contact area between the grid structure arranged in the second groove and the second well region is increased, the coupling efficiency of the capacitor is improved, and the response speed of the device is improved. In addition, the first groove and the second groove are arranged, so that the grid structure is of a sinking structure. The unit area of the multi-time programmable memory provided by the invention is smaller than that of a device with a planar grid structure under the same device performance.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a multi-time programmable memory and a preparation method thereof.
Background
With the development of semiconductor industry and technology, nonvolatile memories are widely used in the field of microcontrollers and the like. The nonvolatile memory is characterized in that the electric characteristics of transistors of the nonvolatile memory are changed, and the current magnitude is different under the action of certain voltage due to different threshold voltages during writing and erasing. The Multi-Time Programmable Memory (MTP) in the non-volatile Memory can perform operations such as data storage, reading, erasing, and the like for many times, and the stored data does not disappear after power failure, and the Multi-Time Programmable Memory adopts a single-layer floating gate structure and can be combined with a normal CMOS process. Thus, the multi-time programmable memory has become a memory device widely used in electronic devices.
However, the conventional multi-time programmable memory still has the problems of large unit area, high energy consumption, low coupling efficiency and low programming and erasing efficiency of the device. In view of the above, a new multi-time programmable memory is needed to solve the above technical problems.
Disclosure of Invention
The invention aims to provide a multi-time programmable memory and a preparation method thereof, so as to solve at least one problem of reducing the unit area of a device, improving the coupling efficiency, improving the programming and erasing efficiency and reducing the energy consumption of the device.
In order to solve the above technical problem, the present invention provides a method for manufacturing a multi-time programmable memory, comprising:
providing a substrate, wherein a first well region and a second well region are formed in the substrate;
forming a first groove in the first well region and a second groove in the second well region;
forming a gate structure, wherein the gate structure covers part of the surface of the first well region and part of the surface of the second well region, fills the second groove, fills part of the first groove, and exposes part of the side wall and the bottom wall of the first groove;
forming a source electrode, a drain electrode, a body region and a control region, wherein the source electrode is adjacent to the body region, the source electrode and the drain electrode are respectively positioned in the first well region at two opposite sides of the gate structure, and the control region is positioned in the second well region; and the drain electrode is connected with the bottom wall of the exposed part of the first groove.
Optionally, in the method for manufacturing a multi-time programmable memory, the process of forming the first well region and the second well region includes:
forming a shallow trench isolation structure in the substrate to define a first region and a second region;
respectively carrying out ion implantation processes on the first region and the second region to form a first well region in the first region and a second well region in the second region; wherein the first well region has a first conductivity type and the second well region has a second conductivity type.
Optionally, in the method for manufacturing a multi-time programmable memory, a process of forming the gate structure includes:
forming a first oxidation layer, wherein the first oxidation layer covers the surfaces of the first well region and the second well region, and covers the side walls and the bottom walls of the first groove and the second groove;
forming a gate material layer covering the first oxide layer;
etching to remove a part of the gate material layer and a part of the first oxide layer, exposing the surfaces of a part of the first well region and a part of the second well region, and the side wall and the bottom wall of a part of the first groove;
forming a side wall structure, wherein the side wall structure covers the exposed side wall of the grid material layer;
and forming the gate structure by the gate material layer left after etching, the first oxide layer left and the side wall structure.
Optionally, in the method for manufacturing a multi-time programmable memory, the source, the drain, the body region, and the control region are formed by an ion implantation process; wherein the body region has a first conductivity type and the source, drain and control regions have a second conductivity type.
Optionally, in the method for manufacturing the multi-time programmable memory, after the source, the drain, the body region, and the control region are formed, the method further includes:
forming a metal silicide blocking layer covering top surfaces of the source, the drain, the body region, the control region, and the gate structure.
Optionally, in the method for manufacturing a multi-time programmable memory, after the forming the metal silicide blocking layer, the method further includes:
and forming a plurality of metal contact structures, wherein the plurality of metal contact structures are respectively connected with the source electrode, the drain electrode, the body region, the control region and the grid electrode structure so as to electrically lead out the source electrode, the drain electrode, the body region, the control region and the grid electrode structure.
Based on the same inventive concept, the invention provides a multi-time programmable memory, which comprises:
the semiconductor device comprises a substrate, a first semiconductor layer and a second semiconductor layer, wherein the substrate comprises a first well region and a second well region, a first groove is formed in the first well region, and a second groove is formed in the second well region;
the grid structure covers part of the surface of the first well region and part of the surface of the second well region, fills the second groove, fills part of the first groove and exposes part of the side wall and the bottom wall of the first groove;
the source electrode is adjacent to the body region, the source electrode and the drain electrode are respectively positioned in the first well regions on two opposite sides of the grid structure, and the control region is positioned in the second well region; and the drain electrode is connected with the bottom wall of the exposed part of the first groove.
Optionally, in the multi-time programmable memory, the gate structure includes a first oxide layer, a gate material layer, and a sidewall structure; wherein the content of the first and second substances,
the first oxidation layer covers part of the surface of the first well region, part of the surface of the second well region, the side wall and the bottom wall of the second groove, and part of the side wall and the bottom wall of the first groove;
the grid material layer covers the first oxide layer, fills the second groove and fills part of the first groove;
the side wall structure covers the exposed side wall of the grid material layer.
Optionally, in the multi-time programmable memory, the multi-time programmable memory further includes a shallow trench isolation structure, a metal silicide blocking layer, and a plurality of metal contact structures; the shallow trench isolation structure is arranged in the substrate and surrounds the first well region and the second well region; the metal silicide blocking layer covers the source, the drain, the body region, the control region and a top surface of the gate structure; the metal contact structures are respectively connected with the source electrode, the drain electrode, the body region, the control region and the grid electrode structure so as to electrically lead out the source electrode, the drain electrode, the body region, the control region and the grid electrode structure.
Optionally, in the multi-time programmable memory, the first well region and the body region have a first conductivity type, and the second well region, the source, the drain, and the control region have a second conductivity type.
In summary, the present invention provides a multi-time programmable memory and a method for manufacturing the same. The preparation method of the multi-time programmable memory comprises the following steps: providing a substrate, wherein a first well region and a second well region are formed in the substrate; forming a first groove in the first well region and a second groove in the second well region; forming a gate structure, wherein the gate structure covers part of the surface of the first well region and part of the surface of the second well region, fills the second groove, fills part of the first groove, and exposes part of the side wall and the bottom wall of the first groove; forming a source electrode, a drain electrode, a body region and a control region, wherein the source electrode is adjacent to the body region, the source electrode and the drain electrode are respectively positioned in the first well region at two opposite sides of the gate structure, and the control region is positioned in the second well region; and the drain electrode is connected with the bottom wall of the exposed part of the first groove.
Therefore, in the invention, part of the grid structure is arranged in the first groove to form a stepped grid structure, so that the contact area between the first well region and the grid structure is increased, the distance of electrons entering the grid structure is reduced, the programming and erasing efficiency of the device is further improved, the working voltage is reduced, and the energy consumption of the device is reduced. And part of the gate structure is positioned in the second groove, compared with the gate structure which is arranged in a plane, the contact area between the gate structure arranged in the second groove and the second well region is increased, the coupling efficiency of the control region to the gate structure is improved, and the response speed of the device is improved. In addition, the first groove and the second groove are arranged, so that the grid structure is in a sunken shape. The unit area of the multi-time programmable memory provided by the invention is smaller than that of a device with a planar grid structure under the same device performance.
Therefore, the multi-time programmable memory and the preparation method thereof provided by the invention can improve the coupling efficiency, programming and erasing efficiency, reduce the energy consumption of the device, reduce the unit area of the device and meet the development trend of miniaturization of the device.
Drawings
FIG. 1 is a flow chart of a method for fabricating a multi-time programmable memory according to an embodiment of the invention;
FIGS. 2-16 are schematic diagrams of semiconductor structures during fabrication of a multi-time programmable memory according to an embodiment of the present invention;
wherein the description of the reference numbers is:
100-a substrate; 101-a first well region; 102-a second well region; 103-shallow trench isolation structures; 104-a first oxide layer; 105-a layer of gate material; 106 — remaining first oxide layer; 107-the remaining gate material layer; 108-a sidewall structure; 109-body region; 110-source electrode; 111-drain electrode; 112-a control zone; 113-a metal silicide barrier layer; 114-metal contact structures.
Detailed Description
To further clarify the objects, advantages and features of the present invention, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings. It is to be noted that the drawings are in greatly simplified form and are not to scale, but are merely intended to facilitate and clarify the explanation of the embodiments of the present invention. Further, the structures illustrated in the drawings are often part of actual structures. In particular, the drawings may have different emphasis points and may sometimes be scaled differently. It should be further understood that the terms "first," "second," "third," and the like in the description are used for distinguishing between various components, elements, steps, and the like, and are not intended to imply a logical or sequential relationship between various components, elements, steps, or the like, unless otherwise indicated or indicated.
To solve the above technical problem, the present embodiment provides a method for manufacturing a multi-time programmable memory, referring to fig. 1, the method includes:
step one S10: providing a substrate, wherein a first well region and a second well region are formed in the substrate;
step two S20: forming a first groove in the first well region and a second groove in the second well region;
step three S30: forming a gate structure, wherein the gate structure covers part of the surface of the first well region and part of the surface of the second well region, fills the second groove, fills part of the first groove, and exposes part of the side wall and the bottom wall of the first groove;
step four S40: forming a source electrode, a drain electrode, a body region and a control region, wherein the source electrode is adjacent to the body region, the source electrode and the drain electrode are respectively positioned in the first well region at two opposite sides of the gate structure, and the control region is positioned in the second well region; and the drain electrode is connected with the bottom wall of the exposed part of the first groove.
Therefore, in the method for manufacturing the otp memory provided in this embodiment, a portion of the gate structure is disposed in the first groove to form a stepped gate structure, so that the contact area between the first well region and the gate structure is increased, the distance from electrons entering the gate structure is reduced, the programming and erasing efficiency of the device is further improved, the working voltage is reduced, and the energy consumption of the device is reduced. And part of the gate structure is positioned in the second groove, compared with the gate structure which is arranged in a plane, the contact area between the gate structure arranged in the second groove and the second well region is increased, the coupling efficiency of the control region to the gate structure is improved, and the response speed of the device is improved. In addition, the first groove and the second groove are arranged, so that the grid structure is in a sunken shape. The present embodiment provides a smaller unit area of the multi-time programmable memory than a device area in which the gate structure is arranged on a plane, under the same device performance.
The method for manufacturing the multi-time programmable memory provided by the present embodiment is described in detail below with reference to fig. 2 to 16.
Step one, S10: referring to fig. 2-3, a substrate 100 is provided, wherein a first well 101 and a second well 102 are formed in the substrate 100.
The substrate 100 may be any substrate for supporting semiconductor integrated circuit components known to those skilled in the art, and may be a bare die, a wafer after epitaxial growth, or a circuit layer on which devices have been formed. Optionally, the substrate 100 includes a silicon-on-insulator (SOI) substrate, a bulk silicon (bulk silicon) substrate, a germanium substrate, a silicon-germanium substrate, an indium phosphide (InP) substrate, a gallium arsenide (GaAs) substrate, or a germanium-on-insulator substrate. Wherein the substrate 100 has a first conductivity type. Further, in the embodiment, the first conductive type is P-type, i.e., doped with P-type ions, and the second conductive type is N-type, i.e., doped with N-type ions. In other embodiments, the first conductivity type may be N-type and the second conductivity type may be P-type.
Further, after providing the substrate 100, the process of forming the first well region 101 and the second well region 102 includes:
substep S101: a shallow trench isolation structure 103 is formed in the substrate 100 to define a first region and a second region. That is, an active region is defined by the shallow trench isolation structure 103, and the shallow trench isolation structure 103 plays a role of electrical isolation. Optionally, a patterned mask layer is formed on the substrate 100; then, forming a trench structure on the substrate 100 by dry or wet etching; finally, an isolation material is filled to form the shallow trench isolation structure 103.
Substep S102: performing an ion implantation process on the first region and the second region respectively to form a first well region 101 in the first region and a second well region 102 in the second region; the first well region 101 has a first conductivity type, and the second well region 102 has a second conductivity type.
Specifically, a blocking layer is formed on the surface of the substrate 100 to shield the first region and then shield the second region, or shield the second region and then shield the first region, so as to dope P-type ions into the exposed first region and dope N-type ions into the exposed second region, thereby forming the first well region 101 and the second well region 102. Optionally, the ion doping concentrations in the first well region 101 and the second well region 102 are the same.
Step two S20: referring to fig. 4-5, a first trench T1 is formed in the first well 101, and a second trench T2 is formed in the second well 102.
Further, a patterned etch stop layer is formed on the surface of the substrate 100, exposing a portion of the first well region 101 and a portion of the second well region 102. And etching by a dry etching process or a wet etching process to form the first groove T1 and the second groove T2. As shown in fig. 4, the first groove T1 is far from the center of the first well 101 and near one side of the first well 101, so that the gate structure to be formed later is partially located on the surface of the first well 101 and partially located in the first groove T1.
Step three S30: referring to fig. 4 and 6-11, a gate structure is formed, covering a portion of the surface of the first well 101 and a portion of the surface of the second well 102, filling the second trench T2, and filling a portion of the first trench T1, exposing a portion of the sidewalls and bottom walls of the first trench T1.
Wherein the process of forming the gate structure comprises:
the substep one S301: referring to fig. 4 and 6, a first oxide layer 104 is formed, wherein the first oxide layer 104 covers the surfaces of the first well region 101 and the second well region 102, and covers the sidewalls and the bottom walls of the first trench T1 and the second trench T2.
Specifically, the first oxide layer 104 is grown on the surface of the substrate 100 by a thermal oxidation process, that is, the first oxide layer 104 covers the surface of the first well region 101, the surface of the second well region 102, the surface of the shallow trench isolation structure 103, and the inner walls of the first groove T1 and the second groove T2. The first oxide layer 104 is formed to protect the first well region 101 and the second well region 102 and to achieve electrical isolation. Further, the material of the first oxide layer 104 is silicon dioxide.
Substep two, S302: referring to fig. 7, a gate material layer 105 is formed, wherein the gate material layer 105 covers the first oxide layer 104. Further, the gate material layer 105 is made of polysilicon.
Substep three S303: etching removes a portion of the gate material layer 105 and a portion of the first oxide layer 104, exposing a portion of the surfaces of the first well region 101 and the second well region 102, and portions of the sidewalls and the bottom wall of the first recess T1.
Optionally, forming a patterned etching stop layer on the surface of the semiconductor structure to shield a portion of the gate material layer 105 located at one side of the first trench T1 and a portion of the gate material layer 105 connected to the first trench T1 and located at the surface of the first well 101; the gate material layer 105 in the second groove T2 and a portion of the gate material layer 105 connecting the first groove T1 and the second groove T2 are also shielded. Then, the exposed gate material layer 105 and the first oxide layer 104 are sequentially etched and removed by using a dry or wet etching process.
Substep four S304: referring to fig. 8-11, a sidewall structure 108 is formed, where the sidewall structure 108 covers the exposed sidewall of the gate material layer 107; the gate structure is formed by the gate material layer 107 remaining after etching, the first oxide layer 106 remaining after etching, and the sidewall structure 108.
Further, as shown in fig. 8, the gate material layer 107 located in the first well region 101 covers a portion of the surface of the first well region 101 and a portion of the sidewalls and the bottom wall of the first groove T1 connected thereto, i.e., does not completely cover the first groove T1. The gate material layer 107 in the second well region 102 completely covers the second recess T2. The sidewall structure 108 surrounds the sidewall of the gate material layer 107 to protect the gate material layer 107. Wherein the sidewall structure 108 may be an oxide layer, a nitride layer, an ON film layer or an ONO film layer,
wherein fig. 9 is a sectional view taken at a-a ' in fig. 8, fig. 10 is a sectional view taken at C-C ' in fig. 8, and fig. 11 is a sectional view taken at D-D ' in fig. 8. It can be seen from fig. 9-11 that the gate structure located in the first well region 101 is in a stair-step structure, i.e., is located partially in the first recess T1 and partially located on the surface of the first well region 101. The gate structure in the second well region 102 is filled in the second groove T2. The design manner provided by the present embodiment increases the contact area between the gate structure and the first well region and the second well region, which is beneficial to providing the device performance, relative to disposing the gate structure on the surface of the substrate 100. Furthermore, a part of the gate structure located in the first well region 101 is used as a floating gate structure of an MOS transistor, and the stepped shape increases the contact area between the first well region 101 and the gate structure, reduces the distance for electrons to enter the gate structure, improves the programming and erasing efficiency of the device, reduces the working voltage, and reduces the energy consumption of the device. A part of the gate structure located in the second well region 102, and the control region formed subsequently form a capacitor structure, and the gate structure is placed in the second groove T2, so that the contact area between the gate structure and the second well region 102 is increased, the coupling efficiency of the control region to the gate structure can be greatly improved, and the response speed of the device is improved. In addition, the gate structure is arranged in the groove, and the unit area of the device can be reduced.
Step four S40: referring to fig. 12 to 14, a source 110, a drain 111, a body 109 and a control region 112 are formed, wherein the source 110 is adjacent to the body 109, and is located in the first well 101 on two opposite sides of the gate structure with respect to the drain 111, and the control region 112 is located in the second well 102; wherein, the drain electrode 111 meets the bottom wall of the exposed part of the first groove T1.
Specifically, an ion implantation process is adopted to form a source 110, a drain 111, a body region 109 and a control region 112; wherein the body region 109 has a first conductivity type and the source 110, the drain 111 and the control region 112 have a second conductivity type. That is, P-type ions are doped in the body region 109 and N-type ions are doped in the drain electrode 111, the body region 109, and the control region 112, respectively, by forming an ion implantation blocking layer. Optionally, the ion doping concentrations in the source 110, the drain 111, the body region 109 and the control region 112 are the same or different, but are all higher than the first well region 101, the second well region 102 and the substrate 100. The body region 109 is used as a leading-out terminal of the first well region 101, and the control region 102 is used as a control gate of a device. The source 110 and the drain 111 are located in the first well region 101 at two sides of the gate structure, and the drain 111 is formed by performing ion implantation toward the exposed portion of the bottom wall of the first groove T1, so that the drain 111 is located in the first well region 101 under the bottom wall of the first groove T1.
Further, under the voltage action of the source 110 and the drain 111, part of electrons may enter the gate structure through a hot carrier mechanism to form a writing state, or may be pulled out from the gate structure through an electron tunneling effect to form an erasing state. The stepped grid structure reduces the distance of electrons entering the grid structure, improves the programming and erasing efficiency of the device, reduces the working voltage and reduces the energy consumption of the device. Under the voltage action of the source 110, the drain 111 and the control region 112, the gate structure located in the second well region 102 is disposed in the second groove T2, so that the contact area between the gate structure and the second well region 102 is increased by the side wall area of the second trench T2 compared with the contact area disposed on the surface of the second well region 102. Therefore, the coupling efficiency of the control region 112 to the gate structure increases with increasing contact area.
Referring to fig. 15-16, after forming the source 110, the drain 111, the body 109 and the control region 112, the method further comprises: a metal silicide blocking layer 113 is formed, and a plurality of metal contact structures 114 are formed. The metal silicide blocking layer 113 covers the top surfaces of the source 110, the drain 111, the body 109, the control region 112, and the gate structure; a plurality of the metal contact structures 114 interface with the source 110, the drain 111, the body 109, the control region 112, and the metal silicide block layer 113 on the top surface of the gate structure, respectively. The metal silicide blocking layer 113 is used to reduce contact resistance, and the plurality of metal contact structures 114 are used to electrically extract the source 110, the drain 111, the body 109, the control region 112, and the gate structure.
Based on the same inventive concept, the present embodiment provides a multi-time programmable memory, please refer to fig. 2-16, which includes:
the substrate 100, the substrate 100 includes a first well region 101, a second well region 102 and a shallow trench isolation structure 103, and the first well region 101 has a first groove T1 therein, and the second well region 102 has a second groove T2 therein; the shallow trench isolation structure 103 is disposed in the substrate 100 and surrounds the first well region 101 and the second well region 102;
a gate structure covering a portion of the surface of the first well region 101 and a portion of the surface of the second well region 102, filling the second groove T2, and filling a portion of the first groove T1, exposing a portion of the sidewalls and the bottom wall of the first groove T1; further, the gate structure includes a first oxide layer 106, a gate material layer 107, and a sidewall structure 108; wherein the first oxide layer 106 covers a portion of the surface of the first well region 101, a portion of the surface of the second well region 102, and sidewalls and a bottom wall of the second groove T2, and covers a portion of sidewalls and a bottom wall of the first groove T1; the gate material layer 107 covers the first oxide layer 106, and fills the full second groove T2 and fills a part of the first groove T2; the sidewall spacer structure 108 covers the exposed sidewall of the gate material layer 107;
a source 110, a drain 111, a body 109 and a control region 112, wherein the source 110 is adjacent to the body 109, and is located in the first well 101 on two opposite sides of the gate structure with the drain 111, respectively, and the control region 112 is located in the second well 102; the drain electrode 111 is connected with the bottom wall of the exposed part of the first groove T1;
the metal silicide blocking layer 113, the metal silicide blocking layer 113 covering the source 110, the drain 111, the body region 109, the control region 112 and the top surface of the gate structure for reducing contact resistance;
the metal contact structures 114 are located on the metal silicide blocking layer 113, and the metal contact structures 114 are respectively connected to the source 110, the drain 111, the body region 109, the control region 112, and the gate structure, and are used for electrically leading out the source 110, the drain 111, the body region 109, the control region 112, and the gate structure.
Further, the first well region 101 and the body region 109 have a first conductivity type, and the second well region 102, the source 110, the drain 111, and the control region 112 have a second conductivity type. In the embodiment, the first conductive type is P-type, i.e., doped with P-type ions, and the second conductive type is N-type, i.e., doped with N-type ions. In other embodiments, the first conductivity type may be N-type and the second conductivity type may be P-type.
As described above, in the first well region 101, a portion of the gate structure, the source 110, the drain 111, and the body 109 form an NMOS structure, and in the second well region 102, a portion of the gate structure, and the control region 112 form a capacitor structure. The multi-time programmable memory provided by the embodiment comprises the NMOS structure and the capacitor structure.
In a device programming state, the source 110 and the body 109 are connected to a voltage of 0V, the drain 111 and the control region 112 are connected to a high voltage PHV, and then the gate structure is coupled to a positive voltage by the gate structure at one end of the NMOS under the coupling action of the control region 112, and then the channel of the NMOS is opened. Under the action of the voltages at the source 110 and the drain 111, part of the electrons enter the gate structure through the hot carrier mechanism, and are in a programmed state. The stepped gate structure in the NMOS increases the contact area between the gate structure and the first well 101, increases the probability of electrons entering the gate structure, and reduces the distance of electrons entering the gate structure, thereby improving the programming efficiency of the device and reducing the operating voltage. Meanwhile, the second trench T2 is disposed to increase the contact area between the gate structure and the second well region 102, thereby improving the coupling efficiency of the control region 112 to the gate structure.
In the device erasing state, the source 110, the body 109 and the control region 112 are connected to a voltage of 0V, and the drain 111 is connected to a high voltage PHV. Under the voltage of the drain 111, electrons in the gate structure are pulled out from the gate structure by an electron tunneling effect, i.e., erasing is achieved. Similarly, the stepped gate structure and the gate structure filled in the second groove T2 can improve the erasing efficiency and the coupling efficiency, and reduce the working voltage and the power consumption when in the erasing state
In a device reading state, the source 110 and the body 109 are connected to a voltage of 0V, the control region 112 is connected to a control gate operating voltage Vcg, and the drain 111 is connected to an operating voltage Vdd. And because electrons in the grid structure can influence the current of the device, the working state of the device can be obtained by reading the current.
In summary, the present embodiment provides a multi-time programmable memory and a manufacturing method thereof. In this embodiment, a portion of the gate structure is disposed in the first groove T1 to form a stepped gate structure, so as to increase a contact area between the first well 101 and the gate structure, and reduce a distance for electrons to enter the gate structure, thereby improving programming and erasing efficiency of the device, reducing operating voltage, and reducing energy consumption of the device. And, a part of the gate structure is located in the second groove T2, so that compared with a gate structure arranged in a plane, the contact area between the gate structure arranged in the second groove T2 and the second well region 101 is increased, the coupling efficiency of the control region 112 to the gate structure is improved, and the response speed of the device is improved. In addition, the first groove T1 and the second groove T2 are arranged, so that the gate structure has a sunken appearance. The present embodiment provides a smaller unit area of the multi-time programmable memory than a device area in which the gate structure is arranged on a plane, under the same device performance. Therefore, the multiple-time programmable memory and the preparation method thereof provided by the embodiment can improve the coupling efficiency, the programming and erasing efficiency and reduce the energy consumption of the device, can also reduce the unit area of the device, and meet the development trend of miniaturization of the device.
It should be understood, however, that the intention is not to limit the invention to the particular embodiments described. It will be apparent to those skilled in the art from this disclosure that many changes and modifications can be made, or equivalents modified, in the embodiments of the invention without departing from the scope of the invention. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention are still within the protection scope of the technical solution of the present invention, unless the content of the technical solution of the present invention is departed from.
Claims (10)
1. A method for preparing a multi-time programmable memory is characterized by comprising the following steps:
providing a substrate, wherein a first well region and a second well region are formed in the substrate;
forming a first groove in the first well region and a second groove in the second well region;
forming a gate structure, wherein the gate structure covers part of the surface of the first well region and part of the surface of the second well region, fills the second groove, fills part of the first groove, and exposes part of the side wall and the bottom wall of the first groove;
forming a source electrode, a drain electrode, a body region and a control region, wherein the source electrode is adjacent to the body region, the source electrode and the drain electrode are respectively positioned in the first well region at two opposite sides of the gate structure, and the control region is positioned in the second well region; and the drain electrode is connected with the bottom wall of the exposed part of the first groove.
2. The method of claim 1, wherein the step of forming the first well region and the second well region comprises:
forming a shallow trench isolation structure in the substrate to define a first region and a second region;
respectively carrying out ion implantation processes on the first region and the second region to form a first well region in the first region and a second well region in the second region; wherein the first well region has a first conductivity type and the second well region has a second conductivity type.
3. The method of claim 1, wherein the step of forming the gate structure comprises:
forming a first oxidation layer, wherein the first oxidation layer covers the surfaces of the first well region and the second well region, and covers the side walls and the bottom walls of the first groove and the second groove;
forming a gate material layer covering the first oxide layer;
etching to remove a part of the gate material layer and a part of the first oxide layer, exposing the surfaces of a part of the first well region and a part of the second well region, and the side wall and the bottom wall of a part of the first groove;
forming a side wall structure, wherein the side wall structure covers the exposed side wall of the grid electrode material layer;
and forming the grid structure by the rest of the etched grid material layer, the rest of the first oxide layer and the side wall structure.
4. The method of claim 1, wherein the source, the drain, the body region and the control region are formed by an ion implantation process; wherein the body region has a first conductivity type and the source, drain and control regions have a second conductivity type.
5. The method of claim 1, wherein after forming the source, the drain, the body, and the control region, the method further comprises:
forming a metal silicide blocking layer covering top surfaces of the source, the drain, the body region, the control region, and the gate structure.
6. The method of claim 5, wherein after forming the metal silicide blocking layer, the method further comprises:
and forming a plurality of metal contact structures, wherein the plurality of metal contact structures are respectively connected with the source electrode, the drain electrode, the body region, the control region and the grid electrode structure so as to electrically lead out the source electrode, the drain electrode, the body region, the control region and the grid electrode structure.
7. A multiple-time programmable memory, comprising:
the semiconductor device comprises a substrate, a first semiconductor layer and a second semiconductor layer, wherein the substrate comprises a first well region and a second well region, a first groove is formed in the first well region, and a second groove is formed in the second well region;
the grid structure covers part of the surface of the first well region and part of the surface of the second well region, fills the second groove, fills part of the first groove and exposes part of the side wall and the bottom wall of the first groove;
the source electrode is adjacent to the body region, the source electrode and the drain electrode are respectively positioned in the first well regions on two opposite sides of the grid structure, and the control region is positioned in the second well region; and the drain electrode is connected with the bottom wall of the exposed part of the first groove.
8. The multi-time programmable memory according to claim 7, wherein the gate structure comprises a first oxide layer, a gate material layer and a sidewall structure; wherein the content of the first and second substances,
the first oxidation layer covers part of the surface of the first well region, part of the surface of the second well region, the side wall and the bottom wall of the second groove, and part of the side wall and the bottom wall of the first groove;
the grid material layer covers the first oxide layer, fills the second groove and fills part of the first groove;
the side wall structure covers the exposed side wall of the grid material layer.
9. The multi-time programmable memory of claim 7, further comprising a shallow trench isolation structure, a metal silicide block layer, and a plurality of metal contact structures; the shallow trench isolation structure is arranged in the substrate and surrounds the first well region and the second well region; the metal silicide blocking layer covers the source, the drain, the body region, the control region and a top surface of the gate structure; the metal contact structures are respectively connected with the source electrode, the drain electrode, the body region, the control region and the grid electrode structure so as to electrically lead out the source electrode, the drain electrode, the body region, the control region and the grid electrode structure.
10. The memory of claim 7, wherein the first well region and the body region have a first conductivity type, and the second well region, the source, the drain, and the control region have a second conductivity type.
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