CN117219500B - Integrated structure of transistor device and flash memory and integrated method thereof - Google Patents
Integrated structure of transistor device and flash memory and integrated method thereof Download PDFInfo
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- 229910052581 Si3N4 Inorganic materials 0.000 description 1
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
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Abstract
The invention provides an integrated structure of a transistor device and a flash memory and an integrated method thereof. The integration method comprises the following steps: providing a substrate, and forming a conductive material layer on the substrate, wherein the conductive material layer covers the top surface of the substrate of the flash memory area and the gate groove in the transistor area; and performing an etching process on the conductive material layer to form a floating gate or a control gate of the flash memory in the flash memory region, and forming a gate electrode of the transistor device in the transistor region by using the conductive material in the gate trench. That is, the integration method provided by the invention can integrate the flash memory and the transistor device on the same chip, thereby being beneficial to realizing miniaturization of products. Also, in the integration method, the control gate (or floating gate) in the flash memory and the gate electrode in the transistor device are simultaneously prepared using the same conductive material layer, so that the integration process is simplified.
Description
Technical Field
The present invention relates to the field of semiconductor technologies, and in particular, to an integrated structure of a transistor device and a flash memory and an integration method thereof.
Background
Flash memory (e.g., embedded flash e-flash) has been widely used in various fields including smart cards, MCUs, power/battery management chips, display driver chips, etc. due to its very strong reliability, high-speed erasing operation, etc. And, transistors are semiconductor devices commonly used in the semiconductor field, which are also applied in large numbers in various fields. The transistor device and the flash memory are not generally integrated on the same chip due to the large difference of the structures and the processes of the transistor device and the flash memory, which is not beneficial to realizing miniaturization of products.
Disclosure of Invention
The invention aims to provide an integration method of a transistor device and a flash memory, which is used for simplifying an integration process while realizing the integration setting of the transistor device and the flash memory.
The invention provides an integration method of a transistor device and a flash memory, which comprises the following steps: providing a substrate, wherein the substrate is provided with a flash memory area and a transistor area, and a grid groove is formed in the transistor area; forming a conductive material layer on the substrate, wherein the conductive material layer covers the top surface of the substrate of the flash memory region and the gate groove in the transistor region; and performing an etching process on the conductive material layer to form a floating gate or a control gate of the flash memory in the flash memory region, and forming a gate electrode of the transistor device in the transistor region by using the conductive material in the gate trench.
Optionally, the transistor device comprises a shielded gate field effect transistor. Wherein, before forming the conductive material layer, further comprising: filling a shielding electrode material layer in the grid electrode groove of the transistor region; etching back the shielding electrode material layer to reduce the height of the shielding electrode material layer in the grid electrode groove so as to form a shielding electrode of the transistor device; and forming an isolation layer on a top surface of the shielding electrode.
Optionally, before forming the conductive material layer, forming a floating gate of the flash memory on a top surface of a substrate of the flash memory region; and forming the conductive material layer and etching the conductive material layer to form a control gate of the flash memory and a gate electrode of the transistor device. And after filling the shielding electrode material layer in the gate trench of the transistor region and before etching back the shielding electrode material layer, sequentially forming a first oxide layer and a floating gate on the top surface of the substrate of the flash memory region.
Optionally, after forming the floating gate, forming a second oxide layer on a top surface of the floating gate, and etching back the shielding electrode material layer after forming the second oxide layer.
Optionally, before forming the conductive material layer, forming a floating gate of the flash memory on a top surface of a substrate of the flash memory region; and forming the conductive material layer and etching the conductive material layer to form a control gate of the flash memory and a gate electrode of the transistor device. The thickness of the conductive material layer is set according to the thickness requirement of a control gate in the flash memory.
Optionally, when forming the conductive material layer, the conductive material layer conformally covers the trench sidewall of the gate trench and the top surface of the isolation layer. And performing an etching process on the conductive material layer includes: forming a mask layer on the conductive material layer, wherein the mask layer covers a region corresponding to a control gate in the flash memory region and also exposes the transistor region; etching the conductive material layer under the mask of the mask layer to remove the exposed conductive material in the flash memory region and retain the conductive material covered by the mask layer to form the control gate; and removing the conductive material on the top surface of the substrate of the transistor region and the conductive material in the central region of the isolation layer, while the portion of the conductive material layer covering the sidewall of the gate trench is left to constitute the gate electrode.
Alternatively, the gate trench is extended in a predetermined direction to form a stripe-shaped trench, the gate electrode is overlaid on trench sidewalls in the extending direction of the stripe-shaped trench, and the gate electrodes separated on the trench sidewalls on opposite sides are connected to each other at end positions of the gate trench.
Optionally, before forming the conductive material layer, sequentially forming a first oxide layer and a floating gate of the flash memory on the top surface of the substrate of the flash memory region; and forming the conductive material layer and etching the conductive material layer to form a control gate of the flash memory and a gate electrode of the transistor device. Wherein prior to forming the conductive material layer, further comprising: a second oxide layer is formed on the top surface of the floating gate and a gate dielectric layer is formed on the inner walls of the gate trench.
Optionally, forming the conductive material layer and etching the conductive material layer to form a floating gate of the flash memory and a gate electrode of the transistor device; and after forming the floating gate, further comprising: and forming a control gate in the flash memory region.
The invention also provides an integrated structure of the transistor device and the flash memory, comprising: a substrate having a flash memory region and a transistor region; a transistor device formed in a transistor region of the substrate, a gate trench formed in the substrate of the transistor region, a gate electrode of the transistor device formed in the gate trench; and the flash memory is formed in the flash memory area of the substrate, the flash memory comprises a floating gate and a control gate, and one of the floating gate and the control gate and the gate electrode are prepared by adopting the same conductive material layer.
The invention also provides a semiconductor integrated circuit comprising the integrated structure.
The invention also provides a preparation method of the semiconductor integrated circuit, which comprises the integration method; alternatively, it includes fabricating a semiconductor integrated circuit using the integrated structure as described above.
In the method for integrating the transistor device and the flash memory, the flash memory (e.g. e-flash) and the transistor device (e.g. SGT) can be integrated on the same chip, which is beneficial to realizing miniaturization of products. In addition, in the integration method, the same conductive material layer is adopted to simultaneously prepare the control gate (or floating gate) of the flash memory and the gate electrode in the transistor device, so that the integration process is simplified.
In addition, the preparation process of the transistor device and the preparation process of the flash memory can be subjected to fusion adjustment, so that the problem that the preparation processes of different devices are mutually influenced is solved. For example, after the gate trench of the transistor region is filled with the shielding electrode material layer, the flash memory region (including the processing process of the first well region, the first oxide layer and the floating gate) may be processed, even if the top of the shielding electrode material layer is damaged, the top of the shielding electrode material layer will be removed in a subsequent step, so that the finally formed shielding electrode is not affected, but the gate trench is protected by the shielding electrode material layer and is prevented from being affected by the manufacturing process of the flash memory, so as to ensure the performance of the finally formed transistor device.
Drawings
Fig. 1 is a flow chart of a method for integrating a transistor device and a flash memory according to an embodiment of the invention.
Fig. 2-10 are schematic diagrams illustrating the structure of an integrated structure of a transistor device and a flash memory in accordance with an embodiment of the present invention during the fabrication process.
Fig. 11 and 12 are layouts of an integrated structure of a transistor device and a flash memory in an embodiment of the present invention.
Wherein, the reference numerals are as follows: 100-a substrate; 100A-flash memory area; 100B-transistor region; 210-field oxide layer; 220 a-a shielding electrode material layer; 220-shielding the electrode; 230-isolating layer; 240-gate dielectric layer; 250-gate electrode; 260-a second well region; 270-source region; 310-a first well region; 320-a first oxide layer; 330-floating gate; 340-side walls; 350-a second oxide layer; 360-control gate; 370-source and drain regions; 400-mask layer; 500-a layer of conductive material; 600-conductive plugs.
Detailed Description
As mentioned in the background, the transistor device and the flash memory are not typically integrated on the same chip in the prior art. In the trend of miniaturization of products, it is necessary to provide a method for integrally providing a transistor device and a flash memory. One of the methods for integrally setting the transistor device and the flash memory includes, for example: the flash memory is formed in one region of a substrate using a process for manufacturing the flash memory, and then the transistor device is formed in another region using a process for manufacturing the transistor device. The integration method has more steps and affects the production efficiency.
In this regard, the present invention provides an integration method of a transistor device and a flash memory, which can realize integrated arrangement of the transistor device and the flash memory on the same chip and is also advantageous in simplifying the integration process. Referring to fig. 1, the method for integrating a transistor device and a flash memory according to an embodiment of the present invention includes the following steps.
In step S100, a substrate is provided, the substrate having a flash memory region and a transistor region, the transistor region having a gate trench formed therein.
In step S200, a conductive material layer is formed on the substrate, wherein the conductive material layer covers the top surface of the substrate of the flash memory region and the gate trench in the transistor region.
In step S300, an etching process is performed on the conductive material layer to form a floating gate or a control gate of the flash memory in the flash memory region, and the conductive material in the gate trench is used to form a gate electrode of the transistor device.
The integrated structure of the transistor device and the flash memory and the integrated method thereof according to the present invention are described in further detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention. It will be appreciated that relative terms such as "above," "below," "top," "bottom," "above," and "below" as illustrated in the figures may be used to describe various element relationships to one another. These relative terms are intended to encompass different orientations of the element in addition to the orientation depicted in the figures. For example, if the device is inverted relative to the view in the drawings, an element described as "above" another element, for example, will now be below the element.
In step S100, referring specifically to fig. 2, a substrate 100 is provided, the substrate 100 having a flash memory region 100A and a transistor region 100B. The flash memory region 100A is used to form a flash memory, and the transistor region 100B is used to form a transistor device, such as a power transistor device, and may be a trench transistor device. In this embodiment, an e-flash memory and an SGT transistor (i.e., a shielded gate field effect transistor) are taken as an example.
With continued reference to fig. 2, a gate trench is formed in the substrate of the transistor region 100B for accommodating the gate structure of the transistor device. Taking the SGT device as an example in this embodiment, the method may further include, after forming the gate trench: a field oxide layer 210 and a shield electrode material layer 220a are formed, the field oxide layer 210 covering at least the inner surface of the gate trench for separating the shield electrode from the inner wall of the gate trench. The field oxide layer 210 may be formed, for example, by an oxidation process, and may be provided to have a large thickness to secure the voltage-withstanding performance of the device. And, when preparing the shielding electrode material layer 220a, the electrode material may be filled in the gate trench by a deposition process, and at the same time, the electrode material may also cover the top surface of the substrate, and then the electrode material on the top surface of the substrate may be removed by an etching process, and the electrode material in the gate trench may be retained. The field oxide layer 210 may be maintained in this step to also cover the top surface of the substrate of the transistor region 100B and to fill the gate trench with the shield electrode material layer 220 a.
The subsequent process further comprises: a floating gate and a control gate are formed in the flash memory region 100A, and a gate electrode is formed in the transistor region 100B, in the gate trench, over the shield electrode. In a specific example, a gate electrode may be formed in the transistor region 100B while preparing a floating gate of the flash memory. Alternatively, in another example, a gate electrode may be formed in a transistor region while a control gate of a flash memory is being manufactured.
In this embodiment, a control gate of a flash memory and a gate electrode of a transistor device are prepared at the same time. Based on this, before the control gate is prepared in the flash memory region 100A, it further includes: a first well region 310, a first oxide layer 320, and a floating gate 330 are sequentially formed within the flash memory region 100A. Referring specifically to fig. 3, a first well region 310 may be formed in the substrate of the flash memory region 100A by using an ion implantation process, where the first well region 310 is, for example, a P-type doped region; next, a first oxide layer 320 is formed on the top surface of the substrate of the flash memory region 100A; thereafter, a floating gate 330 is formed on the first oxide layer 320. In addition, after the floating gate 330 is formed, a sidewall 340 may be further formed on the sidewall of the floating gate 330.
Referring next to fig. 4-6, before forming the control gate, the method further includes: a second oxide layer 350 is formed on the floating gate 330. In this embodiment, a LOCOS process may be used to form the second oxide layer 350 on the floating gate 330, which specifically includes: referring first to fig. 4, a mask layer 400 (the mask layer 400 includes, for example, a silicon nitride layer) is formed on the substrate 100, the mask layer 400 exposing a top surface of the floating gate 330; next, referring to fig. 5, an oxidation process is performed to form the second oxide layer 350 on the top surface of the exposed floating gate 330. In a specific example, the material of the floating gate 330 includes polysilicon, and thus the material of the oxidized second oxide layer 350 includes silicon oxide. Thereafter, the mask layer 400 may be removed.
As shown in fig. 5 and 6, the second oxide layer 350 is formed using a LOCOS process such that an end portion thereof has a beak structure, and accordingly, the floating gate 330 is adjusted to have a sharp corner shape at a position corresponding to the beak. The subsequently formed control gate covers the sharp corner region of the floating gate 330, so that a stronger tunneling electric field can be formed at the sharp corner position of the floating gate 330 when the memory is in an erasing operation, so that electrons in the floating gate 330 are more likely to tunnel, and the erasing operation is realized.
For the flash memory region 100A, a control gate fabrication process may be performed after the second oxide layer 350 is formed. And for the transistor region 100A, further including, before preparing the gate electrode: an etch back process is performed on the shielding electrode material layer 220a in the transistor region 100B to reduce the height of the shielding electrode material layer 220a in the gate trench, providing a receiving space for the subsequent preparation of the gate electrode.
It should be noted that, in the present embodiment, after the second oxide layer 350 is formed, the shielding electrode material layer 220A is etched back, at this time, the top surface of the substrate of the flash memory region 100A is covered with the first oxide layer 320, the floating gate 330 is covered with the second oxide layer 350, and the top surface of the substrate of the transistor region 100B is covered with the field oxide layer 210, so that other regions can be effectively protected from damage during the etching back of the shielding electrode material layer 220A.
Referring specifically to fig. 7, after forming the second oxide layer 350, the method further includes: etching back the shielding electrode material layer 220a to reduce the height of the shielding electrode material layer 220a to form a shielding electrode 220 located at a lower portion of the gate trench; next, an isolation layer 230 is formed on the top surface of the shield electrode 220, the isolation layer 230 being for isolating the shield electrode 220 and a gate electrode formed later; next, a portion of the field oxide layer 210 located above the isolation layer 230 is removed to expose trench sidewalls of the gate trench located above the isolation layer 230; thereafter, a gate dielectric layer 240 may be formed on the exposed trench sidewalls using an oxidation process, wherein the thickness of the gate dielectric layer 240 may be correspondingly set according to the threshold voltage of the formed transistor device and other related properties.
Thereafter, a control gate may be formed in the flash memory region 100A and a gate electrode may be formed in the transistor region 100B, specifically referring to step S200 below.
In step S200, referring specifically to fig. 8, a conductive material layer 500 is formed on the substrate 100, the conductive material layer 500 covering the substrate top surface of the flash memory region 100A and the gate trench in the transistor region 100B. The material of the conductive material layer 500 may include polysilicon, for example.
In a specific example, the thickness of the conductive material layer 500 may be set according to the thickness requirement for the control gate in the flash memory. For example, the thickness of the control gate in the flash memory is required to be 2500-3500 a, and the thickness of the conductive material layer 500 may be 2500-3500 a. It should be noted that, when the thickness of the conductive material layer 500 is set according to the thickness requirement of the control gate in the flash memory, the thickness of the control gate is generally thinner, so that the conductive material layer 500 with a corresponding thickness will not fill the gate trench in the transistor region 100B, i.e. the conductive material layer 500 will cover the trench sidewall of the gate trench and the top surface of the isolation layer 230 in a conformal manner. In this way, it is advantageous to form a discrete gate electrode with a smaller size in the gate trench, and the gate-source capacitance is reduced, which is specifically referred to in step S300.
In step S300, referring specifically to fig. 9, an etching process is performed on the conductive material layer 500 to form a control gate 360 of the flash memory in the flash memory region 100A, where the control gate 360 covers a portion of the second oxide layer 350 above the floating gate 330 and a sidewall on a sidewall of the floating gate 330, and further extends to the first oxide layer 320, so that the control gate 360 can cover a sharp corner region of the floating gate 330; and, in the transistor region 100B, a gate electrode 250 of the transistor device is formed using the conductive material in the gate trench.
Specifically, a mask layer may be formed on the conductive material layer 500, covering an area corresponding to the control gate 360 within the flash memory region 100A, and also exposing the transistor region 100B; next, the conductive material layer 500 is etched under the mask of the mask layer to remove the conductive material exposed in the flash memory region 100A and to remain the conductive material covered by the mask layer to form the control gate 360, and the conductive material on the top surface of the substrate of the transistor region 100B may be simultaneously etched away, the portion of the conductive material layer 500 covering the central region of the isolation layer 230 is removed, and the portion of the conductive material layer 500 covering the sidewalls of the gate trench is left to form the gate electrode 250. That is, in the present embodiment, during the process of patterning the conductive material layer in the flash memory region 100A by using the mask layer, the discrete gate electrode 250 can be formed in the gate trench of the transistor region 100B in a self-aligned manner, and the discrete gate electrode 250 reduces the overlapping area with the shielding electrode 220, so that the gate-source capacitance can be effectively reduced, and the driving loss and the switching loss of the device can be improved.
It should be noted that, in the above example, the conductive material layer 500 conformally covers the gate trench, but does not fill the gate trench, and further forms the discrete gate electrode 250. However, in other examples, the conductive material layer 500 may also fill the gate trench (e.g., the thickness of the conductive material layer 500 in this example is greater; or the opening size of the gate trench is smaller, etc.), and the formed gate electrode may also be made to be a structure that entirely fills the gate trench after etching the conductive material layer.
In a further aspect, referring specifically to fig. 10, the method further includes: performing an ion implantation process on the flash memory region 100A to form a source drain region 370 in the substrate, the source drain region 370 being specifically formed in the first well region 310 and being located at a side of the floating gate 330 away from the control gate 360 and a side of the control gate 360 away from the floating gate 330, respectively; and performing an ion implantation process on the transistor region 100B to form a second well region 260 and a source region 270 located within the second well region 260 within the substrate.
For a clearer illustration of the integrated structure of the transistor device and the flash memory, further description is provided below in connection with the layout of the integrated structure shown in fig. 11. As shown in fig. 11, a flash memory including a well region 310, a floating gate 330 and a control gate 360 formed over the well region 310, and source and drain regions 370 formed in the well region 310 at sides of the floating gate 330 and the control gate 360 is formed in the flash memory region 100A.
And forming a trench transistor device within the transistor region 100B, which specifically includes: a gate electrode 250 formed in the gate trench and a source region 270 located at the side of the gate trench. In a specific example, the gate trench extends along a predetermined direction to form an elongated trench, and the gate electrode 250 covers the trench sidewall of the gate trench along the extending direction of the elongated trench. Further, the gate electrodes 250 on the trench sidewalls on opposite sides may be connected to each other at the end portions of the gate trench, and the connection portions where the gate electrodes 250 are connected to each other may constitute a gate electrode lead-out region. In addition, the source regions 270 may also be arranged in a stripe shape to extend along the sides of the gate trench in compliance with the extending direction of the gate trench.
In a further aspect, referring specifically to fig. 12, the integration method further includes: an interconnect structure is formed for electrically extracting the flash memory in the flash region 100A and the transistor devices in the transistor region 100B. The preparation method of the interconnection structure specifically comprises the following steps: forming an interlayer dielectric layer on the substrate, wherein the interlayer dielectric layer covers the flash memory region 100A and the transistor region 100B; next, a plurality of conductive plugs 600 are formed in the interlayer dielectric layer, the plurality of conductive plugs 600 including conductive plugs electrically connecting the source drain regions 370 and the control gates 360 in the flash memory device and further including conductive plugs electrically connecting the gate electrodes 250 and the source regions 270 in the transistor device.
In the above embodiments, the control gate of the flash memory and the gate electrode of the transistor device are prepared at the same time. However, in other embodiments, it is also possible to prepare both the floating gate of the flash memory and the gate electrode of the transistor device. The specific steps include, for example: in step S100, a gate trench may be formed in the transistor region as well, and before performing step S200, a first oxide layer 320 may be formed on the top surface of the substrate of the flash memory region 100A, and a gate dielectric layer 240 may be formed on the inner wall of the gate trench of the transistor region 100B; next, step S200 and step S300 are performed to form a conductive material layer and etch the conductive material layer, forming the floating gate 330 of the flash memory and the gate electrode 250 of the transistor device. Thereafter, processing may continue with flash memory region 100A to form control gate 360 within flash memory region 100A.
Based on the above-mentioned integration method, there is further provided an integration structure of a transistor device and a flash memory, specifically referring to fig. 10 to 12, the integration structure includes: the substrate 100 has a flash memory region 100A and a transistor region 100B, wherein the flash memory region 100A has a flash memory formed therein and the transistor region 100B has a transistor device formed therein.
Specifically, the substrate of the transistor region 100B has a gate trench formed therein, and the gate electrode 250 of the transistor device is formed in the gate trench. For example, as shown in fig. 11, the gate trench may be extended in a predetermined direction to be formed as an elongated trench. In a specific example, a separate gate electrode 250 may be disposed within the gate trench, the gate electrode 250 being formed specifically on the trench sidewalls of the gate trench. For the elongated gate trench, the gate electrode 250 covers the trench sidewall of the gate trench along the extending direction of the elongated trench. Further, the gate electrodes 250 on the trench sidewalls on opposite sides may be connected to each other at the end portions of the gate trench, and the connection portions where the gate electrodes 250 are connected to each other may constitute a gate electrode lead-out region. And the transistor device further comprises a source region 270 forming a side of the gate trench, which source region 270 may likewise extend along the side of the gate trench in conformity with the direction of extension of the gate trench and be arranged in a stripe shape.
In a specific example, the transistor device is a power transistor device, for example, including a shielded gate field effect transistor (SGT device), where a shielding electrode 220 is further formed in the gate trench, the shielding electrode 220 is located below the gate electrode 250, and the shielding electrode 220 and the gate electrode 250 are separated from each other by an isolation layer 230.
With continued reference to fig. 10-12, the flash memory includes a floating gate 330 and a control gate 360, and the control gate 360 may partially cover the floating gate 330 and extend onto the top surface of the substrate on one side of the floating gate 330. Wherein one of the floating gate 330 and the control gate 360 in the flash memory is fabricated using the same conductive material layer as the gate electrode 250 in the transistor device, thus the floating gate 330 or the control gate 360 is made of the same material as the gate electrode 250, for example, each comprises a polysilicon material.
There is also provided a semiconductor integrated circuit specifically including or fabricated using the integrated structure as described above, that is, the semiconductor integrated circuit in this embodiment has the transistor device and the flash memory as described above integrated on the same substrate.
In a specific example, the semiconductor integrated circuit has, for example, a BCD device and a VIP device (i.e., a vertical device), which are formed on the same substrate. The BCD devices may include bipolar transistors, CMOS transistors, and DMOS transistors, among others, and VIP devices may include SGT devices, IGBT devices, and the like, for example. The flash memory may be integrated in the device region of the BCD device, or an area may be defined on the substrate for integrated arrangement of the flash memory.
And a method of manufacturing the semiconductor integrated circuit, a corresponding integrated method including the transistor device and the flash memory as described above, or a method of manufacturing the semiconductor integrated circuit using the integrated structure as described above. When the integration method as described above is utilized, the integration process can be simplified while the integration setting of the transistor device and the flash memory is also achieved.
It should be noted that, in the present description, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different manner from other embodiments, and identical and similar parts between the embodiments are all enough to refer to each other. And, while the present invention has been disclosed in terms of preferred embodiments, the above embodiments are not intended to limit the present invention. Many possible variations and modifications of the disclosed technology can be made by anyone skilled in the art without departing from the scope of the technology, or the technology can be modified to be equivalent. Therefore, any simple modification, equivalent variation and modification of the above embodiments according to the technical substance of the present invention still fall within the scope of the technical solution of the present invention.
It should be further understood that the terms "first," "second," "third," and the like in this specification are used merely for distinguishing between various components, elements, steps, etc. in the specification and not for indicating a logical or sequential relationship between the various components, elements, steps, etc., unless otherwise indicated. It should also be recognized that, as used herein and in the appended claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. For example, reference to "a step" or "an apparatus" means a reference to one or more steps or apparatuses, and may include sub-steps as well as sub-apparatuses.
Claims (12)
1. An integration method of a transistor device and a flash memory, comprising:
providing a substrate, wherein the substrate is provided with a flash memory area and a transistor area for forming a vertical shielding grid field effect transistor, and a grid groove is formed in the substrate of the transistor area;
forming a shielding electrode and an isolation layer in the grid electrode groove of the transistor area in sequence, wherein the isolation layer is formed on the top surface of the shielding electrode;
forming a conductive material layer on the substrate, wherein the conductive material layer covers the top surface of the substrate of the flash memory region and the gate groove in the transistor region; the method comprises the steps of,
and performing an etching process on the conductive material layer to form a floating gate or a control gate of the flash memory in the flash memory region, and forming a gate electrode of the transistor device in the transistor region by using the conductive material in the gate trench.
2. The method of integrating a transistor device and a flash memory of claim 1, wherein the method of forming the shielding electrode comprises:
filling a shielding electrode material layer in the grid electrode groove of the transistor region;
and etching the shielding electrode material layer back to reduce the height of the shielding electrode material layer in the grid groove so as to form the shielding electrode of the transistor device.
3. The method of integrating a transistor device and a flash memory of claim 2, wherein forming the conductive material layer is preceded by forming a floating gate of the flash memory on a top surface of a substrate of the flash memory region; and forming the conductive material layer and etching the conductive material layer to form a control gate of the flash memory and a gate electrode of the transistor device;
and after filling the shielding electrode material layer in the gate trench of the transistor region and before etching back the shielding electrode material layer, sequentially forming a first oxide layer and a floating gate on the top surface of the substrate of the flash memory region.
4. The method of integrating a transistor device and a flash memory of claim 3, further comprising forming a second oxide layer on a top surface of the floating gate after forming the floating gate, and etching back the shield electrode material layer after forming the second oxide layer.
5. The method of integrating a transistor device and a flash memory of claim 2, wherein forming the conductive material layer is preceded by forming a floating gate of the flash memory on a top surface of a substrate of the flash memory region; and forming the conductive material layer and etching the conductive material layer to form a control gate of the flash memory and a gate electrode of the transistor device;
the thickness of the conductive material layer is set according to the thickness requirement of a control gate in the flash memory.
6. The method of integrating a transistor device and a flash memory device of claim 5, wherein the layer of conductive material conformally covers trench sidewalls of the gate trench and a top surface of the isolation layer when forming the layer of conductive material; and performing an etching process on the conductive material layer includes:
forming a mask layer on the conductive material layer, wherein the mask layer covers a region corresponding to a control gate in the flash memory region and also exposes the transistor region; the method comprises the steps of,
etching the conductive material layer under the mask of the mask layer to remove the exposed conductive material in the flash memory region and reserving the conductive material covered by the mask layer to form the control gate; and removing the conductive material on the top surface of the substrate of the transistor region and the conductive material in the central region of the isolation layer, while the portion of the conductive material layer covering the sidewall of the gate trench is left to constitute the gate electrode.
7. The method of integrating a transistor device and a flash memory according to claim 6, wherein the gate trench is extended in a predetermined direction to form a stripe-shaped trench, the gate electrode is covered on trench sidewalls in the extending direction of the stripe-shaped trench, and gate electrodes on the trench sidewalls which are separated on opposite sides are connected to each other at end positions of the gate trench.
8. The method of integrating a transistor device and a flash memory of claim 1, wherein a first oxide layer and a floating gate of the flash memory are sequentially formed on a top surface of a substrate of the flash memory region prior to forming the conductive material layer; and forming the conductive material layer and etching the conductive material layer to form a control gate of the flash memory and a gate electrode of the transistor device;
wherein prior to forming the conductive material layer, further comprising: a second oxide layer is formed on the top surface of the floating gate and a gate dielectric layer is formed on the inner walls of the gate trench.
9. The method of integrating a transistor device and a flash memory of claim 1, wherein forming the layer of conductive material and etching the layer of conductive material to form a floating gate of the flash memory and a gate electrode of the transistor device; and after forming the floating gate, further comprising: and forming a control gate in the flash memory region.
10. An integrated structure of a transistor device and a flash memory, comprising:
a substrate having a flash memory region and a transistor region;
the transistor device comprises a longitudinal shielding gate field effect transistor, a gate groove is formed in the substrate of the transistor region, a shielding electrode, an isolation layer and a gate electrode of the transistor device are formed in the gate groove from bottom to top, and the isolation layer is located between the shielding electrode and the gate electrode;
and the flash memory is formed in the flash memory area of the substrate, the flash memory comprises a floating gate and a control gate, and one of the floating gate and the control gate and the gate electrode are prepared by adopting the same conductive material layer.
11. A semiconductor integrated circuit comprising the integrated structure of claim 10.
12. A method for manufacturing a semiconductor integrated circuit, characterized by comprising the integration method according to any one of claims 1 to 9; alternatively, it comprises fabricating a semiconductor integrated circuit using the integrated structure of claim 10.
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| CN107591402B (en) * | 2016-07-06 | 2021-03-16 | 联华电子股份有限公司 | Integrated circuit and manufacturing method thereof |
| US10164074B2 (en) * | 2016-11-25 | 2018-12-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device with gate electrode embedded in substrate |
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