CN111477626B - Semi-floating gate memory and preparation method thereof - Google Patents

Abstract

The invention discloses a semi-floating gate memory and a preparation method thereof. The semi-floating gate memory comprises: a semiconductor substrate having a first doping type; a semi-floating gate well region, which has a second doping type and is positioned in the upper region of the semiconductor substrate; the U-shaped groove penetrates through the semi-floating gate well region, and the bottom of the U-shaped groove is positioned at the lower boundary of the semi-floating gate well region; the first gate dielectric layer covers the surface of the U-shaped groove; the floating gate covers the first gate dielectric layer and forms a convex shape with a high middle part and low two sides; the tunneling transistor channel layer covers the upper surface of the middle bulge of the floating gate; the second gate dielectric layer is formed on two sides of the tunneling transistor channel layer and extends to cover the surface of the floating gate, and the control gate covers the second gate dielectric layer and the upper surface of the tunneling transistor channel layer; the grid side walls are positioned on two sides of the first grid laminated layer and the second grid laminated layer; and the source electrode and the drain electrode are formed in the semi-floating gate well region and are positioned at two sides of the first grid laminated layer and the second grid laminated layer.

Description

Semi-floating gate memory and preparation method thereof

Technical Field

The invention relates to the technical field of integrated circuit memories, in particular to a semi-floating gate memory and a preparation method thereof.

Background

At present, the DRAM device used in the integrated circuit chip mainly has a 1T1C structure, that is, a transistor is connected in series with a capacitor, and the capacitor is charged and discharged through the switch of the transistor, so as to realize the conversion between the DRAM devices 0 and 1. As device sizes become smaller, DRAM devices used in integrated circuit chips are facing increasing problems, such as DRAM devices requiring a 64ms refresh, and therefore the capacitance of the capacitor must be maintained above a certain value to ensure a sufficiently long charge retention time. However, as the feature size of integrated circuits shrinks, the fabrication of large capacitors has become more difficult and has made more than 30% of the fabrication cost.

The semi-floating gate memory is an alternative concept of a DRAM device, and is different from a common 1T1C structure, the semi-floating gate device is composed of a floating gate transistor and an embedded tunneling transistor, and the floating gate of the floating gate transistor is written and erased through a channel of the embedded tunneling transistor. However, in the conventional planar semi-floating gate memory device, the tunneling transistor is located between the floating gate and the drain, that is, the tunneling transistor needs to occupy a part of the chip area, which reduces the integration density of the chip.

Disclosure of Invention

In order to solve the above problems, the present invention discloses a semi-floating gate memory, wherein a charge transfer channel is established between a control gate and a floating gate, that is, a tunneling transistor is arranged between the floating gate and the control gate, and the floating gate of the floating gate memory is written and erased by the tunneling transistor. This is a kind of vertical charge transfer channel, so it does not occupy extra chip area, and it will not cause the decrease of integration level.

Specifically, the 1-half floating gate memory comprises: a semiconductor substrate having a first doping type; the semi-floating gate well region is provided with a second doping type and is positioned in the upper region of the semiconductor substrate; the U-shaped groove penetrates through the semi-floating gate well region, and the bottom of the U-shaped groove is positioned at the lower boundary of the semi-floating gate well region; the first grid electrode lamination comprises a first grid electrode medium layer, a floating grid electrode and a tunneling transistor channel layer, wherein the first grid electrode medium layer covers the surface of the U-shaped groove; the floating gate covers the first gate dielectric layer and is in a convex shape with a high middle part and low two sides; the tunneling transistor channel layer covers the upper surface of the middle bulge of the floating gate; the second grid laminated layer comprises a second grid dielectric layer and a control grid, the second grid dielectric layer is formed on two sides of the tunneling transistor channel layer and extends to cover the surface of the floating grid, and the control grid covers the second grid dielectric layer and the upper surface of the tunneling transistor channel layer; the grid side walls are positioned on two sides of the first grid laminated layer and the second grid laminated layer; and the source electrode and the drain electrode are formed in the semi-floating gate well region and are positioned at two sides of the first grid laminated layer and the second grid laminated layer.

In the semi-floating gate memory of the invention, preferably, the first gate dielectric layer and the second gate dielectric layer are made of SiO₂、Al₂O₃、ZrO₂、HfZrO、HfO₂HfAlO, HfSiO, and any combination thereof.

In the semi-floating gate memory of the present invention, preferably, the floating gate is a heavily doped polysilicon layer of the first doping type.

In the semi-floating gate memory of the present invention, preferably, the channel layer of the tunneling transistor is lightly doped polysilicon of the second doping type.

In the semi-floating gate memory of the present invention, preferably, the control gate is a heavily doped polysilicon layer of the second doping type.

In the semi-floating gate memory of the present invention, preferably, the control gate is TiN, TaN, MoN or WN.

The invention also discloses a preparation method of the semi-floating gate memory, which comprises the following steps: providing a semiconductor substrate with a first doping type; forming a semi-floating gate well region with a second doping type in an upper region of the semiconductor substrate; etching the semi-floating gate well region to form a U-shaped groove, so that the U-shaped groove penetrates through the semi-floating gate well region, and the bottom of the U-shaped groove is positioned at the lower boundary of the semi-floating gate well region; forming a first grid laminated layer, sequentially forming a first grid medium layer, a floating grid and a tunneling transistor channel layer, enabling the first grid medium layer to cover the surface of the U-shaped groove, enabling the floating grid to cover the first grid medium layer and form a convex shape with a high middle part and low two sides, and enabling the tunneling transistor channel layer to cover the upper surface of the middle protrusion of the floating grid; forming a second grid laminated layer, and sequentially forming a second grid dielectric layer and a control grid, so that the second grid dielectric layer is formed on two sides of the tunneling transistor channel layer and extends to cover the surface of the floating grid, and the control grid covers the second grid dielectric layer and the upper surface of the tunneling transistor channel layer; forming grid side walls on two sides of the first grid laminated layer and the second grid laminated layer; and forming a source electrode and a drain electrode on two sides of the first grid laminated layer and the second grid laminated layer in the semi-floating grid well region.

In the method for manufacturing a semi-floating gate memory of the present invention, preferably, the floating gate is a heavily doped polysilicon layer of a first doping type

In the method for manufacturing a semi-floating gate memory of the present invention, preferably, the channel layer of the tunneling transistor is a lightly doped polysilicon of the second doping type

In the method for manufacturing the semi-floating gate memory, preferably, the control gate is a heavily doped polysilicon layer of a second doping type, or the control gate is TiN, TaN, MoN or WN.

Drawings

FIG. 1 is a flow chart of a method for manufacturing a semi-floating gate memory according to the present invention.

Fig. 2 is a schematic diagram of the device structure after oxide formation.

Fig. 3 is a schematic diagram of the device structure after forming the semi-floating gate well region.

Fig. 4 is a schematic diagram of the device structure after forming the U-shaped groove.

Fig. 5 is a schematic diagram of the device structure after oxide removal.

FIGS. 6-9 are schematic device structures of steps for forming a first gate stack.

FIGS. 10-13 are schematic device structures of steps for forming a second gate stack.

Fig. 14 is a schematic structural diagram of the device after forming the gate sidewall spacers.

Fig. 15 is a schematic diagram of the device structure of the semi-floating gate memory of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more clearly and completely understood, the technical solutions in the embodiments of the present invention will be described below with reference to the accompanying drawings in the embodiments of the present invention, and it should be understood that the specific embodiments described herein are only for explaining the present invention and are not intended to limit the present invention. The described embodiments are only some embodiments of the invention, not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

In the description of the present invention, it should be noted that the terms "upper", "lower", "vertical", "horizontal", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience in describing the present invention and simplifying the description, but do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.

Furthermore, numerous specific details of the invention, such as structure, materials, dimensions, processing techniques and techniques of the devices are described below in order to provide a more thorough understanding of the invention. However, as will be understood by those skilled in the art, the present invention may be practiced without these specific details. Unless otherwise indicated below, various portions of the device may be constructed of materials known to those skilled in the art, or materials developed in the future that serve similar functions may be used.

Fig. 1 is a flow chart of a method for manufacturing a semi-floating gate memory according to the present invention, and fig. 2 to 15 are schematic structural diagrams of steps of a method for manufacturing a novel semi-floating gate memory. As shown in fig. 1, the preparation method comprises the following specific steps: in step S1, a semiconductor substrate 200 having a first doping type is provided. The semiconductor substrate 200 may be a suitable substrate in various forms, such as a bulk semiconductor substrate such as Si, Ge, etc., and a compound semiconductor substrate such as SiGe, GaAs, GaSb, AlAs, InAs, InP, GaN, SiC, InGaAs, InSb, InGaSb, etc., a semiconductor-on-insulator Substrate (SOI), etc. For convenience of explanation, the following description will be made taking a Si substrate as an example. A layer of oxide 202, typically SiO, is then grown on the surface of the semiconductor substrate 200₂Mainly to avoid defects caused by the direct ion bombardment of the semiconductor substrate itself, the resulting structure is shown in fig. 2.

In step S2, a semi-floating gate well region 201 having a second doping type is formed. Specifically, a well 201 having the second doping type is formed in the surface region of the semiconductor substrate 200 by ion implantation, and the resulting structure is shown in fig. 3. In this embodiment, the first doping type is p-type, the second doping type is n-type, that is, the semiconductor substrate 200 is a p-type doped substrate, and an n-type lightly doped well 201 is formed in a surface region thereof.

In step S3, a U-shaped groove is formed. Spin-coating photoresist, and defining the position of the U-shaped groove by photoetching processes such as exposure, development and the like. Patterning is performed by dry etching, such as ion milling etching, plasma etching, reactive ion etching, laser ablation, or wet etching using an etchant solution, so as to form a U-shaped trench in the semi-floating gate well region 201, such that the U-shaped trench penetrates through the semi-floating gate well region 201 and the bottom of the U-shaped trench is located at the lower boundary of the semi-floating gate well region 201, and the resulting structure is shown in fig. 4. Next, the oxide 202 is removed by the same photolithography and etching method as described above, and the resulting structure is shown in fig. 5.

In step S4, a first gate stack is formed, and a first gate dielectric layer, a floating gate and a tunneling transistor channel layer are sequentially formed from bottom to top. Specifically, the following steps are included, and the description is made with reference to fig. 6 to 9. Depositing HfO on the device structure by adopting an atomic layer deposition method₂The layer serves as a first gate dielectric layer 203 and the resulting structure is shown in fig. 6. HfO is selected in this embodiment₂The first gate dielectric layer is made of a material selected from the group consisting of SiO, although the invention is not limited thereto₂、Al₂O₃、ZrO₂、HfZrO、HfO₂HfAlO, HfSiO, and any combination thereof. The deposition method may also be physical vapor deposition, chemical vapor deposition, or pulsed laser deposition.

Then, a polysilicon layer is grown by a physical vapor deposition method, and a p-type heavily doped polysilicon layer is formed as the floating gate 204 by ion implantation, and the resulting structure is shown in fig. 7. A photoresist is then spun on the heavily p-doped polysilicon layer and patterned by a photolithography process that includes exposure and development to define the shape of the first gate stack. The both-end portion polysilicon layer is removed by dry etching such as ion mill etching, plasma etching, reactive ion etching, laser ablation, or wet etching using an etchant solution, thereby forming a convex shape with a high middle and low ends, and the photoresist is removed by dissolving or ashing in a solvent, and the resulting structure is shown in fig. 8.

Finally, spin-coating photoresist on the surface of the convex p-type heavily doped polysilicon layer, and forming a pattern by a photoetching process including exposure and development; forming n-type lightly doped polysilicon in the middle protruding region of the P-type heavily doped polysilicon layer by ion implantation; the remaining photoresist is removed and the resulting structure is shown in fig. 9. The bottom of the n-type lightly doped polysilicon is higher than the two ends of the p-type heavily doped polysilicon, and the n-type lightly doped polysilicon is used as the channel layer 205 of the tunneling transistor.

In step S5, a second gate stack is formed, and a second gate dielectric layer 206 and a control gate 207 are sequentially formed. Specifically, the following steps are included, and the description is made with reference to fig. 10 to 13. Depositing HfO on the device structure by adopting an atomic layer deposition method₂The layer serves as a second gate dielectric layer 206 and the resulting structure is shown in figure 10. However, the present invention is not limited thereto, and the second gate dielectric layer may be selected from SiO₂、Al₂O₃、ZrO₂、HfZrO、HfO₂HfAlO, HfSiO, and any combination thereof. A photoresist is then spun on the second gate dielectric layer 206 and patterned to define the floating gate opening by a photolithography process that includes exposure and development. Removing the second gate dielectric layer 206 over the channel layer 205 of the tunneling transistor by dry etching, such as ion mill etching, plasma etching, reactive ion etching, laser ablation, or by wet etching using an etchant solution; and the photoresist is removed by dissolving or ashing in a solvent, the resulting structure is shown in fig. 11.

Next, a polysilicon layer is grown by physical vapor deposition, and an n-type heavily doped polysilicon layer is formed as a control gate 208 by ion implantation, and the resulting structure is shown in fig. 12. However, the present invention is not limited thereto, and the control gate may be made of a metal material, for example, one selected from TiN, TaN, MoN, and WN. Finally, a photoresist is spin-coated on the control gate 208 and patterned to define the sidewall shape by a photolithography process including exposure and development. A portion of the first gate dielectric layer 203, the floating gate 204, the second gate dielectric layer 206 and the control gate 207 at both ends is removed by dry etching, such as ion milling etching, plasma etching, reactive ion etching, laser ablation, or wet etching using an etchant solution, and the resulting structure is shown in fig. 13.

In step S6, gate spacers are formed. Growing Si on the surface of the device by adopting a chemical vapor deposition method₃N₄Layer, then removing part of Si by photolithography and dry etching₃N₄Layer by layer, thereby forming spacers 208 on both sides of the first gate stack and the second gate stack, and the resulting structure is shown in fig. 14. Of course, the invention can also form the grid side wall by other deposition processes, such as electron beam evaporation, atomic layer deposition, sputtering and the like, and the material of the grid side wall can also be SiO for example₂Etc. insulating material.

In step S7, a source and a drain are formed. Spin-coating photoresist, and performing a photoetching process to define the shapes of the source electrode and the drain electrode. Depositing metal Ni by adopting a physical vapor deposition method, then removing the photoresist, and finally forming NiSi compounds as a source electrode 209 and a drain electrode 210 by adopting a laser annealing method, wherein the obtained structure is shown in FIG. 15. In this embodiment, NiSi is selected as the source/drain electrode. However, the present invention is not limited thereto, and the source-drain electrodes may be CoSi, TiSi, PtSi, NiPtSi, or the like.

As shown in fig. 15, the semi-floating gate memory of the present invention includes: a semiconductor substrate 200 having a first doping type; a semi-floating gate well region 201, which has a second doping type and is located in an upper region of the semiconductor substrate 200; a U-shaped groove penetrating the semi-floating gate well region 201, and the bottom of the U-shaped groove is located at the lower boundary of the semi-floating gate well region 201; the first grid laminated layer comprises a first grid dielectric layer 203, a floating grid 204 and a tunneling transistor channel layer 205, wherein the first grid dielectric layer 203 covers the surface of the U-shaped groove; the floating gate 204 covers the first gate dielectric layer 203 and forms a convex shape with a high middle part and two low sides; the tunneling transistor channel layer 205 covers the middle convex upper surface of the floating gate 204; a second gate stack including a second gate dielectric layer 206 and a control gate 207, wherein the second gate dielectric layer 206 is formed on both sides of the tunneling transistor channel layer 205 and extends to cover the surface of the floating gate 204, and the control gate 207 covers the second gate dielectric layer 206 and the upper surface of the tunneling transistor channel layer 205; gate spacers 208 positioned on both sides of the first gate stack and the second gate stack; and a source 209 and a drain 210 formed in the semi-floating gate well 201 on both sides of the first gate stack and the second gate stack.

The first gate dielectric layer 203 is preferably SiO₂、Al₂O₃、ZrO₂、HfZrO、HfO₂HfAlO, HfSiO, etc., or any combination thereof. Floating gate 204 is preferably a heavily doped polysilicon layer of the first doping type. The tunnel transistor channel layer 205 is a lightly doped polysilicon of a second doping type. The second gate dielectric layer 206 is SiO₂、Al₂O₃、ZrO₂、HfZrO、HfO₂HfAlO, HfSiO, and the like, or any combination thereof. The control gate 207 is a heavily doped polysilicon layer of the second doping type, or the control gate 207 is TiN, TaN, MoN or WN. The source and drain may be NiSi, CoSi, TiSi, PtSi, NiPtSi, etc.

In the above structure, the floating gate 204, the n-type lightly doped polysilicon layer (tunnel transistor channel layer) 205, the second gate dielectric layer 206 and the control gate 207 constitute a tunnel transistor. When a negative voltage is applied to the control gate, a diode formed between the p-type floating gate 204 and the n-type lightly doped polysilicon layer 205 is in a conducting state, and electrons flow into the floating gate 204 from the control gate 207 through the diode, so that the threshold voltage of the semi-floating gate memory changes, that is, the writing operation is completed. When a positive voltage is applied to the control gate, a diode formed between the p-type floating gate 204 and the n-type lightly doped polysilicon layer 205 is in a reverse bias state, but the control gate 207 simultaneously carries out energy band regulation on the n-type lightly doped polysilicon layer through the second gate dielectric 206 in the longitudinal direction, so that the conduction band bottom of the n-type lightly doped polysilicon layer moves downwards and is lower than the valence band top of the p-type floating gate, at this time, electrons in the valence band of the floating gate can tunnel into the conduction band of the n-type lightly doped polysilicon layer, and then the electrons flow back to the control gate from the floating gate, namely, the erasing operation is completed.

According to the invention, the tunneling transistor is built between the floating gate and the control gate, and a charge transmission channel is built longitudinally, so that the chip area is not occupied additionally, and the integration level is not reduced. In addition, the adoption of the U-shaped groove can increase the channel length of the floating gate transistor, so that the short-channel effect can be weakened. Moreover, the adopted process is completely compatible with the traditional CMOS process

The above description is only for the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention.

Claims (8)

1. A semi-floating gate memory device, comprising,

the method comprises the following steps:

a semiconductor substrate (200) having a first doping type;

a semi-floating gate well region (201) having a second doping type and located in an upper region of the semiconductor substrate (200);

the U-shaped groove penetrates through the semi-floating gate well region (201), and the bottom of the U-shaped groove is positioned at the lower boundary of the semi-floating gate well region (201);

a first gate stack comprising a first gate dielectric layer (203), a floating gate (204) and a tunneling transistor channel layer (205), wherein the first gate dielectric layer (203) covers the surface of the U-shaped groove; the floating gate (204) covers the first gate dielectric layer (203) and forms a convex shape with a high middle part and low two sides; the tunneling transistor channel layer (205) covers the middle convex upper surface of the floating gate (204);

a second gate stack comprising a second gate dielectric layer (206) and a control gate (207), wherein the second gate dielectric layer (206) is formed on two sides of the tunneling transistor channel layer (205) and extends to cover the surface of the floating gate (204), and the control gate (207) covers the second gate dielectric layer (206) and the upper surface of the tunneling transistor channel layer (205);

gate spacers (208) located on both sides of the first gate stack and the second gate stack;

a source (209) and a drain (210) formed in the semi-floating gate well region (201) on either side of the first and second gate stacks;

the tunnel transistor channel layer (205) is a lightly doped polysilicon of a second doping type.

2. The semi-floating gate memory of claim 1,

the first gate dielectric layer (203) and the second gate dielectric layer (206) are made of SiO₂、Al₂O₃、ZrO₂、HfZrO、HfO₂HfAlO, HfSiO, and any combination thereof.

3. The semi-floating gate memory of claim 1,

the floating gate (204) is a heavily doped polysilicon layer of a first doping type.

4. The semi-floating gate memory of claim 1,

the control gate (207) is a heavily doped polysilicon layer of a second doping type.

5. The semi-floating gate memory of claim 1,

the control gate (207) is TiN, TaN, MoN or WN.

6. A preparation method of a semi-floating gate memory is characterized in that,

the method comprises the following steps:

providing a semiconductor substrate (200) having a first doping type;

forming a semi-floating gate well region (201) having a second doping type in an upper region of the semiconductor substrate (200),

etching the semi-floating gate well region (201) to form a U-shaped groove, wherein the U-shaped groove penetrates through the semi-floating gate well region (201), and the bottom of the U-shaped groove is positioned at the lower boundary of the semi-floating gate well region (201);

forming a first grid laminated layer, sequentially forming a first grid medium layer (203), a floating grid (204) and a tunneling transistor channel layer (205), enabling the first grid medium layer to cover the surface of the U-shaped groove, enabling the floating grid (204) to cover the first grid medium layer (203) and form a protruding shape with a high middle part and two low sides, and enabling the tunneling transistor channel layer (205) to cover the upper surface of the protrusion in the middle of the floating grid (204);

forming a second gate stack, sequentially forming a second gate dielectric layer (206) and a control gate (207), so that the second gate dielectric layer (206) is formed on two sides of the tunneling transistor channel layer (205) and extends to cover the surface of the floating gate (204), and the control gate (207) covers the second gate dielectric layer (206) and the upper surface of the tunneling transistor channel layer (205);

forming gate side walls (208) on two sides of the first gate stack and the second gate stack;

forming a source (209) and a drain (210) on either side of the first gate stack and the second gate stack in the semi-floating gate well region;

the tunnel transistor channel layer (205) is a lightly doped polysilicon of a second doping type.

7. The method of claim 6, wherein the step of forming the floating gate memory cell,

the floating gate (204) is a heavily doped polysilicon layer of a first doping type.

8. The method of claim 6, wherein the step of forming the floating gate memory cell,

the control gate (207) is a heavily doped polysilicon layer of a second doping type, or the control gate is TiN, TaN, MoN or WN.

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