CN111508960B - Low-operating-voltage semi-floating gate memory and preparation method thereof - Google Patents

Low-operating-voltage semi-floating gate memory and preparation method thereof Download PDF

Info

Publication number
CN111508960B
CN111508960B CN202010346656.4A CN202010346656A CN111508960B CN 111508960 B CN111508960 B CN 111508960B CN 202010346656 A CN202010346656 A CN 202010346656A CN 111508960 B CN111508960 B CN 111508960B
Authority
CN
China
Prior art keywords
gate
semi
dielectric layer
floating gate
grid
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202010346656.4A
Other languages
Chinese (zh)
Other versions
CN111508960A (en
Inventor
朱宝
陈琳
孙清清
张卫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fudan University
Shanghai IC Manufacturing Innovation Center Co Ltd
Original Assignee
Fudan University
Shanghai IC Manufacturing Innovation Center Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fudan University, Shanghai IC Manufacturing Innovation Center Co Ltd filed Critical Fudan University
Priority to CN202010346656.4A priority Critical patent/CN111508960B/en
Publication of CN111508960A publication Critical patent/CN111508960A/en
Application granted granted Critical
Publication of CN111508960B publication Critical patent/CN111508960B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/20—DRAM devices comprising floating-body transistors, e.g. floating-body cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment

Abstract

The invention belongs to the technical field of integrated circuit memories, and particularly relates to a low-operating-voltage semi-floating gate memory and a preparation method thereof. The semi-floating gate memory of the invention comprises: a semiconductor substrate having a first doping type; a semi-floating gate well region having a second doping type; the U-shaped groove penetrates through the semi-floating gate well region, and the bottom of the U-shaped groove is positioned at the lower boundary of the semi-floating gate well region; the first gate dielectric layer covers the surface of the U-shaped groove; the first metal gate covers the first gate dielectric layer; the second gate dielectric layer covers the surface of the first metal gate and the surface of part of the semi-floating gate well region, the second metal gate covers the second gate dielectric layer, and the second gate dielectric layer and the second metal gate are both covered in the U-shaped groove; the grid side walls are positioned on two sides of the first grid laminated layer and the second grid laminated layer; and the source electrode and the drain electrode are positioned at two sides of the first grid laminated layer and the second grid laminated layer. The switching speed of the semi-floating gate transistor is increased, and the operating voltage is reduced; the control capability of the control gate on the channel near the U-shaped groove is greatly increased.

Description

Low-operating-voltage semi-floating gate memory and preparation method thereof
Technical Field
The invention belongs to the technical field of integrated circuit memories, and particularly relates to a low-operating-voltage semi-floating gate memory and a preparation method thereof.
Background
At present, the DRAM device used in an integrated circuit chip mainly has a 1T1C structure, that is, a transistor is connected in series with a capacitor, and the capacitor is charged and discharged through the switch of the transistor, so as to realize the conversion between DRAM devices 0 and 1. As device sizes become smaller, DRAM devices used in integrated circuit chips are facing increasing problems, such as DRAM devices requiring a 64ms refresh, and therefore the capacitance of the capacitor must be maintained above a certain value to ensure a sufficiently long charge retention time, but as the feature size of integrated circuits shrinks, the fabrication of large capacitors has become more difficult and has made up more than 30% of the fabrication cost. The semi-floating gate memory is an alternative concept of a DRAM device, and is different from a common 1T1C structure, the semi-floating gate device is composed of a floating gate transistor and an embedded tunneling transistor, and the floating gate of the floating gate transistor is written and erased through a channel of the embedded tunneling transistor. From the working principle of the semi-floating gate memory, it can be seen that the switching speed of the semi-floating gate memory is related to the control capability of the gate to the channel. Therefore, how to further improve the control capability of the gate of the tunneling transistor to the channel becomes a key for further improving the switching speed of the semi-floating gate collector and reducing the power consumption.
Disclosure of Invention
The invention aims to provide a low-operating-voltage semi-floating gate memory with high switching speed and low power consumption and a preparation method thereof.
The invention provides a low operating voltage semi-floating gate memory, comprising:
a semiconductor substrate having a first doping type;
the semi-floating gate well region is provided with a second doping type and is positioned in the upper region of the semiconductor substrate;
the U-shaped groove penetrates through the semi-floating gate well region, and the bottom of the U-shaped groove is positioned at the lower boundary of the semi-floating gate well region;
the first grid electrode lamination comprises a first grid electrode dielectric layer and a first metal grid; the first gate dielectric layer covers the surface of the U-shaped groove, and an opening is formed in the semi-floating gate well region; the first metal gate covers the first gate dielectric layer and is in contact with the semi-floating gate well region at the opening;
the second grid electrode lamination comprises a second grid electrode medium layer and a second metal grid, the second grid electrode medium layer covers the surface of the first metal grid and part of the surface of the semi-floating grid well region, the second metal grid covers the second grid electrode medium layer, and the second grid electrode medium layer and the second metal grid are both covered in the U-shaped groove;
the grid side walls are positioned on two sides of the first grid laminated layer and the second grid laminated layer;
and the source electrode and the drain electrode are formed in the semi-floating gate well region and are positioned at two sides of the first gate stack and the second gate stack.
In the low-operating-voltage semi-floating gate memory, preferably, the first gate dielectric layer and the second gate dielectric layer are made of SiO 2 、Al 2 O 3 、ZrO 2 、HfZrO、HfO 2 One of HfAlO and HfSiO, or the combination of any of the above.
In the low-operating-voltage semi-floating gate memory, preferably, the first metal gate and the second metal gate are one of TiN, TaN, Ru and Co, or a combination of any of TiN, TaN, Ru and Co.
In the low-operating-voltage semi-floating gate memory, the thickness of the first metal gate is preferably between 3nm and 5 nm.
In the low-operating-voltage semi-floating gate memory of the present invention, preferably, the source electrode and the drain electrode are NiSi, CoSi, TiSi, PtSi, or NiPtSi.
The invention provides a preparation method of a low-operating-voltage semi-floating gate memory, which comprises the following specific steps of:
(1) providing a semiconductor substrate with a first doping type;
(2) forming a semi-floating gate well region with a second doping type in the upper region of the semiconductor substrate, and etching the semi-floating gate well region to form a U-shaped groove, so that the U-shaped groove penetrates through the semi-floating gate well region and the bottom of the U-shaped groove is positioned at the lower boundary of the semi-floating gate well region;
(3) forming a first grid electrode lamination, sequentially forming a first grid dielectric layer and a first metal grid, enabling the first grid dielectric layer to cover the surface of the U-shaped groove, and forming an opening in the semi-floating grid well region; the first metal gate covers the first gate dielectric layer and is in contact with the semi-floating gate well region at the opening;
(4) forming a second grid electrode lamination, and sequentially forming a second grid electrode dielectric layer and a second metal grid to enable the second grid electrode dielectric layer to comprise a second grid electrode dielectric layer and a second metal grid, wherein the second grid electrode dielectric layer covers the surface of the first metal grid and part of the surface of the semi-floating grid well region, the second metal grid covers the second grid electrode dielectric layer, and the second grid electrode dielectric layer and the second metal grid are both covered in the U-shaped groove;
(5) forming grid side walls on two sides of the first grid laminated layer and the second grid laminated layer;
(6) and forming a source electrode and a drain electrode on two sides of the first grid laminated layer and the second grid laminated layer in the semi-floating grid well region.
In the preparation method of the low-operating-voltage semi-floating gate memory, preferably, the first gate dielectric layer and the second gate dielectric layer are made of SiO 2 、Al 2 O 3 、ZrO 2 、HfZrO、HfO 2 One of HfAlO and HfSiO, or the combination of any of the above.
In the preparation method of the low-operating-voltage semi-floating gate memory, preferably, the first metal gate and the second metal gate are one of TiN, TaN, Ru and Co, or a combination of any of TiN, TaN, Ru and Co.
In the method for manufacturing the low-operating-voltage semi-floating gate memory, preferably, the thickness of the first metal gate is between 3nm and 5 nm.
In the method for manufacturing the low operating voltage semi-floating gate memory of the invention, preferably, the source electrode and the drain electrode are NiSi, CoSi, TiSi, PtSi or NiPtSi.
The second gate dielectric and the control gate are covered on the surface of the U-shaped groove, so that the area of the dielectric capacitor is greatly increased, and the capacitance value of the dielectric capacitor is greatly increased. Since the subthreshold swing is inversely proportional to the dielectric capacitance, the subthreshold swing is also greatly reduced. This means that the switching speed of the semi-floating gate transistor is greatly increased and thus the operating voltage can also be greatly reduced. In addition, the control gate is covered inside the U-shaped groove, so that the control capability of the control gate on the channel near the U-shaped groove is greatly increased. In addition, in the preparation process, the dielectric layer and the metal are deposited by adopting an atomic layer deposition method, the dielectric layer and the metal can have good conformality and step coverage rate on the surface of the U-shaped groove, and meanwhile, the uniformity of the film can be greatly improved.
Drawings
FIG. 1 is a flow chart of a method for manufacturing a low-operating-voltage semi-floating gate memory according to the present invention.
Fig. 2 is a schematic diagram of the device structure after oxide formation.
Fig. 3 is a schematic diagram of the device structure after forming the semi-floating gate well region.
Fig. 4 is a schematic diagram of the device structure after forming the U-shaped groove.
Fig. 5 is a schematic diagram of the device structure after oxide removal.
FIGS. 6-9 are schematic device structures of steps for forming a first gate stack.
FIGS. 10-12 are schematic device structures of steps for forming a second gate stack.
Fig. 13 is a schematic structural diagram of the device after forming the gate sidewall spacers.
Fig. 14 is a schematic diagram of the device structure of the semi-floating gate memory of the present invention.
Detailed Description
The invention will be further described with reference to the following examples and the accompanying drawings. It should be understood that the examples are only for explaining the present invention and are not intended to limit the present invention. All other embodiments obtained by a person skilled in the art without making any inventive step are within the scope of protection of the present invention.
FIG. 1 is a flow chart of a method for manufacturing a semi-floating gate memory. Fig. 2 to 14 are schematic structural diagrams illustrating steps of a method for manufacturing a low-operating-voltage semi-floating gate memory. As shown in fig. 1, in step S1, a semiconductor substrate 200 having a first doping type is provided. The semiconductor substrate 200 may be a suitable substrate in various forms, for example, a bulk semiconductor substrate such as Si, Ge, etc., and a compound semiconductor substrate such as SiGe, GaAs, GaSb, AlAs, InAs, InP, GaN, SiC, InGaAs, InSb, InGaSb, etc., a semiconductor-on-insulator Substrate (SOI), etc. For convenience of explanation, the following description will be made taking a Si substrate as an example. Then, a layer of oxide 202, typically SiO, is grown on the surface of the semiconductor substrate 200 2 Mainly to avoid defects caused by the direct ion bombardment of the semiconductor substrate itself, the resulting structure is shown in fig. 2.
In step S2, the semi-floating gate well 201 with the second doping type is formed. A well region 201 with the second doping type is formed in the surface layer region of the semiconductor substrate 200 by means of ion implantation, and the resulting structure is shown in fig. 3. In this embodiment, the first doping type is p-type, the second doping type is n-type, that is, the semiconductor substrate 200 is a p-type doped substrate, and an n-type lightly doped well 201 is formed in a surface region thereof.
And step S3, forming a U-shaped groove. Spin-coating photoresist, and defining the position of the U-shaped groove by photoetching processes such as exposure, development and the like. Patterning is performed by dry etching, such as ion milling etching, plasma etching, reactive ion etching, laser ablation, or wet etching using an etchant solution, so as to form a U-shaped trench in the semi-floating gate well region 201, the bottom of the U-shaped trench being in contact with the semiconductor substrate 200, and the resulting structure is shown in fig. 4. The oxide 202 is then removed by the same lithographic and etching methods as described above, and the resulting structure is shown in fig. 5.
In step S4, a first gate stack is formed. Specifically, the following steps are included, and the description is made with reference to fig. 6 to 9. Depositing SiO on the device structure by adopting an atomic layer deposition method 2 Layer 203 serves as a first gate dielectric layer and the resulting structure is shown in figure 6. And then spin-coating a photoresist, and defining the source end starting position of the tunneling transistor through photoetching processes such as exposure, development and the like. Removing portions of the SiO by dry etching, e.g. ion milling etching, plasma etching, reactive ion etching, laser ablation, or patterning by wet etching using an etchant solution 2 Layer 203 exposes a portion of the surface of the semi-floating gate well region 201 and the resulting structure is shown in fig. 7. A TiN layer 204 was then formed as a first metal gate on the above structure using an atomic layer deposition method, and the resulting structure was as shown in fig. 8. And then spin-coating a photoresist, and defining the shape of the first gate stack by photolithography processes such as exposure and development. Portions of the TiN layer 204 are removed by dry etching, such as ion mill etching, plasma etching, reactive ion etching, laser ablation, or patterning by wet etching using an etchant solution, and the resulting structure is shown in fig. 9. SiO is selected in the present embodiment 2 As a first gridAnd selecting TiN as the first metal gate material as the dielectric layer material. However, the present invention is not limited thereto, and the first gate dielectric layer may be selected from SiO 2 、Al 2 O 3 、ZrO 2 、HfZrO、HfO 2 HfAlO, HfSiO, and any combination thereof. The first metal gate layer is made of a suitable material for forming a metal gate, such as one selected from TiN, TaN, Ru, Co, and any combination thereof, and has a thickness of 3 to 5 nm.
In step S5, a second gate stack is formed. Specifically, the following steps are included, and the description is made with reference to fig. 10 to 13. Depositing Al on the device structure by adopting an atomic layer deposition method 2 O 3 Layer 205 serves as a second gate dielectric layer and the resulting structure is shown in figure 10. A TiN layer 206 is then formed as a second metal gate using an atomic layer deposition method, and the resulting structure is shown in fig. 11. The second gate dielectric layer and the second metal gate are covered in the U-shaped groove. Finally, a photoresist is spin coated on the second metal gate TiN layer 206 and patterned to define the shape of the second gate stack by a photolithography process including exposure and development thereof. One-side portion of Al is removed by dry etching, such as ion milling etching, plasma etching, reactive ion etching, laser ablation, or by wet etching using an etchant solution 2 O 3 Layer 205 and TiN layer 206, and removing SiO from the other side portion 2 Layer 203, TiN layer 204, Al 2 O 3 Layer 205 and TiN layer 206, the resulting structure is shown in fig. 12. Then, the photoresist is removed by dissolving or ashing in a solvent. In the present embodiment, Al is selected 2 O 3 And selecting TiN as a second metal gate material as a second gate dielectric layer material. However, the present invention is not limited thereto, and the second gate dielectric layer may be selected from SiO 2 、Al 2 O 3 、ZrO 2 、HfZrO、HfO 2 HfAlO, HfSiO, combinations of the above materials, or the like. The second metal gate layer may be selected from, for example, TiN, TaN, Ru, Co, or combinations thereof.
In step S6, a gate spacer is formed. Chemical vapor deposition method is adopted to deposit on the semi-floating gate well region, the first gate stack and the second gateGrowing SiO on the surface of the polar lamination 2 Layer 207, then removing portions of the SiO by photolithography and dry etching 2 Layer 207 to form sidewalls on both sides of the first gate stack and the second gate stack, the resulting structure being shown in fig. 13. Of course, the invention may also form the gate sidewall by other deposition processes, such as electron beam evaporation, atomic layer deposition, sputtering, etc., and the gate sidewall material may also be, for example, an insulating material such as SiN, etc.
In step S7, a source electrode and a drain electrode are formed. Spin-coating photoresist, and performing a photoetching process to define the shapes of the source electrode and the drain electrode. Depositing metal Ni by adopting a physical vapor deposition method, then removing photoresist, and finally forming NiSi compounds as a source electrode 208 and a drain electrode 209 by adopting a laser annealing method, wherein the obtained structure is shown in FIG. 14. In this embodiment, NiSi is selected as the source/drain electrode. However, the present invention is not limited thereto, and the source electrode or the drain electrode may be selected from NiSi, CoSi, TiSi, PtSi, NiPtSi, and the like.
As shown in fig. 14, the low operation voltage semi-floating gate memory of the present invention comprises a semiconductor substrate 200 having a first doping type; a semi-floating gate well region 201, which has a second doping type and is located in an upper region of the semiconductor substrate 200; the U-shaped groove penetrates through the semi-floating gate well region 201, and the bottom of the U-shaped groove is positioned at the lower boundary of the semi-floating gate well region 201; the first gate stack comprises a first gate dielectric layer 203 and a first metal gate 204, wherein the first gate dielectric layer 203 covers the surface of the U-shaped groove and forms an opening in the semi-floating gate well region 201; the first metal gate 204 covers the first gate dielectric layer 203 and is in contact with the semi-floating gate well region 201 at the opening; the second gate stack comprises a second gate dielectric layer 205 and a second metal gate 206, the second gate dielectric layer 205 covers the surface of the first metal gate 204 and part of the surface of the semi-floating gate well region 201, the second metal gate 206 covers the second gate dielectric layer 205, and the second gate dielectric layer 205 and the second metal gate 206 are both covered in the U-shaped groove; the gate side walls 207 are positioned on two sides of the first gate stack and the second gate stack; and a source electrode 208 and a drain electrode 209 formed in the semi-floating gate well 201 and located at two sides of the first gate stack and the second gate stack.
The first gate dielectric layer 203 and the second gate dielectric layer 205 are preferably SiO 2 、Al 2 O 3 、ZrO 2 、HfZrO、HfO 2 HfAlO, HfSiO, or the like, or any combination of the above. The first metal gate 204 and the second metal gate 206 are preferably TiN, TaN, Ru, Co, etc., or any combination thereof. The thickness of the first metal gate 204 is between 3nm and 5 nm. The source electrode 208 and the drain electrode 209 may be selected from NiSi, CoSi, TiSi, PtSi, NiPtSi, and the like.
The second gate dielectric and the second metal gate (i.e. the control gate) of the low-operating-voltage semi-floating gate memory are covered on the surface of the U-shaped groove, so that the area of the dielectric capacitor is greatly increased, and the capacitance value of the dielectric capacitor is greatly increased. Since the subthreshold swing is inversely proportional to the dielectric capacitance, the subthreshold swing is also greatly reduced. This means that the switching speed of the semi-floating gate transistor is greatly increased and thus the operating voltage can also be greatly reduced. In addition, the control gate is covered in the U-shaped groove, so that the control capability of the control gate on a channel near the U-shaped groove is greatly increased. In addition, in the preparation process, the dielectric layer and the metal are deposited by adopting an atomic layer deposition method, the dielectric layer and the metal can have good conformality and step coverage rate on the surface of the U-shaped groove, and meanwhile, the uniformity of the film can be greatly improved.
The above description is only for the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention.

Claims (10)

1. A low operating voltage semi-floating gate memory, comprising:
a semiconductor substrate (200) having a first doping type;
a semi-floating gate well region (201) having a second doping type and located in an upper region of the semiconductor substrate (200);
the U-shaped groove penetrates through the semi-floating gate well region (201), and the bottom of the U-shaped groove is positioned at the lower boundary of the semi-floating gate well region (201);
the first grid laminated layer comprises a first grid dielectric layer (203) and a first metal grid (204), wherein the first grid dielectric layer (203) covers the surface of the U-shaped groove and forms an opening in the semi-floating grid well region (201); the first metal gate (204) covers the first gate dielectric layer (203) and is in contact with the semi-floating gate well region (201) at the opening;
the second grid electrode stack comprises a second grid electrode dielectric layer (205) and a second metal grid (206), and the second grid electrode dielectric layer (205) covers the surface of the first metal grid (204) and part of the surface of the semi-floating grid well region (201); the second metal gate (206) covers the second gate dielectric layer (205), and the second gate dielectric layer (205) and the second metal gate (206) are covered in the U-shaped groove;
gate spacers (207) located on both sides of the first gate stack and the second gate stack;
and a source electrode (208) and a drain electrode (209) formed in the semi-floating gate well region (201) on both sides of the first gate stack and the second gate stack.
2. The low-operating-voltage semi-floating gate memory according to claim 1, wherein the first gate dielectric layer (203) and the second gate dielectric layer (205) are SiO 2 、Al 2 O 3 、ZrO 2 、HfZrO、HfO 2 One of HfAlO and HfSiO, or the combination of any of the above.
3. The low operating voltage half-floating gate memory of claim 1, wherein the first metal gate (204), the second metal gate (206) is one of TiN, TaN, Ru, Co, or a combination of any of them.
4. The low operating voltage semi-floating gate memory according to claim 1, wherein the thickness of the first metal gate (204) is between 3nm and 5 nm.
5. The low operating voltage semi-floating gate memory of claim 1, wherein the source electrode (208), the drain electrode (209) are NiSi, CoSi, TiSi, PtSi or NiPtSi.
6. A preparation method of a low-operation-voltage semi-floating gate memory is characterized by comprising the following specific steps:
providing a semiconductor substrate (200) having a first doping type;
forming a semi-floating gate well region (201) with a second doping type on an upper layer region of the semiconductor substrate (200);
etching the semi-floating gate well region (201) to form a U-shaped groove, wherein the U-shaped groove penetrates through the semi-floating gate well region (201), and the bottom of the U-shaped groove is positioned at the lower boundary of the semi-floating gate well region (201);
forming a first grid laminated layer, sequentially forming a first grid dielectric layer (203) and a first metal grid (204), enabling the first grid dielectric layer (203) to cover the surface of the U-shaped groove, and forming an opening in the semi-floating grid well region (201); the first metal gate (204) covers the first gate dielectric layer (203) and is in contact with the semi-floating gate well region (201) at the opening;
forming a second gate stack, and sequentially forming a second gate dielectric layer (205) and a second metal gate (206), so that the second gate dielectric layer comprises the second gate dielectric layer (205) and the second metal gate (206), the second gate dielectric layer (205) covers the surface of the first metal gate (204) and part of the surface of the semi-floating gate well region (201), the second metal gate (206) covers the second gate dielectric layer (205), and the second gate dielectric layer (205) and the second metal gate (206) are both covered inside the U-shaped groove;
forming gate side walls (207) on two sides of the first gate stack and the second gate stack;
and in the semi-floating gate well region (201), a source electrode (208) and a drain electrode (209) are formed on two sides of the first gate stack and the second gate stack.
7. The low operating voltage semi-floating gate memory of claim 6The preparation method is characterized in that the first gate dielectric layer (203) and the second gate dielectric layer (205) are SiO 2 、Al 2 O 3 、ZrO 2 、HfZrO、HfO 2 One of HfAlO and HfSiO, or the combination of any of the above.
8. The method for manufacturing a low-operating-voltage semi-floating gate memory according to claim 6, wherein the first metal gate (204) and the second metal gate (206) are one of TiN, TaN, Ru, Co, or a combination of any of them.
9. The method for manufacturing a low-operating-voltage semi-floating gate memory according to claim 6, wherein the thickness of the first metal gate (204) is between 3nm and 5 nm.
10. The method of claim 6, wherein the source electrode (208) and the drain electrode (209) are NiSi, CoSi, TiSi, PtSi or NiPtSi.
CN202010346656.4A 2020-04-27 2020-04-27 Low-operating-voltage semi-floating gate memory and preparation method thereof Active CN111508960B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202010346656.4A CN111508960B (en) 2020-04-27 2020-04-27 Low-operating-voltage semi-floating gate memory and preparation method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202010346656.4A CN111508960B (en) 2020-04-27 2020-04-27 Low-operating-voltage semi-floating gate memory and preparation method thereof

Publications (2)

Publication Number Publication Date
CN111508960A CN111508960A (en) 2020-08-07
CN111508960B true CN111508960B (en) 2022-09-16

Family

ID=71874899

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202010346656.4A Active CN111508960B (en) 2020-04-27 2020-04-27 Low-operating-voltage semi-floating gate memory and preparation method thereof

Country Status (1)

Country Link
CN (1) CN111508960B (en)

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9099490B2 (en) * 2012-09-28 2015-08-04 Intel Corporation Self-aligned structures and methods for asymmetric GaN transistors and enhancement mode operation
CN103579126B (en) * 2013-11-06 2016-05-11 复旦大学 A kind of half floating-gate device and manufacture method thereof of U-shaped structure
CN108447866B (en) * 2018-03-06 2019-03-26 武汉新芯集成电路制造有限公司 Floating-gate device and preparation method thereof
CN109742073A (en) * 2018-12-17 2019-05-10 复旦大学 A kind of half floating transistor and preparation method thereof with high charge holding capacity
CN109742074A (en) * 2018-12-17 2019-05-10 复旦大学 A kind of half floating transistor of high driving current and preparation method thereof
CN110416084A (en) * 2019-07-10 2019-11-05 复旦大学 A kind of half floating transistor and preparation method thereof of high K/ metal-gate structures
CN110416085A (en) * 2019-07-10 2019-11-05 复旦大学 A kind of half floating transistor of SiGe channel structure and preparation method thereof

Also Published As

Publication number Publication date
CN111508960A (en) 2020-08-07

Similar Documents

Publication Publication Date Title
KR101983894B1 (en) Semiconductor device and manufacturing method thereof
US10615078B2 (en) Method to recess cobalt for gate metal application
KR100642754B1 (en) Semiconductor device having etch resistant L shape spacer and fabrication method thereof
US20190013414A1 (en) Method of manufacturing a semiconductor device and a semiconductor device
CN109742073A (en) A kind of half floating transistor and preparation method thereof with high charge holding capacity
US20120261744A1 (en) Microelectronic device structure and manufacturing method thereof
CN109742159A (en) Half floating transistor of a kind of low tunnelling electric leakage and preparation method thereof
US8012816B2 (en) Double pass formation of a deep quantum well in enhancement mode III-V devices
CN111490046B (en) High-erasing-writing speed semi-floating gate memory and preparation method thereof
CN111477624B (en) Semi-floating gate memory based on longitudinal tunneling transistor and preparation method thereof
CN103426756A (en) Semiconductor component and manufacture method thereof
CN111540741B (en) Semi-floating gate memory based on floating gate and control gate connecting channel and preparation method thereof
CN111477627B (en) Semi-floating gate memory based on double-floating gate material and preparation method thereof
CN111477625B (en) Semi-floating gate memory based on defect trapping material and preparation method thereof
CN111508960B (en) Low-operating-voltage semi-floating gate memory and preparation method thereof
CN111508961A (en) High-tunneling-efficiency semi-floating gate memory and preparation method thereof
US11367778B2 (en) MOSFET device structure with air-gaps in spacer and methods for forming the same
CN111477626B (en) Semi-floating gate memory and preparation method thereof
CN111540739B (en) Semi-floating gate memory based on double tunneling transistors and preparation method thereof
CN103811315A (en) Semiconductor device and manufacturing method thereof
CN111540740B (en) Semi-floating gate memory based on pn junction and Schottky diode and preparation method thereof
CN111564443B (en) High-integration-density semi-floating gate memory and preparation method thereof
EP4195273A1 (en) Semiconductor structure and manufacturing method therefor
CN112909000B (en) Semi-floating gate memory and manufacturing process thereof
CN109979822B (en) Semiconductor device and method of forming the same

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant