CN100407424C - Complementary type metal-oxide-semiconductor transistor element and its making method - Google Patents
Complementary type metal-oxide-semiconductor transistor element and its making method Download PDFInfo
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- CN100407424C CN100407424C CN200510091053XA CN200510091053A CN100407424C CN 100407424 C CN100407424 C CN 100407424C CN 200510091053X A CN200510091053X A CN 200510091053XA CN 200510091053 A CN200510091053 A CN 200510091053A CN 100407424 C CN100407424 C CN 100407424C
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Abstract
The invention relates to a CMOS transistor, which comprises: the first transistor that comprises the first grid, the grid oxidant layer between the first grid and the semi-conductor substrate; the deflected side wall at the side wall of first grid; the first light doping drain/source poured into one side of deflected side wall; the first heavy doping drain/source poured beside the first light doping drain/source; and the first etching stopping layer with the first stress state; the second transistor which comprise the second grid, the grid oxidant layer between the second grid and the semi-conductor substrate; the nitride silicon side wall at the side wall of second grid; the second light doping drain/source poured under the nitride silicon side wall; the second heavy doping drain/source poured beside the second light doping drain/source; and the second etching stopping layer with the second stress state; the first etching stopping layer covers the second etching stopping layer.
Description
Technical field
The present invention relates to a kind of semiconductor technology, relate in particular to a kind of CMOS (Complementary Metal Oxide Semiconductor) (complementary metal-oxide-semiconductor, CMOS) field effect transistor element and preparation method thereof.Feature of the present invention makes N type metal oxide semiconductor field effect transistor element have higher saturated drain current (I in conjunction with the nitride etch stop with (compression or extension) under different stress (stress) effect
Dsat), improve the operation usefulness of semiconductor transistor component by this.
Background technology
See also Fig. 1 to Fig. 5, what it illustrated is that existing skill is made the transistorized generalized section of CMOS.At first, as shown in Figure 1, on Semiconductor substrate 10, be formed with N type trap 12, P type trap 14, and the shallow-channel insulation zone 16 that N type trap 12 and P type trap 14 are separated.
On N type trap 12 and P type trap 14, be formed with polysilicon gate 18 respectively, and the grid oxic horizon 20 between polysilicon gate 18 and Semiconductor substrate 10.Polysilicon gate 18 has vertical sidewall 18a and upper surface 18b.
As shown in Figure 2, then on the vertical sidewall 18a of polysilicon gate 18, form inclined to one side sidewall (offset spacer) 22, be generally dioxide sidewalls.And then utilize ion implantation technology 24 and ion implantation technology 28 respectively, in the Semiconductor substrate 10 of the both sides of polysilicon gate 18, form N type lightly doped drain/source electrode 26 and P type lightly doped drain/source electrode 30.
As shown in Figure 3, then on the vertical sidewall 18a of polysilicon gate 18, form silicon dioxide laying 31 and silicon nitride sidewall 32.And then utilize ion implantation technology 34 and ion implantation technology 38 respectively, in the Semiconductor substrate 10 of the both sides of polysilicon gate 18, form N type heavy doping drain/source 36 and P type heavy doping drain/source 40.
Then, as shown in Figure 4, carry out the metal silication reaction, on upper surface 18b, N type heavy doping drain/source 36 and the P type heavy doping drain/source 40 of polysilicon gate 18, form metal silicide layer 46.Then, deposit thickness is about the silicon nitride layer 50 of 300 to 600 dusts on Semiconductor substrate 10, the etching stopping layer when being used as the subsequent etch contact hole (contact etch stop layer).
At last, as shown in Figure 5, dielectric layer 54 on nitride etch stop 50, utilize existing photoetching and etch process then, form contact hole in dielectric layer 54 and nitride etch stop 50, and then form contact plunger 60 in contact hole.In etching contact hole process, nitride etch stop 50 provides this etched terminal point, alleviates the injury of etching composition for source electrode or drain electrode by this.
Summary of the invention
CMOS transistor unit that provides a kind of improvement and preparation method thereof is provided main purpose of the present invention, can make the CMOS transistor unit have preferable operation usefulness.
According to a preferred embodiment of the invention, the invention provides a kind of CMOS (Complementary Metal Oxide Semiconductor) (CMOS) transistor unit, comprising: semi-conductive substrate; One nmos pass transistor, include first grid, first grid oxide layer between this first grid and this Semiconductor substrate, be positioned at inclined to one side sidewall of silica on this first grid sidewall, inject the N type lightly doped drain/source region of this Semiconductor substrate of inclined to one side sidewall of this silica one side, inject the N type heavy doping drain/source zone of this other Semiconductor substrate of this N type lightly doped drain/source region, and have high first nitride etch stop of upholding (tensile) stress, be covered in this first grid, on this N type lightly doped drain/source region and this N type heavy doping drain/source zone; An and PMOS transistor, include second grid, second grid oxide layer between this second grid and this Semiconductor substrate, be positioned at silicon nitride sidewall on this second grid sidewall, inject the P type lightly doped drain/source region of this Semiconductor substrate under this silicon nitride sidewall, inject the P type heavy doping drain/source zone of this other Semiconductor substrate of this P type lightly doped drain/source region, and second nitride etch stop with high compression (compressive) stress, be covered in this second grid, on this silicon nitride sidewall and this P type heavy doping drain/source zone, and this first nitride etch stop covers on this second nitride etch stop.
The invention is characterized in conjunction with having different stress (stress) the effect nitride etch stop of (compression or extension) down, nitride etch stop at nmos pass transistor use stretching stress state makes the nmos pass transistor element have higher saturated drain current (I
Dsat), improve the operation usefulness of semiconductor transistor component by this.
In order to make those skilled in the art can further understand feature of the present invention and technology contents, see also following about detailed description of the present invention and accompanying drawing.Yet accompanying drawing is only for reference and aid illustration usefulness, is not to be used for the present invention is limited.
Description of drawings
What Fig. 1 to Fig. 5 illustrated is that existing skill is made the transistorized generalized section of CMOS;
What Fig. 6 to Figure 12 illustrated is the transistorized generalized section of making CMOS of the preferred embodiment of the present invention.
The main element symbol description
10 Semiconductor substrate 12N type traps
18 polysilicon gate 18a gate lateral walls
18b gate upper surface 20 grid oxic horizons
22 inclined to one side sidewall 24 ion implantation technologies
26N type lightly doped drain/source electrode 28 ion implantation technologies
30P type lightly doped drain/source electrode 31 silicon dioxide layings
32 silicon nitride sidewall, 34 ion implantation technologies
36N type heavy doping drain/source 38 ion implantation technologies
40P type heavy doping drain/source 46 metal silicide layers
50 silicon nitride layers, 54 dielectric layers
60 contact plungers
100 Semiconductor substrate 112N type traps
118 polysilicon gate 118a gate lateral walls
11gb gate upper surface 120 grid oxic horizons
122 inclined to one side sidewall 124 ion implantation technologies
126N type lightly doped drain/source electrode 128 ion implantation technologies
130P type lightly doped drain/source electrode
132 silicon nitride sidewall, 134 ion implantation technologies
136N type heavy doping drain/source 138 ion implantation technologies
140P type heavy doping drain/source 146 metal silicide layers
150 silicon nitride layers, 152 silicon nitride layers
154 dielectric layers, 160 contact plungers
172 photoresist layer 300NMOS transistors
The 400PMOS transistor
Embodiment
What Fig. 6 to Figure 12 illustrated is that the preferred embodiment of the present invention is made the transistorized generalized section of CMOS.At first, as shown in Figure 6, same N type trap 112, the P type trap 114 of on Semiconductor substrate 100, being formed with earlier, and the shallow-channel insulation zone 116 that N type trap 112 and P type trap 114 are separated.Semiconductor substrate 100 can be silicon substrate, silicon-coated insulated base material or the semiconductor substrate that includes epitaxial loayer.Aforesaid epitaxial loayer can be by the monocrystalline silicon extension or by the epitaxial loayer of SiGe strain.
On N type trap 112 and P type trap 114, be formed with polysilicon gate 118 respectively, and the grid oxic horizon 120 between polysilicon gate 118 and Semiconductor substrate 100.Polysilicon gate 118 has vertical sidewall 118a and upper surface 118b.
As shown in Figure 7, then on the vertical sidewall 118a of polysilicon gate 118, form inclined to one side sidewall 122 that thickness is about 20 to the 150 Izod right sides, it typically is dioxide sidewalls.And then utilize ion implantation technology 124 and ion implantation technology 128 respectively, in the Semiconductor substrate 100 of the both sides of polysilicon gate 118, form N type lightly doped drain/source electrode 126 and P type lightly doped drain/source electrode 130.
As shown in Figure 8, then on the vertical sidewall 118a of polysilicon gate 118, form silicon nitride sidewall 132, utilize ion implantation technology 134 and ion implantation technology 138 more respectively, in the Semiconductor substrate 100 of the both sides of polysilicon gate 118, form N type heavy doping drain/source 136 and P type heavy doping drain/source 140, form nmos pass transistor 300 and PMOS transistor 400.
As shown in Figure 9, carry out the metal silication reaction subsequently, on upper surface 118b, N type heavy doping drain/source 136 and the P type heavy doping drain/source 140 of polysilicon gate 118, form metal silicide layer 146.Then, deposit thickness is about 300 to 2000 dusts on Semiconductor substrate 100, preferably is about the silicon nitride layer 150 on 900 to the 1100 Izod right sides.
The invention is characterized in that silicon nitride layer 150 is painstakingly the stress of its silicon nitride layer 150 to be adjusted into compression (compressive) state in deposition process, the absolute value that preferably can make its stress value is greater than more than the 1Gpa, for example 1.3GPa.Form heavily stressed silicon nitride layer 150, can utilize plasma enhanced chemical vapor deposition (PECVD) method or carry out with other equivalent technology.
As shown in figure 10, cover PMOS transistor 400, expose the silicon nitride layer 150 on nmos pass transistor 300 and the nmos pass transistor 300 with photoresist layer 172.With etching mode silicon nitride sidewall 132 of silicon nitride layer on the nmos pass transistor 300 150 and nmos pass transistor 300 is removed simultaneously then.What deserves to be mentioned is that the preferred embodiment of the present invention is under silicon nitride sidewall 132 and but the silicon dioxide laying in the existing skill, therefore this moment, the N type lightly doped drain/source electrode 126 of nmos pass transistor 300 painstakingly is exposed.
As shown in figure 11, deposit thickness is about 300 to 2000 dusts on Semiconductor substrate 100 surfaces subsequently, preferably is about the silicon nitride layer 152 on 900 to the 1100 Izod right sides.Another feature of the present invention is that silicon nitride layer 152 is painstakingly the stress of its silicon nitride layer 152 to be adjusted into extension (tensile) state in deposition process, and the absolute value that preferably can make its stress value is greater than more than the 1Gpa, for example 1.3GPa.
Form the silicon nitride layer 152 of high stretching stress, can utilize plasma enhanced chemical vapor deposition (PECVD) method equally or carry out with other equivalent technology.The silicon nitride layer 152 of this high stretching stress is deposited on the N type lightly doped drain/source electrode 126 of nmos pass transistor 300, and covers on the silicon nitride layer 150 of PMOS transistor 400 high compression stress.
In addition, silicon nitride layer 152 is except as the follow-up contact etch stop layer, and the silicon nitride layer 152 of high stretching stress can make the silicon channel region of nmos pass transistor 300 produce strain, can significantly promote the operation usefulness of nmos pass transistor 300 by this.And for PMOS transistor 400,, therefore can not have influence on the operation usefulness of PMOS transistor 400 owing to have the silicon nitride layer 150 of high compression stress and the silicon nitride layer 152 of the high stretching stress of subsequent deposition to cry quites.
In addition, according to another embodiment of the present invention, the present invention can also utilize the contact etch stop layer of high compression stress to improve the transistorized operation usefulness of PMOS, for example, transform the transistor among Figure 11 300 into transistor into PMOS, be nmos pass transistor and transistor 400 transformed into, and silicon nitride layer 150 is transformed into to having the contact etch stop layer of high stretching stress, and silicon nitride layer 152 is transformed into to having the contact etch stop layer of high compression stress.
At last, as shown in figure 12, dielectric layer 154 on silicon nitride layer 152, for example Pyrex (BSG), boron-phosphorosilicate glass (BPSG), undoped silicon oxygen layer (undoped silicon glass, USG) or low-dielectric constant layer or the like, utilize existing photoetching and etch process then, in dielectric layer 154 and silicon nitride layer 152 and 150, form contact hole, and then in contact hole, form contact plunger 160.
In sum, the present invention includes following feature and advantage at least:
(1) the present invention is an operation usefulness of improving nmos pass transistor with the silicon nitride layer that height is upheld (tensile) stress, or in another embodiment, improves the transistorized operation usefulness of PMOS with the silicon nitride layer of high compression (compressive) stress.
(2) contact etch stop layer of the present invention on the drain/source zone of nmos pass transistor 300 is individual layer (silicon nitride layer 152 of high stretching stress), and the contact etch stop layer on the drain/source zone of PMOS transistor 400 is double-deck (silicon nitride layer 152 of high stretching stress adds the silicon nitride layer 150 of beneath high compression stress).
(3) silicon nitride sidewall 132 of nmos pass transistor 300 of the present invention is removed, and silicon nitride sidewall of PMOS transistor 400 then is retained.And, owing to have silicon nitride sidewall, the silicon nitride layer 150 of high compression stress can not touch the P type lightly doped drain/source electrode 130 of PMOS transistor 400.
The above only is the preferred embodiments of the present invention, and all equalizations of doing according to claim of the present invention change and modify, and all should belong to covering scope of the present invention.
Claims (19)
1. CMOS transistor unit comprises:
Semi-conductive substrate;
One nmos pass transistor, comprise first grid, first grid oxide layer between this first grid and this Semiconductor substrate, be positioned at inclined to one side sidewall of silica on this first grid sidewall, inject the N type lightly doped drain/source region of this Semiconductor substrate of inclined to one side sidewall of this silica one side, inject the N type heavy doping drain/source zone of this other Semiconductor substrate of this N type lightly doped drain/source region, and first nitride etch stop with high stretching stress, be covered in this first grid, on this N type lightly doped drain/source region and this N type heavy doping drain/source zone; And
One PMOS transistor, comprise second grid, second grid oxide layer between this second grid and this Semiconductor substrate, be positioned at silicon nitride sidewall on this second grid sidewall, inject the P type lightly doped drain/source region of this Semiconductor substrate under this silicon nitride sidewall, inject the P type heavy doping drain/source zone of this other Semiconductor substrate of this P type lightly doped drain/source region, and second nitride etch stop with high compression stress, be covered in this second grid, on this silicon nitride sidewall and this P type heavy doping drain/source zone.
2. CMOS transistor unit as claimed in claim 1, wherein this first nitride etch stop covers on this second nitride etch stop.
3. CMOS transistor unit as claimed in claim 1, wherein aforesaid first nitride etch stop with high stretching stress, the absolute value of its stress value is greater than 1Gpa.
4. CMOS transistor unit as claimed in claim 1, wherein aforesaid second nitride etch stop with high compression stress, the absolute value of its stress value is greater than 1Gpa.
5. CMOS transistor unit as claimed in claim 1, wherein the thickness of this first nitride etch stop is 900 to 1100 dusts.
6. CMOS transistor unit as claimed in claim 1, wherein the thickness of this second nitride etch stop is 900 to 1100 dusts.
7. CMOS transistor unit as claimed in claim 1 wherein also is formed with metal silicide layer on this N type heavy doping drain/source zone and this P type heavy doping drain/source zone.
8. CMOS transistor unit as claimed in claim 1, wherein this second nitride etch stop does not contact with transistorized this P type lightly doped drain/source region of this PMOS.
9. CMOS transistor unit comprises:
Semi-conductive substrate;
One the first transistor, comprise first grid, first grid oxide layer between this first grid and this Semiconductor substrate, be positioned at inclined to one side sidewall on this first grid sidewall, inject the first lightly doped drain/source region of this Semiconductor substrate of this inclined to one side sidewall one side, inject the first heavy doping drain/source zone of this other Semiconductor substrate of this first lightly doped drain/source region, and first etching stopping layer with first stress state, be covered in this first grid, on this first lightly doped drain/source region and this first heavy doping drain/source zone; And
One transistor seconds, comprise second grid, second grid oxide layer between this second grid and this Semiconductor substrate, be positioned at silicon nitride sidewall on this second grid sidewall, inject the second lightly doped drain/source region of this Semiconductor substrate under this silicon nitride sidewall, inject the second heavy doping drain/source zone of this other Semiconductor substrate of this second lightly doped drain/source region, and second etching stopping layer with second stress state, be covered in this second grid, on this silicon nitride sidewall and this second heavy doping drain/source zone.
10. CMOS transistor unit as claimed in claim 9, wherein this first etching stopping layer covers on this second etching stopping layer.
11. CMOS transistor unit as claimed in claim 9, wherein this first transistor is a nmos pass transistor, and this transistor seconds is the PMOS transistor.
12. CMOS transistor unit as claimed in claim 9, wherein this first etching stopping layer comprises silicon nitride, and this first stress state is the stretching stress state.
13. CMOS transistor unit as claimed in claim 9, wherein this second etching stopping layer comprises silicon nitride, and this second stress state is a compressing stress state.
14. CMOS transistor unit as claimed in claim 9, wherein the thickness of this first etching stopping layer is 900 to 1100 dusts.
15. CMOS transistor unit as claimed in claim 9, wherein the thickness of this second etching stopping layer is 900 to 1100 dusts.
16. CMOS transistor unit as claimed in claim 9, wherein this inclined to one side sidewall is a silica layer.
17. CMOS transistor unit as claimed in claim 9, wherein this first transistor is the PMOS transistor, and this transistor seconds is a nmos pass transistor.
18. CMOS transistor unit as claimed in claim 9, wherein this first etching stopping layer comprises silicon nitride, and this first stress state is a compressing stress state.
19. as claim 9 a described CMOS transistor unit, wherein this second etching stopping layer comprises silicon nitride, and this second stress state is the stretching stress state.
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| CN100407424C true CN100407424C (en) | 2008-07-30 |
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| CN102386134B (en) * | 2010-09-03 | 2013-12-11 | 中芯国际集成电路制造(上海)有限公司 | Method for making semiconductor device structure |
| CN102446854B (en) * | 2010-10-12 | 2014-06-04 | 中芯国际集成电路制造(北京)有限公司 | Manufacturing method for CMOS (Complementary Metal Oxide Semiconductor) transistor |
| CN102184895A (en) * | 2011-04-08 | 2011-09-14 | 上海先进半导体制造股份有限公司 | Side wall of high-voltage complementary metal-oxide-semiconductor transistor (CMOS) device and manufacturing method thereof |
| CN102420248A (en) * | 2011-04-20 | 2012-04-18 | 上海华力微电子有限公司 | Semiconductor device and method for improving electron mobility of transistor |
| TWI548039B (en) * | 2015-03-17 | 2016-09-01 | 力晶科技股份有限公司 | Method for fabricating semiconductor device |
| CN109545747B (en) * | 2017-09-22 | 2021-11-02 | 联华电子股份有限公司 | Semiconductor element and manufacturing method thereof |
| CN110021663B (en) * | 2018-01-09 | 2023-08-15 | 联华电子股份有限公司 | Semiconductor device with a semiconductor element having a plurality of electrodes |
| CN111933642A (en) * | 2020-09-18 | 2020-11-13 | 晶芯成(北京)科技有限公司 | Semiconductor device and manufacturing method thereof |
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| US6573172B1 (en) * | 2002-09-16 | 2003-06-03 | Advanced Micro Devices, Inc. | Methods for improving carrier mobility of PMOS and NMOS devices |
| US20040029323A1 (en) * | 2000-11-22 | 2004-02-12 | Akihiro Shimizu | Semiconductor device and method for fabricating the same |
| US20040104405A1 (en) * | 2002-12-02 | 2004-06-03 | Taiwan Semiconductor Manufacturing Company | Novel CMOS device |
| US20050093078A1 (en) * | 2003-10-30 | 2005-05-05 | Victor Chan | Increasing carrier mobility in NFET and PFET transistors on a common wafer |
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Patent Citations (4)
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| US20040029323A1 (en) * | 2000-11-22 | 2004-02-12 | Akihiro Shimizu | Semiconductor device and method for fabricating the same |
| US6573172B1 (en) * | 2002-09-16 | 2003-06-03 | Advanced Micro Devices, Inc. | Methods for improving carrier mobility of PMOS and NMOS devices |
| US20040104405A1 (en) * | 2002-12-02 | 2004-06-03 | Taiwan Semiconductor Manufacturing Company | Novel CMOS device |
| US20050093078A1 (en) * | 2003-10-30 | 2005-05-05 | Victor Chan | Increasing carrier mobility in NFET and PFET transistors on a common wafer |
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