CN101393894B - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereof Download PDFInfo
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- CN101393894B CN101393894B CN200710046315XA CN200710046315A CN101393894B CN 101393894 B CN101393894 B CN 101393894B CN 200710046315X A CN200710046315X A CN 200710046315XA CN 200710046315 A CN200710046315 A CN 200710046315A CN 101393894 B CN101393894 B CN 101393894B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 239000000758 substrate Substances 0.000 claims abstract description 30
- 239000000463 material Substances 0.000 claims description 41
- 238000000034 method Methods 0.000 claims description 33
- 238000005530 etching Methods 0.000 claims description 28
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 25
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 25
- 229920002120 photoresistant polymer Polymers 0.000 claims description 23
- 230000006835 compression Effects 0.000 claims description 16
- 238000007906 compression Methods 0.000 claims description 16
- 229910021332 silicide Inorganic materials 0.000 claims description 11
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 11
- 230000015572 biosynthetic process Effects 0.000 claims description 7
- 238000000151 deposition Methods 0.000 claims description 7
- 230000008021 deposition Effects 0.000 claims description 7
- 229910052751 metal Inorganic materials 0.000 claims description 7
- 239000002184 metal Substances 0.000 claims description 7
- 239000011248 coating agent Substances 0.000 claims description 5
- 238000000576 coating method Methods 0.000 claims description 5
- 229910017052 cobalt Inorganic materials 0.000 claims description 5
- 239000010941 cobalt Substances 0.000 claims description 5
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 5
- RUFLMLWJRZAWLJ-UHFFFAOYSA-N nickel silicide Chemical compound [Ni]=[Si]=[Ni] RUFLMLWJRZAWLJ-UHFFFAOYSA-N 0.000 claims description 5
- 229910021334 nickel silicide Inorganic materials 0.000 claims description 5
- 238000000059 patterning Methods 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 50
- 238000005516 engineering process Methods 0.000 description 13
- 230000008569 process Effects 0.000 description 11
- 238000000137 annealing Methods 0.000 description 9
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 8
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 6
- 108091006146 Channels Proteins 0.000 description 4
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 description 4
- 230000008901 benefit Effects 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 239000007789 gas Substances 0.000 description 4
- 239000012535 impurity Substances 0.000 description 4
- 239000003595 mist Substances 0.000 description 4
- 229910052757 nitrogen Inorganic materials 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 239000003795 chemical substances by application Substances 0.000 description 3
- 238000009826 distribution Methods 0.000 description 3
- 239000001307 helium Substances 0.000 description 3
- 229910052734 helium Inorganic materials 0.000 description 3
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 230000009467 reduction Effects 0.000 description 3
- 230000001105 regulatory effect Effects 0.000 description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 239000002800 charge carrier Substances 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 229910000449 hafnium oxide Inorganic materials 0.000 description 2
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 2
- 229910052736 halogen Inorganic materials 0.000 description 2
- 150000002367 halogens Chemical class 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum(3+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000004528 spin coating Methods 0.000 description 2
- IATRAKWUXMZMIY-UHFFFAOYSA-N strontium oxide Chemical compound [O-2].[Sr+2] IATRAKWUXMZMIY-UHFFFAOYSA-N 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 229910052715 tantalum Inorganic materials 0.000 description 2
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 238000001947 vapour-phase growth Methods 0.000 description 2
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 108010075750 P-Type Calcium Channels Proteins 0.000 description 1
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 1
- WUNIMIODOAGQAW-UHFFFAOYSA-N [O-2].[Ba+2].[Ti+4] Chemical compound [O-2].[Ba+2].[Ti+4] WUNIMIODOAGQAW-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- ILCYGSITMBHYNK-UHFFFAOYSA-N [Si]=O.[Hf] Chemical compound [Si]=O.[Hf] ILCYGSITMBHYNK-UHFFFAOYSA-N 0.000 description 1
- JIMUOUDLWPNFAY-UHFFFAOYSA-N [Si]=O.[Hf].[N] Chemical compound [Si]=O.[Hf].[N] JIMUOUDLWPNFAY-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000000460 chlorine Substances 0.000 description 1
- 229910052801 chlorine Inorganic materials 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 238000002310 reflectometry Methods 0.000 description 1
- 229910052707 ruthenium Inorganic materials 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- CZXRMHUWVGPWRM-UHFFFAOYSA-N strontium;barium(2+);oxygen(2-);titanium(4+) Chemical compound [O-2].[O-2].[O-2].[O-2].[Ti+4].[Sr+2].[Ba+2] CZXRMHUWVGPWRM-UHFFFAOYSA-N 0.000 description 1
- SFZCNBIFKDRMGX-UHFFFAOYSA-N sulfur hexafluoride Chemical compound FS(F)(F)(F)(F)F SFZCNBIFKDRMGX-UHFFFAOYSA-N 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
- 229910001936 tantalum oxide Inorganic materials 0.000 description 1
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 description 1
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 1
- 229910021341 titanium silicide Inorganic materials 0.000 description 1
- GFQYVLUOOAAOGM-UHFFFAOYSA-N zirconium(iv) silicate Chemical compound [Zr+4].[O-][Si]([O-])([O-])[O-] GFQYVLUOOAAOGM-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7843—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being an applied insulating layer
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The invention discloses a semiconductor device which comprises an NMOS transistor and a PMOS transistor formed on a substrate; and grid electrodes, source cathode doped areas, drain doped areas, and side walls formed on two sides of the grid electrodes are arranged on the NMOS transistor and the PMOS transistor respectively. The device is characterized in that the side walls on the two sides of the grid electrode of the NMOS transistor possess tensile stress, and the side walls on the two sides of the grid electrode of the PMOS transistor possess compressive stress. The stress gives the side walls a greater role in adjusting the stress applied to channels and the source/drain areas, with the carrier mobility further enhanced and the performance of the device improved.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly a kind of complementary mos device (CMOS) and manufacture method thereof.
Background technology
In semiconductor fabrication, known form on the doped region stressor layers can below contain on the layer of impurity or the substrate and produce mechanical stress, such stress can increase the energy of impurity.Impurity or electric charge carrier that energy increases can make semiconductor device that higher running speed is arranged.Between more than ten years in the past, utilize the mode of reduction mos field effect transistor (MOSFET) size, so as to the component density and the cost of the service speed of each function element of improving integrated circuit constantly, usefulness performance, circuit.The method of reduction mainly comprises the thickness of reduction of gate length and grid oxic horizon.Along with device feature size enters the deep sub-micron technique node, in order further to promote the usefulness of semiconductor device, utilize the stress rete, be arranged in Semiconductor substrate formation strained channel zone, for the MOS transistor of N type or the MOS transistor of P type, use the strained channel zone can improve the mobility of charge carrier rate, improve the performance of element.
Application number is to disclose a kind of mos field effect transistor with compartmentalization stress structure in 200510093507.7 the Chinese patent application, it is on the direction of source electrode-drain electrode, form the stressor layers of tensile stress (Tensile Strain) in the N of NMOS type channel surface, to increase the mobility of electronics, and at the PMOS transistor on the direction of source electrode-drain electrode, in the stressor layers of P type channel surface formation compression (Compressive Strain), to improve the mobility in hole.
The stress rete is applied to the MOS device with in the situation that improves device performance, normally in the source, drain electrode and gate lateral wall surface forms the stress rete, this stress rete covers source, the drain and gate sidewall surfaces is used to regulate transverse compression or tensile stress along channel direction.Promptly can form stressor layers at substrate surface earlier the opportunity that forms the stress rete before source-drain electrode mixes, substrate is applied suitable stress, makes substrate have the stress distribution of expectation; Also can be after source-drain electrode mix, at substrate surface deposition stress rete, to regulate the stress distribution between raceway groove and the source-drain area, on the other hand as the etching stop layer of follow-up formation connecting hole., how further to utilize stress engineering that device performance is improved and remain the vital task that engineers faces constantly for 65nm even the semiconductor device processing technology that strides forward below the 45nm for technology node.
Summary of the invention
The object of the present invention is to provide a kind of semiconductor device and manufacture method thereof, can further improve the stress distribution density of complementary mos device, improve device performance.
A kind of manufacture method of semiconductor device is provided, has comprised:
Provide to have NMOS and the transistorized Semiconductor substrate of PMOS, described NMOS and PMOS device have grid, source/drain doping region respectively;
At described substrate surface deposition tension stress material layer, described tension stress layer of material covers NMOS and PMOS transistor;
Form first mask pattern, described mask pattern covers the tension stress material layer on nmos pass transistor surface and exposes the tension stress material layer on PMOS transistor surface;
See through the tension stress material layer on the described PMOS transistor of described first mask pattern etching surface, to remove the tension stress material layer on described PMOS transistor surface;
Remove described first mask pattern;
Form second mask pattern, described mask pattern covers the PMOS transistor and exposes the tension stress material layer on nmos pass transistor surface;
See through the tension stress material layer on the described nmos pass transistor of described second mask pattern etching surface, thereby form the tension stress side wall in the grid both sides of nmos pass transistor;
Remove described second mask pattern;
Have compression material layer, described compression layer of material covers NMOS and PMOS transistor in described substrate surface deposition;
The described compression material layer of etching, thereby at the transistorized grid of PMOS both sides formation compression side wall.
Further, described method also is included in the step that described grid, source electrode and drain doping region surface form metal silicide.
Further, the material of described tension stress material layer is a silicon nitride.
Further, the material of described compression material layer is a silicon nitride.
Further, the step that forms described mask pattern comprises: coating photoresist layer and the described photoresist figure of patterning.
Further, described photoresist is positive photoresist or negative photoresist.
Further, described metal silicide is the combination of nickel silicide or cobalt silicide or nickel silicide and cobalt silicide.
Compared with prior art, the present invention has the following advantages:
Semiconductor device of the present invention and manufacture method thereof after foreign ion doping and annealing are finished in the zone of source, drain electrode, form the side wall (spacer) with stress in the grid both sides.Promptly form the side wall of forming by stress silicon nitride with tensile stress in the grid both sides of nmos pass transistor, and form the side wall of forming by stress silicon nitride in the transistorized grid of PMOS both sides, and then in substrate surface formation stress silicon nitride rete with compression.Form side wall with stress in the grid both sides, because side wall is than the raceway groove of the close more grid of the stress rete below of source/drain surface, therefore the side wall that has stress with follow-up in the substrate source/stress film that drain surface forms compares, and is more remarkable and direct to the stress regulating action of raceway groove and source/drain region.After source/drain surface formed the stress rete, the acting in conjunction of the side wall that this stress rete and grid both sides are made up of stress material can further improve the stress regulating action, and the raising carrier mobility is improved the operating characteristics of device.
Description of drawings
By the more specifically explanation of the preferred embodiments of the present invention shown in the accompanying drawing, above-mentioned and other purpose, feature and advantage of the present invention will be more clear.Reference numeral identical in whole accompanying drawings is indicated identical part.Painstakingly do not draw accompanying drawing in proportion, focus on illustrating purport of the present invention.In the accompanying drawings, for cheer and bright, amplified the thickness in layer and zone.
Fig. 1 to Fig. 7 is the schematic diagram according to the stressor layers forming process of the cmos device of the embodiment of the invention.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, the specific embodiment of the present invention is described in detail below in conjunction with accompanying drawing.
Semiconductor device of the present invention and the side wall stress rete formation method that manufacture method provided thereof relate to PMOS transistor and the nmos pass transistor in the cmos device.For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, preferred embodiment of the present invention is described in detail below in conjunction with accompanying drawing.A lot of details have been set forth in the following description so that fully understand the present invention.But the present invention can implement much to be different from alternate manner described here, and those skilled in the art can do similar popularization under the situation of intension of the present invention.Therefore the present invention is not subjected to the restriction of following public concrete enforcement.
Fig. 1 to Fig. 7 is the schematic diagram according to the stressor layers forming process of the cmos device of the embodiment of the invention.At first as shown in Figure 1, in Semiconductor substrate 100, be formed with N trap (N Well) and P trap (P Well), in N trap and P trap, form PMOS transistor and nmos pass transistor respectively, utilize fleet plough groove isolation structure to isolate between above-mentioned PMOS transistor and the nmos pass transistor.PMOS transistor and nmos pass transistor constitute cmos device by the interlayer connection line.Semiconductor substrate 100 can be the silicon materials that comprise semiconductor element, and for example the silicon of monocrystalline, polycrystalline or non crystalline structure or SiGe (SiGe) also can be silicon-on-insulators (SOI).In addition, Semiconductor substrate can also comprise other material, for example the sandwich construction of epitaxial loayer or buried layer.Though in these several examples of having described the material that can form substrate 110, any material that can be used as Semiconductor substrate all falls into the spirit and scope of the present invention.
At Semiconductor substrate 100 surface deposition grid oxic horizons, grid oxic horizon can be silica (SiO2) or silicon oxynitride (SiNO).At the following process node of 65nm, the material of grid oxic horizon is preferably high-k (high k) material.Can be used as the material that forms the high dielectric constant grid dielectric layer and comprise hafnium oxide, hafnium silicon oxide, nitrogen hafnium silicon oxide, lanthana, zirconia, zirconium silicon oxide, titanium oxide, tantalum oxide, strontium barium oxide titanium, barium monoxide titanium, strontium oxide strontia titanium, aluminium oxide etc.Particularly preferably be hafnium oxide, zirconia and aluminium oxide.Though in this a few examples of having described the material that can be used for forming grid oxic horizon, this layer can be formed by other material that reduces grid leakage current.At grid oxic horizon surface deposition polysilicon layer, utilize the photoresist figure as the above-mentioned polysilicon layer of mask etching, form the grid 140 and the transistorized grid 160 of PMOS of nmos pass transistor.Grid 140 and 160 material except that polysilicon, can also be polycrystalline silicon germanium, metal silicide (for example Titanium silicide, cobalt silicide, nickel silicide, tantalum silicide etc.), conducting metal oxide, conductive metal nitride (for example titanizing nitrogen, tantalum nitrogen), metal (for example tantalum, titanium, molybdenum, tungsten, platinum, aluminium, hafnium, ruthenium etc.) or its combination.
In the substrate of the grid 140 of nmos pass transistor and the transistorized grid of PMOS 160 both sides, form nmos pass transistor and transistorized source electrode of PMOS and drain electrode by ion implantation technology impurity ion.After technology in, in substrate surface deposited silicon nitride layer 120.This silicon nitride layer 120 covers source electrode, drain electrode and gate surface and gate lateral wall.The method of deposited silicon nitride layer 120 can adopt chemical vapor deposition (CVD) technology, low-pressure chemical vapor phase deposition (LPCVD) technology or ald (ALD) technology etc.After deposited silicon nitride layer 120, it is carried out annealing in process.Can use various method for annealing, for example use Halogen lamp LED or tungsten lamp, the temperature of annealing is 900～1000 ℃, and the silicon nitride layer 120 after the annealing is stressor layers that a kind of edge laterally has tensile stress.
Then, as shown in Figure 2, silicon nitride layer 120 surfaces on substrate utilize spin coating (spin on) technology coating photoresist layer.Before coating, can form bottom anti-reflection layer (BARC, not shown) earlier, the reflectivity when exposing to reduce.Utilize the above-mentioned photoresist layers of art pattern CADization such as conventional photoetching process is exposed, development, cleaning, form photoresist mask pattern 180.This photoresist figure 180 covers the silicon nitride layer 120 on nmos pass transistor surfaces and exposes the silicon nitride layer 120 on PMOS transistor surface.
Subsequently as shown in Figure 3, with photoresist figure 180 be the silicon nitride layer 120 on the PMOS transistor surface of mask etching exposure.Adopt dry etching, for example plasma etching industrial.In the etching process in reative cell the using plasma etching technics carry out etching.During etching, the directivity of etching realizes by the bias power and negative electrode (substrate just) substrate bias power of control plasma source.Feed etchant gas flow 50-400sccm in the present embodiment in the reative cell, underlayer temperature is controlled between 20 ℃ and 90 ℃, and chamber pressure is 4-80mTorr, plasma source power output 50W-2000W.Etching gas adopts mist, comprises the mist as SF6, CHF3, CF4, chlorine C12, nitrogen N 2, helium He and oxygen O2.This etching agent has very high etching selection for the stressor layers silicon nitride material.
After etching is finished, adopt wet-cleaned or cineration technics to remove photoresist figure 180.Utilize spin coating (spin on) technology coating photoresist layer in substrate surface again, utilize the above-mentioned photoresist layers of art pattern CADization such as exposure, development, cleaning, form photoresist mask pattern 190.This photoresist figure 190 covers PMOS transistors and exposes the silicon nitride layer 120 on nmos pass transistor surface, as shown in Figure 4.
Next as shown in Figure 5, above-mentioned photoresist figure 190 pair pmos transistors have played protective effect.Utilize the plasma etching industrial etching to cover the silicon nitride layer 120 of nmos pass transistor.The directivity of etching can realize by the bias power and the cathode bias power of control plasma source in etching process.Feed etchant gas flow 220sccm in the present embodiment in the reative cell, underlayer temperature is controlled at 50 ℃, and chamber pressure is 60mTorr, plasma source power output 1000W.Etching agent adopts the mist of CHF3, nitrogen N 2, helium He and oxygen O2.Obtain having the side wall 200 of tensile stress after the etching in grid 140 both sides.
In ensuing processing step, as shown in Figure 6, adopt wet-cleaned or cineration technics to remove photoresist figure 190.Then utilize chemical vapor deposition (CVD) technology or low-pressure chemical vapor phase deposition (LPCVD) technology at another silicon nitride layer 150 of substrate surface deposit, carry out annealing in process then, the temperature of annealing can be used various method for annealing between 600～800 ℃, for example use the heating of Halogen lamp LED or tungsten lamp.Silicon nitride layer 150 after the annealing is along laterally having compression.
Subsequently, utilize the above-mentioned silicon nitride layer 150 of plasma etching industrial etching.Process conditions in etching process adopt the process conditions identical with the silicon nitride layer 120 of covering nmos pass transistor among etching Fig. 4.The directivity of etching can realize by the bias power and the cathode bias power of control plasma source.Feed etchant gas flow 220sccm in the present embodiment in the reative cell, underlayer temperature is controlled at 50 ℃, and chamber pressure is 60mTorr, plasma source power output 1000W.Etching agent adopts the mist of CHF3, nitrogen N 2, helium He and oxygen O2.Just obtain having the side wall 220 of compression like this after the etching in grid 160 both sides, as shown in Figure 7.
Cmos device of the present invention comprises substrate 100 as shown in Figure 7, and the N trap and the P trap that form in substrate 100, the nmos pass transistor that forms in the P trap, described nmos pass transistor comprise grid 140, source electrode and drain electrode and at the side wall 200 of grid 140 both sides; The PMOS transistor that forms in the N trap, described PMOS transistor comprise grid 160, source electrode and drain electrode and at the side wall 220 of grid 160 both sides; The silicon nitride of wherein said side wall 200 for having tension stress, the silicon nitride of described side wall 220 for having compression.Because side wall 200 is more near the raceway groove of grid 140 belows, side wall 220 is also more near the raceway groove of grid 160 belows, therefore has the side wall 200 of stress and the 220 pairs of raceway grooves and source/drain region and has significant more stress regulating action.After follow-up source/drain surface formed the stress rete, the acting in conjunction of this stress rete and grid both sides side wall can further improve carrier mobility, improves device performance.
The above only is preferred embodiment of the present invention, is not the present invention is done any pro forma restriction.Though the present invention discloses as above with preferred embodiment, yet be not in order to limit the present invention.Any those of ordinary skill in the art, do not breaking away under the technical solution of the present invention scope situation, all can utilize the method and the technology contents of above-mentioned announcement that technical solution of the present invention is made many possible changes and modification, or be revised as the equivalent embodiment of equivalent variations.Therefore, every content that does not break away from technical solution of the present invention, all still belongs in the scope of technical solution of the present invention protection any simple modification, equivalent variations and modification that above embodiment did according to technical spirit of the present invention.
Claims (7)
1. the manufacture method of a semiconductor device comprises:
Provide to have NMOS and the transistorized Semiconductor substrate of PMOS, described NMOS and PMOS device have grid, source/drain doping region respectively;
At described substrate surface deposition tension stress material layer, described tension stress layer of material covers NMOS and PMOS transistor;
Form first mask pattern, described mask pattern covers the tension stress material layer on nmos pass transistor surface and exposes the tension stress material layer on PMOS transistor surface;
See through the tension stress material layer on the described PMOS transistor of described first mask pattern etching surface, to remove the tension stress material layer on described PMOS transistor surface;
Remove described first mask pattern;
Form second mask pattern, described mask pattern covers the PMOS transistor and exposes the tension stress material layer on nmos pass transistor surface;
See through the tension stress material layer on the described nmos pass transistor of described second mask pattern etching surface, thereby form the tension stress side wall in the grid both sides of nmos pass transistor;
Remove described second mask pattern;
Have compression material layer, described compression layer of material covers NMOS and PMOS transistor in described substrate surface deposition;
The described compression material layer of etching, thereby at the transistorized grid of PMOS both sides formation compression side wall.
2. the method for claim 1 is characterized in that: described method also is included in the step that described grid, source electrode and drain doping region surface form metal silicide.
3. the method for claim 1, it is characterized in that: the material of described tension stress material layer is a silicon nitride.
4. the method for claim 1, it is characterized in that: the material of described compression material layer is a silicon nitride.
5. the method for claim 1, it is characterized in that: the step that forms described mask pattern comprises: coating photoresist layer and the described photoresist figure of patterning.
6. method as claimed in claim 5 is characterized in that: described photoresist is positive photoresist or negative photoresist.
7. method as claimed in claim 2 is characterized in that: described metal silicide is the combination of nickel silicide or cobalt silicide or nickel silicide and cobalt silicide.
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| Application Number | Priority Date | Filing Date | Title |
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| CN200710046315XA CN101393894B (en) | 2007-09-20 | 2007-09-20 | Semiconductor device and manufacturing method thereof |
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| CN200710046315XA CN101393894B (en) | 2007-09-20 | 2007-09-20 | Semiconductor device and manufacturing method thereof |
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| Publication Number | Publication Date |
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| CN101393894A CN101393894A (en) | 2009-03-25 |
| CN101393894B true CN101393894B (en) | 2011-08-17 |
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Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101958249B (en) * | 2009-07-16 | 2012-05-16 | 中芯国际集成电路制造(上海)有限公司 | Method for improving current carrier migration rate of MOS transistor |
| CN102064176B (en) * | 2009-11-11 | 2013-03-20 | 中国科学院微电子研究所 | Semiconductor device and manufacturing method thereof |
| CN102110647B (en) * | 2009-12-23 | 2013-09-18 | 中芯国际集成电路制造(上海)有限公司 | Optimized etching method of stress memorization technology |
| CN102386134B (en) * | 2010-09-03 | 2013-12-11 | 中芯国际集成电路制造(上海)有限公司 | Method for making semiconductor device structure |
| CN102420138A (en) * | 2010-09-25 | 2012-04-18 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of transistor |
| CN102569394B (en) | 2010-12-29 | 2014-12-03 | 中芯国际集成电路制造(北京)有限公司 | Transistor and manufacture method thereof |
| CN102543744B (en) | 2010-12-29 | 2014-12-24 | 中芯国际集成电路制造(北京)有限公司 | Transistor and manufacturing method thereof |
| CN102646591B (en) | 2011-02-22 | 2015-09-02 | 中芯国际集成电路制造(上海)有限公司 | The manufacture method of transistor |
| CN102651345B (en) | 2011-02-24 | 2014-01-08 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of transistor |
| CN103178011A (en) * | 2011-12-22 | 2013-06-26 | 中芯国际集成电路制造(上海)有限公司 | Complementary metal oxide semiconductor (CMOS) and forming method thereof |
| CN115440666B (en) * | 2022-11-10 | 2023-01-24 | 广州粤芯半导体技术有限公司 | Method for manufacturing CMOS device with dual stress liner structure |
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