CN100499079C - CMOS device stress membrane forming method - Google Patents
CMOS device stress membrane forming method Download PDFInfo
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- CN100499079C CN100499079C CNB2006101188297A CN200610118829A CN100499079C CN 100499079 C CN100499079 C CN 100499079C CN B2006101188297 A CNB2006101188297 A CN B2006101188297A CN 200610118829 A CN200610118829 A CN 200610118829A CN 100499079 C CN100499079 C CN 100499079C
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- stress film
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Abstract
The invention discloses a method for forming a stress membrane of a CMOS device. The CMOS device includes a PMOS transistor and a NMOS transistor. The method includes the following steps: a first stress membrane is formed, which covers the PMOS transistor and the NMOS transistor; a dielectric layer is formed on the surface of the first stress membrane between the PMOS transistor and the NMOS transistor; a first mask graph only covering the NMOS transistor is formed; the first stress membrane and a medium layer on the PMOS transistor are etched and the first mask graph is removed; a second stress membrane material is deposited, the surface of which is flush with the surface of the first stress membrane material; the second mask graph is formed; the surface of the second stress membrane is etched until being flush with the surface of the first stress membrane material; and the second mask graph and the rest dielectric layer are removed. The invention can remove salient on the stress membrane conjunction part of the NMOS transistor and the PMOS transistor.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly a kind of method that forms the cmos device stress film.
Background technology
In semi-conductor industry, knownly produce mechanical stress forming on the doped region on film that stress film can be by containing impurity down below or the substrate, increase the related semiconductor component speeds.Such stress has been promoted the energy of impurity.Doping or electric charge carrier that energy increases can make semiconductor element, and for example transistor has higher running speed, and therefore the applied stress film is helpful in the various suitable application.
Between more than ten years in the past, utilize reduction mos field effect transistor (Metal-oxide-semiconductor Field-effect Transistors, MOSFET) mode of size, so as to the component density and the cost of the service speed of each function element of improving integrated circuit constantly, usefulness performance, circuit, the method for reduction mainly comprises the thickness of reduction of gate length and grid oxic horizon.Make the MOSFET element in order further to promote transistorized usefulness, utilize the strained channel zone that is arranged in the Semiconductor substrate some.For complementary metal oxide semiconductor field effect transistor (CMOS), with the MOSFET of n type or the MOSFET of p type, use the strained channel zone can improve the mobility of charge carrier rate, to increase the usefulness of element.Application number is to disclose a kind of mos field effect transistor with compartmentalization stress structure in 200510093507.7 the Chinese patent application, it is on the direction of source electrode one drain electrode, in the n of NMOSFET type passage, form the stress film of elongation strain (TensileStrain), can increase the mobility of electronics, and on the direction of source electrode one drain electrode, in the p of PMOSFET type passage, form the stress film of compression strain (Compressive Strain), can increase the mobility in hole.Fig. 1 is the stress film position view of cmos device.As shown in Figure 1, on nmos pass transistor 116, form the stress film 110 of elongation strain (Tensile Strain), can increase the mobility of electronics, and on PMOS transistor 117, form the stress film 120 of compression strain (Compressive Strain), can increase the mobility in hole.But the contact site 118 in stress film 110 and 120 protruding phenomenon occurs through regular meeting, and Fig. 2 to Fig. 5 is this schematic diagram that convexes to form process of explanation.In the process that forms stress film, form wherein one deck earlier, for example on PMOS transistor 117 and stress film 110, deposit another ply stress film 120 then at the stress film 110 that forms elongation strain (TensileStrain) on the nmos pass transistor 116 earlier, as shown in Figure 2; On the stress film 120 that covers PMOS transistor 117, form photoresist figure 112 again, as shown in Figure 3; Utilize photoresist figure 112 to fall to cover stress film on the nmos pass transistor 116 subsequently, as shown in Figure 4 for mask etching; Because during deposition stress film 120, this stress film also covers the stress film 110 of previous formation, therefore after removing photoresist figure 112, can stay projection 113 in the junction of stress film 110 and 120, influence the carrying out of subsequent technique.
Summary of the invention
The invention provides a kind of method that forms the cmos device stress film, can eliminate the projection of the transistorized stress film of nmos pass transistor and PMOS junction.
A kind of method that forms the cmos device stress film provided by the invention, described cmos device comprises PMOS transistor and nmos pass transistor, described method comprises the following steps:
Form first stress film, described first stress film covers described nmos pass transistor and PMOS transistor; First stress film surface between described PMOS transistor and nmos pass transistor forms dielectric layer; Form first mask pattern that only covers described nmos pass transistor; First stress film and dielectric layer on the described PMOS transistor of etching, and remove described first mask pattern; Deposit the second stress film material, described second stress film material surface and the described first stress film flush; Form second mask pattern; The described second stress film material of etching to the described first stress film flush; Remove described second mask pattern and remaining dielectric layer.
Described second mask pattern covers first stress film on the described nmos pass transistor and the second stress film material surface on the described PMOS transistor.
Described first stress film is identical with the width of second mask pattern of the described second stress film material surface.Described first mask pattern only covers first stress film and the dielectric layer surface on the described nmos pass transistor.The material of described first stress film and second stress film is a silicon nitride.The material of described dielectric layer is the Silicon-rich polymer.Described first stress film is the stress film with tensile stress, and described second stress film is the stress film with compression stress.
Have the method for the another kind formation cmos device stress film of identical or relevant art feature with the present invention, described cmos device comprises PMOS transistor and nmos pass transistor.Described method comprises the following steps:
Form first stress film, described first stress film covers described nmos pass transistor and PMOS transistor; First stress film surface between described PMOS transistor and nmos pass transistor forms dielectric layer; Form and only cover transistorized first mask pattern of described PMOS; First stress film and dielectric layer on the described nmos pass transistor of etching, and remove described first mask pattern; Deposit the second stress film material, described second stress film material surface and the described first stress film flush; Form second mask pattern; The described second stress film material of etching is to flushing with described first stress film; Remove described second mask pattern and remaining dielectric layer.
Described second mask pattern covers first stress film on the described PMOS transistor and the second stress film material surface on the described nmos pass transistor.
Described first stress film is identical with the width of second mask pattern of the described second stress film material surface.Described first mask pattern only covers first stress film and the dielectric layer surface on the described PMOS transistor.Described first stress film is the stress film with compression stress, and described second stress film is the stress film with tensile stress.The material of described dielectric layer is the Silicon-rich polymer.The material of described first stress film and second stress film is a silicon nitride.
Compared with prior art, the present invention has the following advantages:
Cmos device stress film formation method of the present invention has adopted the technology of twice mask, promptly at first forms and covers nmos pass transistor and transistorized first stress film of PMOS; First stress film surface between described PMOS transistor and nmos pass transistor forms the BARC layer; Form first mask pattern that only covers described nmos pass transistor then; First stress film and dielectric layer on the described PMOS transistor of etching, and remove described first mask pattern; Then deposit the second stress film material, described second stress film material surface and the described first stress film flush; Form second mask pattern subsequently; With second mask pattern be the described second stress film material of mask etching to the described first stress film flush; And remove described second mask pattern and remaining dielectric layer.Adopt the method for twice mask etching of the present invention to eliminate protruding phenomenon in the junction of the stress film of nmos pass transistor 116 and the formation of PMOS transistor surface.
Description of drawings
By the more specifically explanation of the preferred embodiments of the present invention shown in the accompanying drawing, above-mentioned and other purpose, feature and advantage of the present invention will be more clear.Reference numeral identical in whole accompanying drawings is indicated identical part.Painstakingly do not draw accompanying drawing in proportion, focus on illustrating purport of the present invention.In the accompanying drawings, for cheer and bright, amplified the thickness in layer and zone.
Fig. 1 is the stress film position view of cmos device:
Fig. 2 to Fig. 5 is the schematic diagram of the forming process of the existing cmos device stress film junction of explanation projection;
Fig. 6 to Figure 15 is the generalized section according to the cmos device stress film forming process of the embodiment of the invention;
Figure 16 is the stress film formation method flow diagram according to the embodiment of the invention.
Described schematic diagram is an example, and it should excessively not limit the scope of protection of the invention at this.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, the specific embodiment of the present invention is described in detail below in conjunction with accompanying drawing.
The method of stress film provided by the invention relates to PMOS transistor and the nmos pass transistor among the CMOS.A lot of details have been set forth in the following description so that fully understand the present invention.But the present invention can implement much to be different from alternate manner described here, and those skilled in the art can do similar popularization under the situation of intension of the present invention.Therefore the present invention is not subjected to the restriction of following public concrete enforcement.
Fig. 6 to Figure 15 is the cmos device stress film forming process generalized section according to the embodiment of the invention.For for simplicity, the STI isolated groove in the source electrode of not shown nmos pass transistor 116 and PMOS transistor 117 and drain electrode and grid oxic horizon, side wall (offset spacer) and the substrate.As shown in Figure 6, the cmos device that forms on Semiconductor substrate 100 comprises nmos pass transistor 116 and PMOS transistor 117, substrate 100 can be the silicon materials that comprise semiconductor element, and for example the silicon of monocrystalline, polycrystalline or non crystalline structure or SiGe (SiGe) also can be silicon-on-insulators (SOI).Deposition first stress film 110 on described nmos pass transistor 116 and PMOS transistor 117, the thickness of stress film 110 is
The method of deposition can adopt CVD technology, physical vapor deposition (PVD) technology or ald (ALD) technology, in preferred embodiment, the material of stress film 110 is a silicon nitride, and after forming stress film 110, carry out annealing steps, can use various method for annealing, for example use Halogen lamp LED or tungsten lamp, the temperature of annealing is 800～1000 ℃, and the stress film 110 after the annealing is stress films that a kind of edge laterally has tensile stress.
Then, as shown in Figure 7, first stress film, 110 surfaces between described nmos pass transistor 116 and PMOS transistor 117 form dielectric layer 200; The material of described dielectric layer 200 is the Silicon-rich polymer, is preferably bottom anti-reflection layer (BARC).Utilize spin coating (spin on) technology to form.It is the GF series of products that BARC is preferably brewer Science and Technology Ltd. trade mark, and thickness is
Be preferably
At cmos device surface coated thickness be
Photoresist, utilize the above-mentioned photoresist layers of art pattern CADization such as conventional photoetching process is for example exposed, development, cleaning, form photoresist mask pattern 210, this mask pattern 210 only covers described nmos pass transistor 116, and expose first stress film 110 and dielectric layer 200 on the PMOS transistor 117, as shown in Figure 8.
In ensuing processing step, as shown in Figure 9, first stress film 110 and dielectric layer 200 on the PMOS transistor 117 that exposes with photoresist mask pattern 210 mask etchings.Can use above-mentioned first stress film 110 of various suitable dry etching method etchings and dielectric layer 200, for example reactive ion etching or plasma etching.Next, as shown in figure 10, adopt wet-cleaned or cineration technics to remove photoresist mask pattern 210, adopt CVD technology, physical vapor deposition (PVD) technology or ald (ALD) the technology deposit second stress film material 230 then, this second stress film material 230 is a silicon nitride.Carry out annealing in process then, in various embodiments, the temperature of annealing can be used various method for annealing between 600～800 ℃, for example use Halogen lamp LED or tungsten lamp.The second stress film material 230 after the annealing is retes that a kind of edge laterally has compression stress.Subsequently, carry out cmp (CMP), grind the above-mentioned second stress film material 230, make the described second stress film material 230 surfaces and described first stress film, 110 flush, as shown in figure 11.
In ensuing processing step, be at nmos pass transistor 116 and PMOS transistor surface coated thickness
Photoresist, utilize the above-mentioned photoresist layers of art pattern CADization such as conventional photoetching process is for example exposed, development, cleaning, form photoresist mask pattern 211.First stress film 110 on the photoresist mask pattern 211 covering nmos pass transistors 116 and the second stress film material, 230 surfaces on the PMOS transistor 117, and, first stress film 110 is identical with the width of the photoresist mask pattern 211 on the second stress film material, 230 surfaces, as shown in figure 12.
Then, be the mask etching second stress film material with photoresist mask pattern 211, can adopt dry etching, for example the method for plasma etching is etched to dielectric layer 200 surfaces, as shown in figure 13.In etching process, in reative cell, the using plasma etching technics carries out etching.During etching, the directivity of etching can realize by the bias power and negative electrode (substrate just) substrate bias power of control plasma source.In the present embodiment.Feed etchant gas flow 50-400sccm in the reative cell, underlayer temperature is controlled between 20 ℃ and 90 ℃, and chamber pressure is 4-80mTorr, plasma source power output 50W-2000W.Etching agent adopts mist, and mist can comprise as SF6, CHF3, CF4, chlorine Cl
2, nitrogen N
2, helium He and oxygen O
2Mist and inert gas (such as hydrogen Ar, neon Ne, helium He or the like) or its combination.This etching agent has very high etching selection for the second stress film material silicon nitride material.Continue over etching (over etch) the second stress film material, until with first stress film, 110 flush, be thinned at over etching process medium layer 200.Just formed second stress film 120 this moment, as shown in figure 14.Adopt wet-cleaned or cineration technics to remove mask pattern 211 and remaining dielectric layer 200 at last, as shown in figure 15.As seen from Figure 15, adopt the method for twice mask etching of the present invention, protruding phenomenon has been eliminated in the junction of the stress film that nmos pass transistor 116 and PMOS transistor surface form.
Figure 16 is the stress film formation method flow diagram according to the embodiment of the invention, as shown in figure 16, as summary, at first forms in the embodiment of the inventive method and covers nmos pass transistor and the transistorized first silicon nitride stress film (S101) of PMOS; The surface of the first silicon nitride stress film between PMOS transistor and nmos pass transistor forms BARC layer (S102) then; Form first mask pattern (S103) that only covers nmos pass transistor; The first silicon nitride stress film and BARC layer on the etching PMOS transistor, and remove first mask pattern (S104); Deposit the second silicon nitride stress film material, described material surface and the described first silicon nitride stress film flush (S105); Second mask pattern (S106) of the second silicon nitride stress film material surface on first silicon nitride stress film on the formation covering nmos pass transistor and the PMOS transistor; The etching second silicon nitride stress film material is to flushing (S107) with the first silicon nitride stress film; Remove described second mask pattern and remaining BARC layer (S108).Described second mask pattern covers first stress film and the transistorized second stress film material surface of described PMOS on the described nmos pass transistor.Described first stress film is identical with the width of second mask pattern of the described second stress film material surface.Described first mask pattern only covers first stress film and the dielectric layer surface on the described nmos pass transistor.The material of described first stress film and second stress film is a silicon nitride.The material of described dielectric layer is the Silicon-rich polymer.
Be on nmos pass transistor and PMOS transistor, to form first stress film earlier among the embodiment of the invention described above, and then form second stress film with compression stress with tensile stress.In other embodiments of the invention, also can on nmos pass transistor and PMOS transistor, form first stress film earlier with compression stress.Specifically, in another embodiment of the present invention, form first stress film earlier, described first stress film covers described nmos pass transistor and PMOS transistor; The surface of first stress film between described PMOS transistor and nmos pass transistor forms dielectric layer then; Form subsequently and only cover transistorized first mask pattern of described PMOS; Follow first stress film and dielectric layer on the described nmos pass transistor of etching, and remove described first mask pattern; Deposit the second stress film material subsequently, described second stress film material surface and the described first stress film flush; Forming second mask pattern then, is that the described second stress film material of mask etching is to flushing with described first stress film with second mask pattern; Remove described second mask pattern and remaining dielectric layer at last.Wherein, described second mask pattern covers first stress film on the described PMOS transistor and the second stress film material surface of described nmos pass transistor.Described first stress film is identical with the width of second mask pattern of the described second stress film material surface.Described first mask pattern only covers first stress film and the dielectric layer surface on the described PMOS transistor.Described first stress film is the stress film with compression stress, and described second stress film is the stress film with tensile stress.The material of described first stress film and second stress film is a silicon nitride.The material of described dielectric layer is the Silicon-rich polymer.
The above only is preferred embodiment of the present invention, is not the present invention is done any pro forma restriction.Though the present invention discloses as above with preferred embodiment, yet be not in order to limit the present invention.Any those of ordinary skill in the art, do not breaking away under the technical solution of the present invention scope situation, all can utilize the method and the technology contents of above-mentioned announcement that technical solution of the present invention is made many possible changes and modification, or be revised as the equivalent embodiment of equivalent variations.Therefore, every content that does not break away from technical solution of the present invention, all still belongs in the scope of technical solution of the present invention protection any simple modification, equivalent variations and modification that above embodiment did according to technical spirit of the present invention.
Claims (14)
1, a kind of method that forms the cmos device stress film, described cmos device comprises PMOS transistor and nmos pass transistor, described method comprises the following steps:
Form first stress film, described first stress film covers described nmos pass transistor and PMOS transistor;
First stress film surface between described PMOS transistor and nmos pass transistor forms dielectric layer;
Form first mask pattern that only covers described nmos pass transistor;
First stress film and dielectric layer on the described PMOS transistor of etching, and remove described first mask pattern;
Deposit the second stress film material, described second stress film material surface and the described first stress film flush;
Form second mask pattern, described second mask pattern covers first stress film on the described nmos pass transistor and second stress film on the described PMOS transistor;
The described second stress film material of etching to the described first stress film flush;
Remove described second mask pattern and remaining dielectric layer.
2, the method for claim 1 is characterized in that: described second mask pattern covers first stress film on the described nmos pass transistor and the second stress film material surface on the described PMOS transistor.
3, method as claimed in claim 2 is characterized in that: described first stress film is identical with the width of second mask pattern of the described second stress film material surface.
4, the method for claim 1 is characterized in that: described first mask pattern covers first stress film surface on the described nmos pass transistor and the dielectric layer surface on the described nmos pass transistor.
5, the method for claim 1 is characterized in that: the material of described first stress film and second stress film is a silicon nitride.
6, the method for claim 1 is characterized in that: the material of described dielectric layer is the Silicon-rich polymer.
7, method as claimed in claim 5 is characterized in that: described first stress film is the stress film with tensile stress, and described second stress film is the stress film with compression stress.
8, a kind of method that forms the cmos device stress film, described cmos device comprises PMOS transistor and nmos pass transistor, described method comprises the following steps:
Form first stress film, described first stress film covers described nmos pass transistor and PMOS transistor;
First stress film surface between described PMOS transistor and nmos pass transistor forms dielectric layer;
Form and only cover transistorized first mask pattern of described PMOS;
First stress film and dielectric layer on the described nmos pass transistor of etching, and remove described first mask pattern;
Deposit the second stress film material, described second stress film material surface and the described first stress film flush;
Form second mask pattern, described second mask pattern covers first stress film on the described nmos pass transistor and second stress film on the described PMOS transistor;
The described second stress film material of etching is to flushing with described first stress film;
Remove described second mask pattern and remaining dielectric layer.
9, method as claimed in claim 8 is characterized in that: described second mask pattern covers first stress film on the described PMOS transistor and the second stress film material surface on the described nmos pass transistor.
10, method as claimed in claim 9 is characterized in that: described first stress film is identical with the width of second mask pattern of the described second stress film material surface.
11, method as claimed in claim 8 is characterized in that: described first mask pattern covers first stress film surface and the transistorized dielectric layer of the described PMOS surface on the described PMOS transistor.
12, method as claimed in claim 8 is characterized in that: described first stress film is the stress film with compression stress, and described second stress film is the stress film with tensile stress.
13, method as claimed in claim 8 is characterized in that: the material of described dielectric layer is the Silicon-rich polymer.
14, method as claimed in claim 12 is characterized in that: the material of described first stress film and second stress film is a silicon nitride.
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| CNB2006101188297A CN100499079C (en) | 2006-11-28 | 2006-11-28 | CMOS device stress membrane forming method |
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| CNB2006101188297A CN100499079C (en) | 2006-11-28 | 2006-11-28 | CMOS device stress membrane forming method |
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| CN100499079C true CN100499079C (en) | 2009-06-10 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102054686B (en) * | 2009-11-10 | 2013-01-02 | 中芯国际集成电路制造(上海)有限公司 | Method for forming stress membrane of complementary metal-oxide-semiconductor transistor (CMOS) device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102097377A (en) * | 2009-12-10 | 2011-06-15 | 中芯国际集成电路制造(上海)有限公司 | Making method of semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102054686B (en) * | 2009-11-10 | 2013-01-02 | 中芯国际集成电路制造(上海)有限公司 | Method for forming stress membrane of complementary metal-oxide-semiconductor transistor (CMOS) device |
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