CN100372069C

CN100372069C - Method for forming T type polycrystalline silicon gate through double inlaying process

Info

Publication number: CN100372069C
Application number: CNB2004100184529A
Authority: CN
Inventors: 金平中; 方浩; 陈平人
Original assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Current assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date: 2004-05-19
Filing date: 2004-05-19
Publication date: 2008-02-27
Anticipated expiration: 2024-05-19
Also published as: CN1700419A

Abstract

The present invention provides a method for forming a T-shaped polycrystalline silicon grid electrode by using a dual damascene technology. The method has the following steps: an oxide layer, a nitride layer and a patterning first photoetching adhesive layer are formed on the substrate of a semiconductor; the patterning first photoetching adhesive layer is used as an etching mask to etch the nitride layer and the oxide layer to form a first groove; the patterning first photoetching adhesive layer can be etched once more to form a patterning second photoetching adhesive layer; the patterning second photoetching adhesive layer is used as the etching mask to etch the nitride layer to form a second groove; then the patterning second photoetching adhesive layer is removed, and the surface of the substrate of the semiconductor is exposed from the first groove to form a grid electrode oxide layer; a polycrystalline silicon layer is deposited in the first and the second grooves to remove the residual nitride layer to obtain a polycrystalline silicon grid electrode with a T-shaped contoure.

Description

Utilize dual-damascene technics to form the method for the T type polysilicon bar utmost point

Technical field

The present invention relates to a kind of method of the T of formation type polysilicon bar utmost point, particularly a kind of method of utilizing dual-damascene technics to form the T type polysilicon bar utmost point.

Background technology

Under the trend that semi-conductive technology is advanced towards deep-submicron (deep submicron), to make the integrated level of assembly increase and size of components also with reduce, in this case, transistor must possess Miller capacitance (miller capacitance) value and the high drive current that has more common transistor low, to obtain good assembly driven nature.Therefore common technology has high drive current for reaching, and with the reduction Miller capacitance, the doping process (Source/Drainextension dopant) that carries out source/drain electrode extension area is to obtain high drive current.

But when further dwindling size of components again, when carrying out the doping process of source/drain electrode extension area, dopant ion is embedded in the polysilicon gate edge easily, will cause the polysilicon gate edge more easily to puncture like this.

Therefore, the present invention proposes a kind of method of utilizing dual-damascene technics to form the T type polysilicon bar utmost point, not only can solve the problem that above-mentioned dopant ion is embedded in the polysilicon gate edge easily, also can by reduce in the manufacture process and control gate line wide, thereby reach the purpose of the integrated level that improves assembly simultaneously.

Summary of the invention

Main purpose of the present invention, be to provide a kind of method of utilizing dual-damascene technics to form the T type polysilicon bar utmost point, when it can effectively prevent to carry out the doping process of source/drain electrode extension area, alloy is embedded in the polysilicon gate edge, and causes the lower situation of polysilicon gate edge breakdown voltage.

Another object of the present invention is to provide a kind of method of utilizing dual-damascene technics to form the T type polysilicon bar utmost point, and it has less grid live width, and then reaches the integrated level that increases assembly.

For reaching above-mentioned purpose, the invention provides a kind of method of utilizing dual-damascene technics to form the T type polysilicon bar utmost point, it includes the following step: provide an inside to be formed with the semiconductor-based end of area of isolation; On the semiconductor-based end, form an oxide layer in regular turn, the mononitride layer, an and patterning first photoresist layer, then, be mask with patterning first photoresist layer, nitride layer and oxide layer are carried out etching technics, till exposing the semiconductor-based end, form one first groove, patterning first photoresist layer is returned quarter, to form a patterning second photoresist layer; With patterning second photoresist layer is mask, nitride layer is carried out etching, to form one second groove, remove patterning second photoresist layer, to the semiconductor substrate, carry out an oxidation technology, make the semiconductor-based basal surface that exposes from first groove form a grid oxic horizon, deposition one is filled up the polysilicon layer of first, second groove, then polysilicon layer being carried out a planarization process, remove remaining nitride thing layer, is mask again with the polysilicon layer, the oxide layer that removal exposes is to obtain the polysilicon gate of a T type profile.

Beneficial effect of the present invention is: not only can solve the problem that above-mentioned dopant ion is embedded in the polysilicon gate edge easily, also can by reduce in the manufacture process and control gate line wide, thereby reach the purpose of the integrated level that improves assembly simultaneously.

Description of drawings

Fig. 1 to Fig. 7 is each step structure cutaway view of the present invention.

Fig. 8 to Figure 11 adds each step structure cutaway view behind the etching barrier layer for the present invention.

Label declaration:

The 10 semiconductor-based ends

12 oxide layers

14 nitride layers

16 patternings, first photoresist layer

18 first grooves

20 patternings, second photoresist layer

22 second grooves

24 grid oxic horizons

26 polysilicon layers

28 etching barrier layers

Embodiment

The beneficial effect that further specifies architectural feature of the present invention and reached below in conjunction with drawings and Examples.

The present invention is a kind of method of utilizing dual-damascene technics to form the T type polysilicon bar utmost point, sees also Fig. 1 to Fig. 7, is the structure cutaway view of each step of a preferred embodiment of the present invention.

At first see also Fig. 1, be formed with in an inside at the semiconductor-based end 10 of several area of isolation (not shown) and formed an oxide layer 12 in regular turn, mononitride layer 14, an and patterning first photoresist layer 16, wherein the material of nitride layer 14 can be silicon oxynitride (SiON), silicon nitride or other material, and gets with the Low Pressure Chemical Vapor Deposition deposition.Then, be mask with patterning first photoresist layer 16, nitride layer 14 and oxide layer 12 are carried out an etching technics, till exposing the semiconductor-based end 10, to form one first groove 18, structure as shown in Figure 2.

Then, as shown in Figure 3, patterning first photoresist layer 16 is returned quarter (Etching Back), to form a patterning second photoresist layer 20, is mask with patterning second photoresist layer 20 then, nitride layer 14 is carried out etching, to form one second groove 22, remove patterning second photoresist layer 20 then, form structure as shown in Figure 4, the etching technics that nitration case 14 is implemented wherein is the dry etching that oxide and nitride are had high selectivity.

As shown in Figure 5, an oxidation technology is carried out in semiconductor substrate 10, make from the surface, the semiconductor-based ends 10 that first groove 18 exposes and form a grid oxic horizon 24, wherein oxidation technology is to carry out quick oxidation processes with oxygen, because oxidation processes can be to nitride layer 14 generation effects fast, so implement after the quick oxidation processes, oxygen gas plasma only can react with the semiconductor-based end 10 that exposes from first groove 18, form a grid oxic horizon 24, then, deposition one fills up first on the semiconductor-based end 10,

second groove

18,22 polysilicon layer 26, polysilicon layer 26 is carried out a CMP (Chemical Mechanical Polishing) process (CMP), remove unnecessary polysilicon layer 26,, form structure as shown in Figure 6 to reach so-called comprehensive leveling.

At last, as shown in Figure 7, remove remaining nitride layer 14, be mask with polysilicon layer 26 then, remove the oxide layer 12 that does not cover polysilicon layer 26, to obtain the polysilicon gate of a T type profile, then, can carry out the doping process of source/drain electrode extension area according to common technology.

In addition, for avoiding when forming second groove 22, etch step to nitride layer 14 may cause damage to the semiconductor-based end 10 that exposes from first groove 18, therefore, can be before forming oxide layer 12, first on 10 surface depositions, one etching barrier layer 28, the semiconductor-based end, its structure is incited somebody to action structure as shown in Figure 8, wherein the material of etching barrier layer 28 is a nitride, and its thickness is close with nitride layer 14.

When structure as shown in Figure 8 the time, its processing step should change into: when carrying out desire when forming the etching technics of first groove 18, etch step proceeds to and exposes till the etching barrier layer 28, forms structure as shown in Figure 9.And when carrying out etching, will remove the etching barrier layer 28 that exposes from first groove 18 simultaneously, form structure as shown in figure 10 with 20 pairs of nitration cases of patterning second photoresist layer 14.

Then, please refer to Figure 11, according to aforesaid processing step, form a grid oxic horizon 24 and a polysilicon layer 26, remove nitride layer 14 then, be mask with polysilicon layer 26 at last, remove the oxide layer 12 and etching barrier layer 28 that are not covered, to form the polysilicon gate of a T type profile by polysilicon layer 26.

Polysilicon gate of the present invention, not only have less grid live width, can increase the integrated level of assembly, in the time of more can effectively preventing to carry out the doping process of source/drain electrode extension area, alloy is embedded in the polysilicon gate edge, and causes the lower situation of polysilicon gate edge breakdown voltage.

Above-described embodiment is only in order to illustrate technological thought of the present invention and characteristics; its purpose makes those of ordinary skill in the art can understand content of the present invention and is implementing according to this; the scope of this patent also not only is confined to above-mentioned specific embodiment; be all equal variation or modifications of doing according to disclosed spirit, still be encompassed in protection scope of the present invention.

Claims

1. a method of utilizing dual-damascene technics to form the T type polysilicon bar utmost point comprises the following steps:

The semiconductor substrate is provided, and its inside has formed area of isolation;

On the described semiconductor-based end, form an oxide layer in regular turn, mononitride layer, and a patterning first photoresist layer; Before forming described oxide layer, on the described semiconductor-based end, form one earlier and prevent described nitride layer etching, may cause the etching barrier layer of damage to the described semiconductor-based end; The thickness of described etching barrier layer is slightly less than described nitride layer;

With described patterning first photoresist layer is mask, and described nitride layer and described oxide layer are carried out etching, till exposing described etching barrier layer, to form one first groove;

Described patterning first photoresist layer is carried out etching one time, to form a patterning second photoresist layer;

With described patterning second photoresist layer is mask, and described nitride layer is carried out etching, makes described nitride layer form one second groove, removes described patterning second photoresist layer then;

To carrying out an oxidation technology in the described semiconductor-based end, make the described semiconductor-based basal surface that exposes from described first groove form a grid oxic horizon;

Deposition one polysilicon layer on the described semiconductor-based end, and fill up described first, second groove, then described polysilicon layer is carried out a planarization process; And

Removing remaining described nitride layer, is that mask is removed the described oxide layer that exposes with described polysilicon layer, to obtain the polysilicon gate of a T type profile then.

2. the method for utilizing dual-damascene technics to form the T type polysilicon bar utmost point according to claim 1 is characterized in that: the material of described nitride layer is silicon oxynitride or silicon nitride.

3. the method for utilizing dual-damascene technics to form the T type polysilicon bar utmost point according to claim 1 is characterized in that: after finishing the polysilicon gate of described T type profile, then can proceed the doping process of source/drain electrode.

4. the method for utilizing dual-damascene technics to form the T type polysilicon bar utmost point according to claim 1 is characterized in that: described oxidation technology is quick oxidation technology.

5. the method for utilizing dual-damascene technics to form the T type polysilicon bar utmost point according to claim 4 is characterized in that: described quick oxidation technology is to handle with oxygen gas plasma.

6. the method for utilizing dual-damascene technics to form the T type polysilicon bar utmost point according to claim 1 is characterized in that: described planarization process is a chemical mechanical polishing method.

7. the method for utilizing dual-damascene technics to form the T type polysilicon bar utmost point according to claim 1 is characterized in that: described nitride layer utilizes low-pressure chemical vapor deposition to form.

8. the method for utilizing dual-damascene technics to form the T type polysilicon bar utmost point according to claim 7 is characterized in that: the material of described etching barrier layer is a nitride.