CN111063655A - Method for manufacturing semiconductor device - Google Patents
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- CN111063655A CN111063655A CN201811210091.6A CN201811210091A CN111063655A CN 111063655 A CN111063655 A CN 111063655A CN 201811210091 A CN201811210091 A CN 201811210091A CN 111063655 A CN111063655 A CN 111063655A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
Abstract
The invention provides a manufacturing method of a semiconductor device, which comprises the following steps: providing a semiconductor substrate, wherein an interlayer dielectric layer is formed on the semiconductor substrate; forming a patterned mask layer on the interlayer dielectric layer; performing a first dry etching process by taking the patterned mask layer as a mask to form a first groove in the interlayer dielectric layer; performing a deposition process to form a polymer layer covering the side wall of the first groove; and performing a second dry etching process by taking the polymer layer as a mask to form a second groove at the bottom of the first groove, wherein the first groove and the second groove form a trapezoidal through hole. The manufacturing method of the semiconductor device provided by the invention can realize the preparation of the trapezoidal through hole only by one-time photoetching process, thereby simplifying the process flow, reducing the manufacturing cost and being more beneficial to industrialized production.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a manufacturing method of a semiconductor device.
Background
There is a strong need for new processes and process improvements in integrated circuit fabrication that allow devices and circuits to be fabricated in smaller sizes, with higher densities, higher numbers, and higher reliability. As line widths continue to decrease, the size of interconnect lines within chips also need to be correspondingly scaled down in order to accommodate smaller sized components, which makes the filling of deep trenches or holes for interconnects exceptionally difficult.
When a deposition method such as PVD or CVD is used to fill a W alloy or other conductive metal material in a deep trench or a deep hole, metal atoms preferentially grow at the opening at the top of the hole or the trench, i.e., Overhang (Overhang) occurs, and as the filling time increases, the opening at the top preferentially closes, so that a Void (Void) is formed inside the hole or the trench. As the line width and depth of the holes or trenches decrease, the voids formed become more pronounced, thereby affecting the electrical stability of the entire device and even rendering the entire device ineffective.
Therefore, in order to solve the above problems, it is necessary to provide a new method for manufacturing a semiconductor device.
Disclosure of Invention
In this summary, concepts in a simplified form are introduced that are further described in the detailed description. This summary of the invention is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.
In view of the shortcomings of the prior art, the present invention provides a method for manufacturing a semiconductor device, the method comprising:
providing a semiconductor substrate, wherein an interlayer dielectric layer is formed on the semiconductor substrate;
forming a patterned mask layer on the interlayer dielectric layer;
performing a first dry etching process by taking the patterned mask layer as a mask to form a first groove in the interlayer dielectric layer;
performing a deposition process to form a polymer layer covering the side wall of the first groove;
and performing a second dry etching process by taking the polymer layer as a mask to form a second groove at the bottom of the first groove, wherein the first groove and the second groove form a trapezoidal through hole.
Illustratively, the first etching process, the deposition process, and the second etching process are performed in the same reaction chamber.
Illustratively, the material of the polymer layer includes a fluorocarbon polymer.
Illustratively, the process gases of the deposition process include fluorocarbon gas, fluorohydrocarbon gas, and argon gas.
Illustratively, the fluorocarbon gas comprises CF4、C4F8、C4F6And/or C5F8The fluorocarbon gas comprises CH2F2、CH3F and/or CHF3。
Illustratively, the depth of the first groove is controlled by controlling a process time of the first dry etching process, the depth of the second groove is controlled by controlling a process time of the second dry etching process, and the thickness of the polymer layer is controlled by controlling a process time of the deposition process.
Illustratively, the combination of process gases for dry etching includes C4F8/AR/O2、C4F8/AR/O2/CO、C5F8/AR/O2、C5F8/AR/O2/CO、C4F6/AR/O2、C4F6/AR/O2/CO、CF4/O2、CF4/CHF3/AR and/or CF4/CHF3/AR/O2。
Another aspect of the present invention provides a method of manufacturing a semiconductor device, the method including:
providing a semiconductor substrate, wherein an interlayer dielectric layer is formed on the semiconductor substrate;
forming a patterned mask layer on the interlayer dielectric layer;
performing a first dry etching process by taking the patterned mask layer as a mask to form a first groove in the interlayer dielectric layer;
etching back the mask layer to enlarge the opening of the mask layer;
and performing a second dry etching process by taking the mask layer subjected to the back etching as a mask to increase the depth of the first groove and form a second groove at the top of the first groove, wherein the first groove and the second groove form a trapezoidal through hole.
Illustratively, the first etching process, the etch-back process, and the second etching process are performed in the same reaction chamber.
Illustratively, the process gas of the etch-back process comprises oxygen and/or nitrogen.
The manufacturing method of the semiconductor device provided by the invention can realize the preparation of the trapezoidal through hole only by one-time photoetching process, simplifies the process flow compared with the existing Damascus process, reduces the manufacturing cost and is more beneficial to industrial production.
Drawings
The following drawings of the invention are included to provide a further understanding of the invention. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
In the drawings:
fig. 1 is a process flow diagram illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention;
fig. 2A to 2F are schematic cross-sectional views illustrating devices respectively obtained at respective steps in a method of manufacturing a semiconductor device according to an embodiment of the present invention;
fig. 3 is a process flow diagram illustrating a method of manufacturing a semiconductor device according to another embodiment of the present invention;
fig. 4A to 4F are schematic cross-sectional views illustrating devices respectively obtained at respective steps in a method of manufacturing a semiconductor device according to another embodiment of the present invention.
Detailed Description
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the invention.
It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout.
It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on, adjacent to, connected or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
Spatial relational terms such as "under," "below," "under," "above," "over," and the like may be used herein for convenience in describing the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the invention should not be limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region shown as a rectangle will typically have rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted region. Also, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present invention.
As the size of interconnect lines inside chips is increasingly reduced, the filling of deep trenches or holes for interconnects becomes exceptionally difficult. When a deposition method such as PVD or CVD is used to fill W alloy or other conductive metal materials in the deep trench or the deep hole, metal atoms preferentially grow at the opening at the top of the hole or the trench, that is, overhang occurs, so that the opening at the top is preferentially closed, thereby forming a void inside the hole or the trench.
Aiming at the optimization of the filling effect of the deep hole or the deep groove, one method is to eliminate overhang formed by deposition by using a RIE (reactive ion etching) reverse etching mode after deposition, and the filling effect without a cavity is obtained through the circulation of multiple times of deposition and reverse etching. In a similar manner, although void formation can be avoided, a portion of metal is etched away during the etch-back process, thereby reducing the sputtering rate, reducing the deposition efficiency and increasing the cost. From the same view of flaring, another method is to put the developed sample into a wet groove, increase the CD of the top by utilizing the isotropic characteristic of wet etching, and then transfer the sample to a dry etching machine to finish the final etching, so as to obtain the required sidewall morphology and control the CD of the bottom. However, by using the wet flaring method, the top CD is difficult to control, and thus the requirement of actual industrial production is difficult to meet. In addition, the via holes with openings of different widths can be realized by using a mode of twice glue coating and exposure, and the via holes with different opening widths at the top and the bottom can be realized by matching with twice etching processes, namely the damascene process.
In view of the above problems, the present invention provides a method for manufacturing a semiconductor device, comprising: providing a semiconductor substrate, wherein an interlayer dielectric layer is formed on the semiconductor substrate; forming a patterned mask layer on the interlayer dielectric layer; performing a first dry etching process by taking the patterned mask layer as a mask to form a first groove in the interlayer dielectric layer; performing a deposition process to form a polymer layer covering the side wall of the first groove; and performing a second dry etching process by taking the polymer layer as a mask to form a second groove at the bottom of the first groove, wherein the first groove and the second groove form a trapezoidal through hole.
Another aspect of the present invention provides a method of manufacturing a semiconductor device, including: providing a semiconductor substrate, wherein an interlayer dielectric layer is formed on the semiconductor substrate; forming a patterned mask layer on the interlayer dielectric layer; performing a first dry etching process by taking the patterned mask layer as a mask to form a first groove in the interlayer dielectric layer; etching back the mask layer to enlarge the opening of the mask layer; and performing a second dry etching process by taking the mask layer subjected to the back etching as a mask to increase the depth of the first groove and form a second groove at the top of the first groove, wherein the first groove and the second groove form a trapezoidal through hole.
The manufacturing method of the semiconductor device provided by the invention can realize the preparation of the trapezoidal through hole only by one-time photoetching process, simplifies the process flow compared with the existing Damascus process, reduces the manufacturing cost and is more beneficial to industrial production.
In the following description, for purposes of explanation, specific details are set forth in order to provide a thorough understanding of the present invention. The following detailed description of the preferred embodiments of the invention, however, the invention is capable of other embodiments in addition to those detailed. [ exemplary embodiment one ]
A method for manufacturing a semiconductor device according to an embodiment of the present invention will be described in detail below with reference to fig. 1 and fig. 2A to 2F.
First, step 101 is performed, as shown in fig. 2A, a semiconductor substrate 200 is provided, and an interlayer dielectric layer 201 is formed on the semiconductor substrate 200.
The material of the semiconductor substrate 200 may include a semiconductor element, such as silicon or silicon germanium in a single crystal, polycrystalline, or amorphous structure, a mixed semiconductor structure, such as silicon carbide, indium antimonide, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide, an alloy semiconductor, or a combination thereof, silicon-on-insulator (SOI), and the semiconductor substrate 200 may be an epitaxial layer or a buried layer in a multilayer structure. The semiconductor substrate 200 may further have a device structure formed therein, and the device structure may be a device structure formed in a front-end semiconductor process, such as a MOS transistor. As an example, in the present embodiment, the constituent material of the semiconductor substrate 200 is monocrystalline silicon.
An interlayer dielectric layer 201 is formed on the semiconductor substrate 200. The interlayer dielectric layer 201 is used to isolate and insulate the metal interconnection layer, and usually uses a material with a low dielectric constant, so as to effectively reduce the parasitic capacitance between interconnection structures such as conductive plugs and the like formed in the dielectric layer. The interlevel dielectric layer 201 material may comprise various forms of grown insulating silicon dioxide material, such as BPSG, PSG, FSG, USG, TEOS, thermal oxide silicon dioxide, wet oxide silicon dioxide, silicon-rich silicon dioxide SRO, or combinations of layers thereof, which may be formed by a chemical vapor deposition process, such as Plasma Enhanced Chemical Vapor Deposition (PECVD) or high density plasma enhanced chemical vapor deposition (HDP-CVD).
Next, step 102 is performed to form a patterned mask layer on the interlayer dielectric layer 201.
Specifically, a mask layer covering the interlayer dielectric layer 201 is first formed. The mask layer may be a photoresist layer, or a composite structure composed of a photoresist layer, an anti-reflection layer and a hard mask layer, or other materials or structures that can be used as mask layers, such as a polysilicon layer, a silicon nitride layer, a silicon carbide layer, or a metal film layer. In the present embodiment, the mask layer includes a photoresist layer 203, and the photoresist layer 203 may be formed using a spin-on process. Illustratively, an anti-reflective layer 202 is further formed under the photoresist layer, the anti-reflective layer 202 may be a single layer or multiple layers of organic, which can improve the quality of exposure and ensure that the photoresist layer forms a desired pattern after development, and the anti-reflective layer 202 includes a bottom anti-reflective coating (BARC), a dielectric anti-reflective coating (DARC), or a combination thereof. Next, the photoresist layer 203 is patterned by exposure, development, and the like to form a patterned photoresist layer.
Next, step 103 is executed, as shown in fig. 2B, a first dry etching process is executed by using the patterned mask layer as a mask, so as to form a first groove in the interlayer dielectric layer 201.
Specifically, the anti-reflection layer 202 and the interlayer dielectric layer 201 with a first depth are removed longitudinally along the opening of the photoresist layer 203 by utilizing anisotropic dry etching in the dry etching reaction cavity, so as to form a first groove with a first depth in the interlayer dielectric layer 201. The etching gas used in the anisotropic dry etching may include C4F8/AR/O2、C4F8/AR/O2/CO、C5F8/AR/O2、C5F8/AR/O2/CO、C4F6/AR/O2、C4F6/AR/O2/CO、CF4/O2、CF4/CHF3/AR、CF4/CHF3/AR/O2One or more of them.
In the process of executing the first dry etching process, the first depth can be controlled by controlling the process time of the first dry etching process, and the first depth is the depth of the upper half part with larger width in the subsequently formed trapezoidal through hole. By increasing the time of the first dry etching process, the depth of the first groove is increased. Thereby, a precise control of the depth of the first groove may be achieved.
Next, in step 104, as shown in fig. 2C, a deposition process is performed to form a polymer layer 204 covering the sidewalls of the first recess.
In one embodiment, by adjusting the process parameters, the deposition process and the first dry etching process in step 103 can be performed in the same reaction chamber, thereby greatly reducing the time required for transferring samples between chambers and shortening the production cycle of products.
In one embodiment, the polymer layer 204 is a fluorocarbon polymer. The process gas of the deposition process comprisesFluorocarbon gas, fluorohydrocarbon gas, and argon gas. Wherein the fluorocarbon gas comprises CF4、C4F8、C4F6And/or C5F8The fluorocarbon gas comprises CH2F2、CH3F and/or CHF3That is, the process gas combination used for the deposition process may be CF4/AR/CH2F2、CF4/AR/CH3F、CF4/AR/CHF3、C4F8/AR/CH2F2、C4F8/AR/CH3F、C4F8/AR/CHF3、C4F6/AR/CH2F2、C4F6/AR/CH3F、C4F6/AR/CHF3、C5F8/AR/CH2F2、C5F8/AR/CH3F、C5F8/AR/CHF3One of them. Due to CF4、C4F8、C4F6、C5F8The fluorocarbon gas can form long and strong polymer, which is deposited on the bottom of the first groove as much as possible, and CH2F2、CH3F、CHF3The equal fluorocarbon gas may form a short and weak polymer, which may be deposited on the sidewalls of the first recess as much as possible, so that the polymer layer 204 may be uniformly deposited in the first recess, avoiding excessive deposition of the polymer layer on the bottom of the first recess.
During the deposition process, the thickness of the polymer layer 204, i.e., the difference between the radii of the upper half and the lower half of the trapezoid via to be formed later, can be controlled by controlling the process time of the deposition process. Increasing the time of the deposition process, the thickness of the polymer layer 204 increases. Therefore, the accurate control of the through hole morphology can be realized.
Next, step 105 is executed, as shown in fig. 2D, a second dry etching process is executed by using the polymer layer 204 as a mask, so as to form a second groove at the bottom of the first groove, where the first groove and the second groove form a trapezoidal through hole.
Because the upper half part of the formed trapezoidal through hole is larger in width, and the lower half part of the formed trapezoidal through hole is smaller in width, even if metal atoms preferentially grow at the opening of the top of the trapezoidal through hole in the subsequent process of filling a metal layer in the trapezoidal through hole, the generation of empty holes due to premature closing of the top can be avoided.
In one embodiment, the second dry etching process may be performed in the same reaction chamber as the deposition process by adjusting process parameters. Further, the second dry etching process, the deposition process, and the first dry etching process may be performed in the same reaction chamber. Therefore, the time required for transferring the sample between the cavities is greatly reduced, and the production period of the product is shortened.
Specifically, anisotropic dry etching is used in the dry etching reaction cavity, the polymer layer 204 on the sidewall of the first groove is used as a mask, and the polymer layer 204 at the bottom of the first groove and the interlayer dielectric layer 201 with a second depth are removed longitudinally to form a second groove with a second depth in the interlayer dielectric layer 201, wherein the second depth is a distance from the bottom of the second groove to the bottom of the first groove. The etching gas used for the anisotropic dry etching may include C4F8/AR/O2、C4F8/AR/O2/CO、C5F8/AR/O2、C5F8/AR/O2/CO、C4F6/AR/O2、C4F6/AR/O2/CO、CF4/O2、CF4/CHF3/AR、CF4/CHF3/AR/O2One or more of them.
In the process of executing the second dry etching process, the second depth can be controlled by controlling the process time of the second dry etching process, and the second depth is the depth of the lower half part with smaller width in the subsequently formed trapezoidal through hole. By increasing the time of the second dry etching process, the depth of the second groove is increased. Thereby, a precise control of the depth of the second groove may be achieved.
Next, as shown in fig. 2E, the patterned mask layer and the polymer layer are removed.
Illustratively, the removal of the patterned masking layer and the polymer layer is performed in the same reaction chamber after step 105 is completed. In one embodiment, the method of removing the patterned mask layer and the polymer layer is CO2The plasma processing method is that under the condition of low pressure, carbon dioxide or carbon monoxide is introduced into the same etching reaction cavity to carry out the plasma ashing process.
Next, as shown in fig. 2F, the trapezoidal via hole is filled with a metal layer. The through hole formed in the embodiment is a trapezoidal through hole and has the shape of being wide at the top and narrow at the bottom, so that the problem that the through hole opening is closed too early due to the formation of the overhang on the side wall of the through hole can be effectively solved, and the defect that a hollow hole is formed in the metal layer in the trapezoidal through hole is overcome. The metal layer includes, but is not limited to, a tungsten layer.
For example, the barrier layer/seed layer may be deposited in the trench and the via hole, after the deposition is completed, the trench and the via hole may be filled with a metal layer, and finally, the metal layer may be subjected to a chemical mechanical polishing process to remove a portion of the metal layer located outside the trapezoid via hole, thereby completing the preparation process of the entire interconnect structure.
Thus, the description of the steps related to the method of manufacturing a semiconductor device of the embodiment of the present invention is completed. It is understood that the method for manufacturing a semiconductor device of the present embodiment includes not only the above-described steps but also other necessary steps before, during or after the above-described steps, which are included in the scope of the manufacturing method of the present embodiment.
The manufacturing method of the semiconductor device provided by the invention can realize the preparation of the trapezoidal through hole only by one-time photoetching process, simplifies the process flow compared with the existing Damascus process, reduces the manufacturing cost and is more beneficial to industrial production.
[ second exemplary embodiment ]
A method for manufacturing a semiconductor device according to another embodiment of the present invention will be described in detail below with reference to fig. 3 and 4A to 4F.
First, step 301 is performed, as shown in fig. 4A, a semiconductor substrate 400 is provided, and an interlayer dielectric layer 401 is formed on the semiconductor substrate 400.
The material of the semiconductor substrate 400 may include a semiconductor element, such as silicon or silicon germanium in a single crystal, polycrystalline, or amorphous structure, a mixed semiconductor structure, such as silicon carbide, indium antimonide, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide, an alloy semiconductor, or a combination thereof, silicon-on-insulator (SOI), and the semiconductor substrate 400 may also be an epitaxial layer or a buried layer in a multilayer structure. The semiconductor substrate 400 may also have device structures formed therein, and the device structures may be device structures formed in a front-end semiconductor process, such as MOS transistors. As an example, in the present embodiment, the constituent material of the semiconductor substrate 400 is single crystal silicon.
An interlayer dielectric layer 401 is formed on the semiconductor substrate 400. The interlayer dielectric layer 401 is used to isolate and insulate the metal interconnection layers, and usually uses a material with a low dielectric constant, so as to effectively reduce the parasitic capacitance between interconnection structures such as conductive plugs and the like which are formed in the dielectric layer. The interlevel dielectric layer 401 material may comprise various forms of grown insulating silicon dioxide material, such as BPSG, PSG, FSG, USG, TEOS, thermal oxide silicon dioxide, wet oxide silicon dioxide, silicon-rich silicon dioxide SRO, or combinations of layers thereof, which may be formed by a chemical vapor deposition process, such as Plasma Enhanced Chemical Vapor Deposition (PECVD) or high density plasma enhanced chemical vapor deposition (HDP-CVD), among others.
Next, step 302 is performed to form a patterned mask layer on the interlayer dielectric layer 401.
Specifically, a mask layer covering the interlayer dielectric layer 401 is first formed. The mask layer may be a photoresist layer, or a composite structure composed of a photoresist layer, an anti-reflection layer and a hard mask layer, or other materials or structures that can be used as mask layers, such as a polysilicon layer, a silicon nitride layer, a silicon carbide layer, or a metal film layer. In the present embodiment, the mask layer includes a photoresist layer 403, and the photoresist layer 403 may be formed using a spin-on process. Illustratively, an anti-reflective layer 402 is also formed under the photoresist layer, the anti-reflective layer 402 may be a single layer or multiple layers of organic, which may improve the quality of the exposure and ensure that the photoresist layer forms a desired pattern after development, the anti-reflective layer 402 may include a bottom anti-reflective coating (BARC), a dielectric anti-reflective coating (DARC), or a combination thereof. Next, the photoresist layer 403 is patterned by exposure, development, and the like to form a patterned photoresist layer.
Next, step 303 is executed, as shown in fig. 4B, a first dry etching process is executed by using the patterned mask layer as a mask, so as to form a first groove in the interlayer dielectric layer 401.
Specifically, the anti-reflection layer 402 and a part of the interlayer dielectric layer 401 are removed longitudinally along the opening of the photoresist layer 403 by anisotropic dry etching in the dry etching reaction cavity, so as to form a first groove in the interlayer dielectric layer 401. The etching gas used in the anisotropic dry etching may include C4F8/AR/O2、C4F8/AR/O2/CO、C5F8/AR/O2、C5F8/AR/O2/CO、C4F6/AR/O2、C4F6/AR/O2/CO、CF4/O2、CF4/CHF3/AR、CF4/CHF3/AR/O2One or more of them. In the process of executing the first dry etching process, the depth of the first groove can be controlled by controlling the process time of the first dry etching process, and the depth of the first groove can be increased by increasing the time of the first dry etching process.
Next, step 304 is performed, as shown in fig. 4C, the mask layer 403 is etched back to enlarge the opening of the mask layer 403.
In one embodiment, by adjusting the process parameters, the etch-back process and the first dry etching process in step 303 can be performed in the same reaction chamber, thereby greatly reducing the time required for transferring samples between chambers and shortening the production cycle of products.
In one embodiment, the process gas used in the etch-back process comprises oxygen or nitrogen.
In the process of performing the back etching process, the size of the opening can be controlled by controlling the process time of the back etching process, namely, the original size of the opening of the mask layer is equivalent to the width of the lower half part of the subsequently formed trapezoidal through hole, and the size of the opening of the mask layer after the back etching process is equivalent to the width of the upper half part of the trapezoidal through hole. Therefore, the accurate control of the through hole morphology can be realized.
Next, step 305 is executed, as shown in fig. 4D, a second dry etching process is executed by using the mask layer subjected to the back etching as a mask to increase the depth of the first groove, and a second groove is formed at the top of the first groove, where the first groove and the second groove form a trapezoidal through hole.
Specifically, in the process of the second dry etching process, the depth of the groove formed in step 303 is further increased, so that a part with a smaller width at the bottom of the trapezoidal through hole is formed; meanwhile, because the opening of the mask layer is enlarged, a part of the interlayer dielectric layer 401 exposed by the enlarged opening of the mask layer is also removed, so that a part with a larger width at the top of the trapezoidal through hole is formed.
Because the upper half part of the formed trapezoidal through hole is larger in width, and the lower half part of the formed trapezoidal through hole is smaller in width, even if metal atoms preferentially grow at the opening of the top of the trapezoidal through hole in the subsequent process of filling a metal layer in the trapezoidal through hole, the generation of empty holes due to premature closing of the top can be avoided.
In one embodiment, the second dry etching process may be performed in the same reaction chamber as the etch-back process by adjusting process parameters. Further, the second dry etching process, the etch-back process, and the first dry etching process may be performed in the same reaction chamber. Therefore, the time required for transferring the sample between the cavities is greatly reduced, and the production period of the product is shortened.
Specifically, the depth of the first groove is longitudinally deepened by anisotropic dry etching in the dry etching reaction cavity, and another second groove with a larger width is formed above the first groove, so as to form a trapezoidal through hole in the interlayer dielectric layer 401. The etching gas used for the anisotropic dry etching may include C4F8/AR/O2、C4F8/AR/O2/CO、C5F8/AR/O2、C5F8/AR/O2/CO、C4F6/AR/O2、C4F6/AR/O2/CO、CF4/O2、CF4/CHF3/AR、CF4/CHF3/AR/O2One or more of them.
In the process of executing the second dry etching process, the depth of the trapezoidal through hole can be controlled by controlling the process time of the second dry etching process. By increasing the time of the second dry etching process, the depth of the trapezoidal through hole is increased.
Next, as shown in fig. 4E, the patterned mask layer is removed.
Illustratively, the removal of the patterned masking layer is performed within the same reaction chamber after step 305 is completed. In one embodiment, the patterned mask layer is removed by CO2The plasma processing method is that under the condition of low pressure, carbon dioxide or carbon monoxide is introduced into the same etching reaction cavity to carry out the plasma ashing process.
Next, as shown in fig. 4F, the trapezoidal via is filled with a metal layer 404. The through hole formed in the embodiment is a trapezoidal through hole and has the shape of being wide at the top and narrow at the bottom, so that the problem that the through hole opening is closed too early due to the formation of the overhang on the side wall of the through hole can be effectively solved, and the defect that a hollow hole is formed in the metal layer in the trapezoidal through hole is overcome. The metal layer includes, but is not limited to, a tungsten layer.
For example, the barrier layer/seed layer may be deposited in the trench and the via hole, after the deposition is completed, the trench and the via hole may be filled with a metal layer, and finally, the metal layer may be subjected to a chemical mechanical polishing process to remove a portion of the metal layer located outside the trapezoid via hole, thereby completing the preparation process of the entire interconnect structure.
Thus, the description of the steps related to the method of manufacturing a semiconductor device of the embodiment of the present invention is completed. It is understood that the method for manufacturing a semiconductor device of the present embodiment includes not only the above-described steps but also other necessary steps before, during or after the above-described steps, which are included in the scope of the manufacturing method of the present embodiment.
The manufacturing method of the semiconductor device provided by the invention can realize the preparation of the trapezoidal through hole only by one-time photoetching process, simplifies the process flow compared with the existing Damascus process, reduces the manufacturing cost and is more beneficial to industrial production.
The present invention has been illustrated by the above embodiments, but it should be understood that the above embodiments are for illustrative and descriptive purposes only and are not intended to limit the invention to the scope of the described embodiments. Furthermore, it will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that many variations and modifications may be made in accordance with the teachings of the present invention, which variations and modifications are within the scope of the present invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.
Claims (10)
1. A method of manufacturing a semiconductor device, the method comprising:
providing a semiconductor substrate, wherein an interlayer dielectric layer is formed on the semiconductor substrate;
forming a patterned mask layer on the interlayer dielectric layer;
performing a first dry etching process by taking the patterned mask layer as a mask to form a first groove in the interlayer dielectric layer;
performing a deposition process to form a polymer layer covering the side wall of the first groove;
and performing a second dry etching process by taking the polymer layer as a mask to form a second groove at the bottom of the first groove, wherein the first groove and the second groove form a trapezoidal through hole.
2. The method of manufacturing of claim 1, wherein the first etching process, the deposition process, and the second etching process are performed in a same reaction chamber.
3. The method of manufacturing of claim 1, wherein the material of the polymer layer comprises a fluorocarbon polymer.
4. The manufacturing method according to claim 3, wherein the process gas of the deposition process includes a fluorocarbon gas, a fluorohydrocarbon gas, and an argon gas.
5. The method of manufacturing according to claim 4, wherein the fluorocarbon gas comprises CF4、C4F8、C4F6And/or C5F8The fluorocarbon gas comprises CH2F2、CH3F and/or CHF3。
6. The manufacturing method according to claim 1, wherein the depth of the first recess is controlled by controlling a process time of the first dry etching process, the depth of the second recess is controlled by controlling a process time of the second dry etching process, and the thickness of the polymer layer is controlled by controlling a process time of the deposition process.
7. The method of manufacturing of claim 1, wherein the combination of dry etched process gases comprises C4F8/AR/O2、C4F8/AR/O2/CO、C5F8/AR/O2、C5F8/AR/O2/CO、C4F6/AR/O2、C4F6/AR/O2/CO、CF4/O2、CF4/CHF3/AR and/or CF4/CHF3/AR/O2。
8. A method of manufacturing a semiconductor device, the method comprising:
providing a semiconductor substrate, wherein an interlayer dielectric layer is formed on the semiconductor substrate;
forming a patterned mask layer on the interlayer dielectric layer;
performing a first dry etching process by taking the patterned mask layer as a mask to form a first groove in the interlayer dielectric layer;
etching back the mask layer to enlarge the opening of the mask layer;
and performing a second dry etching process by taking the mask layer subjected to the back etching as a mask to increase the depth of the first groove and form a second groove at the top of the first groove, wherein the first groove and the second groove form a trapezoidal through hole.
9. The method of manufacturing according to claim 8, wherein the first etching process, the etch-back process, and the second etching process are performed in the same reaction chamber.
10. Manufacturing method according to claim 9, characterized in that the process gas of the etch back process comprises oxygen and/or nitrogen.
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| CN116936469A (en) * | 2023-09-14 | 2023-10-24 | 深圳基本半导体有限公司 | Method for manufacturing semiconductor device |
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