JPH10340952A - Method for forming multilayer wiring in integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enhance mass productivity without sacrificing step coverage by forming a first wiring in a first shallow trench while a first metal plug in a first deep trench and connecting the first metal plug electrically with an electrode on a silicon semiconductor wafer through the deep trench. SOLUTION: A metal film containing copper, titanium, or the like, is deposited by CVD to fill first shallow and deep trenches 31, 35. The metal film is then removed by plasma etchback, or the like, except the first shallow and deep trenches 31, 35 to form a second wiring 38A in the first shallow trench 31 and a first metal plug 38B in the first deep trenches 35. The first metal plug 38B is connected electrically with a first wiring 24 through the first deep trenches 35. According to the structure, an ideal step coverage is realized by the deep trench having a step and mass productivity of multilayer wiring integrated circuit can be enhanced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a metal interconnect and a metal plug of an integrated circuit.
g), especially the chemical vapor deposition method (Chemica
The present invention relates to a method for forming a multilayer wiring of an integrated circuit, in which a metal wiring and a metal plug are formed by a metal film formed by using (vapor deposition = CVD).

[0002]

2. Description of the Related Art With the continuous miniaturization of integrated circuit devices, in the era of submicron technology, interconnect technology has been continually scaled down in order to increase the integration density. The formation of complex metal wiring becomes increasingly difficult, and at the same time, contact holes and through holes (Via Hol
e) Step Coverage Problem
It is becoming more and more serious. For example, since the etching selectivity of the photoresist to the metal is too large, the photolithography and the plasma etching (Photolithography and Plasma-Etching) are used.
It is very difficult to form a metal wiring of 15 μm to 0.35 μm. Also, even if the metal wiring becomes thinner and thinner, the thickness of the metal wiring does not decrease so much, so that the ratio of the thickness to the width becomes larger (H
igh Aspect Ratio), a considerably undulating form (Severe
Topography), which is very disadvantageous for the subsequent thin film deposition and photolithography and etching processes.

[0003] In order to solve the problem that the ratio of the thickness to the width of the metal wiring becomes larger, an engineer of NEC Corporation of Japan in 1995 referred to “VLSI SS”.
YMPOSIUM ”, pp. 27-28, the embedded metal formed by the chemical vapor deposition method (Recesse
d Metal) to form a metal wiring and a metal plug. Here, the method will be briefly described. First, a dielectric film and a hard mask are formed on the surface of a silicon semiconductor wafer, and the hard mask is used as an etch stop film. Next, after forming a first photoresist pattern by photolithography, the dielectric film and the hard mask are partially etched out by plasma etching to form a first shallow groove on the surface of the dielectric film. . Further, a second photoresist pattern is formed using another photolithography mask, and the first photoresist pattern is formed using the second photoresist pattern.
And partially exposing the first shallow groove. The etching rate of the hard mask is much smaller than that of the dielectric film, and
Misalignment (Mis
Even if alignment) occurs, it is possible to prevent the hard mask from acting as an etch stop film and etching the dielectric film under the hard mask. Then, the first shallow groove exposed by the plasma etching technique is continuously etched to expose a metal film thereunder, and the first shallow groove is used as a second deep groove. Next, after removing the second photoresist pattern and the hard mask, a metal film is formed by a chemical vapor deposition method, and the metal film is buried in the first shallow groove and the second deep groove. It is. And plasma etch back technology
(Plasma Etchback) or chemical mechanical polishing (Chemical
The metal film other than the first shallow groove and the second deep groove is removed by a mechanical polishing (CMP) technique, and a metal wiring is formed inside the first shallow groove. A metal plug is formed on the substrate.

[0004]

The problem to be solved by the present invention is that the above NEC proposal has not been sufficiently improved in step coverage and mass productivity. Therefore, the purpose of forming metal wirings and metal plugs with a metal film formed by using a chemical vapor deposition method without impairing good step coverage and improving mass productivity is as follows. It is realized by means.

[0005]

In order to solve the above-mentioned problems, a manufacturing method according to the present invention is configured as follows. First, a first dielectric film is formed on a surface of a silicon semiconductor wafer. This silicon semiconductor wafer has a field oxide film, a metal oxide film semiconductor field effect transistor (MOS-FE
T) or an electric element such as a capacitor and an electric resistance, and the metal oxide semiconductor field effect transistor includes a gate oxide film, a gate electrode and a source / drain. The first dielectric film is usually formed by low pressure chemical vapor deposition (Low Pressure Chemical Vapor).
or Deposition = LPCVD) to form a doped silicon dioxide film, the reaction gas of which is monosilane (Monosilane = SiH ₄ ) or tetraethyloxysilane.
(Tetra-Eth-Oxy-Silane = TEOS) with a thickness of 3
It is between 000 and 8000. In many cases, the first dielectric film is planarized using chemical mechanical polishing (CMP) in combination.

Next, after a second dielectric film is formed, a first photoresist pattern is formed by photolithography. Using the first photoresist pattern as an etch mask, the second dielectric film and a predetermined pattern are formed by plasma etching. A first shallow groove is formed on the surface of the first dielectric film by etching out the first dielectric film having a thickness. Then, the first photoresist pattern is partially removed from the side by a resist erosion technique (Resist Erosion) to partially expose the second dielectric film, and the second dielectric film exposed by plasma etching is etched out. But,
Plasma etching is performed up to the surface of the first dielectric film to complete the etching and to remove the first photoresist pattern.

Subsequently, a second photoresist pattern is formed by a photolithography technique.
A photoresist pattern covers a portion of the first shallow groove and a portion of the second dielectric film, exposing a portion of the first shallow groove and a portion of the second dielectric film. Using the second photoresist pattern and the partially exposed second dielectric film as an etch mask, the exposed first dielectric film is etched away by plasma etching. This plasma etching is performed by the metal under the first dielectric film. By performing the process up to the film, the first shallow groove becomes a first deep groove. Then, the second photoresist pattern and the second dielectric film are removed. At this time, on the surface of the first dielectric film,
A first shallow groove and a first deep groove are formed.

Next, a metal film is formed by using a chemical vapor deposition method. The metal film includes a metal such as copper, titanium, tungsten, aluminum and titanium nitride. It is embedded in the first shallow groove and the first deep groove. Finally, the metal film in the region other than the first shallow groove and the first deep groove is removed by plasma etch back or chemical mechanical polishing to form a first metal wiring inside the first shallow groove. A first metal plug is formed inside the first deep groove, and the first metal plug is electrically connected to an electrode on the silicon semiconductor wafer via the first deep groove (corresponding to a contact hole).

Further, by forming a third dielectric film and a fourth dielectric film and repeating the above procedure, a second shallow groove and a second deep groove are formed, and the second shallow groove is formed in the second shallow groove. A metal wiring may be formed, and a second metal plug may be formed in the second deep groove. The second metal plug is electrically connected to the first metal wiring via the second deep groove (corresponding to a through hole). Can be.

According to the present invention, a shallow groove and a deep groove having a step are formed on a dielectric film by a photoresist erosion technique.
A shallow groove and a deep groove with a step are buried by a metal film by VD (chemical vapor deposition). The deep step with a groove realizes ideal step coverage, and a plasma etch back or CMP ( The metal film in the region other than the shallow groove and the deep groove with a step is removed by a chemical mechanical polishing method), a metal wiring is formed inside the shallow groove, and a metal plug is formed inside the deep groove with a step. The method for forming a multilayer wiring can be applied to mass production of a multilayer wiring integrated circuit.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings. Further, the method of the present invention is described based on a through-hole of a double-level metal interconnect technology of an integrated circuit.
The method of the present invention employs a multi-level metal interconnect.
connection) It can also be applied to the manufacture of integrated circuits by technology.

First, in FIG. 1, the electric resistance value is about 3.
A field oxide film (not shown) is formed on the surface of a P-type silicon semiconductor wafer 20 having a crystal orientation (100) of 5 ohm-cm.
The interval between 00 ° is for electric element separation. And P
A metal oxide semiconductor field effect transistor (MOS-FET, not shown) is formed on the silicon wafer 20. A gate oxide film, a gate electrode, and a source / drain are formed in the metal oxide semiconductor field effect transistor. (Neither is shown). Further, polysilicon or polycide is formed on the field oxide film, and serves as a local interconnect (Local Interconnection) of the metal oxide semiconductor field effect transistor (both are not shown).

Next, referring to FIG. 1, an insulating film 22 is formed, and a first metal wiring 24 is formed on the insulating film 22. The insulating film 22 is usually made of a boron-phosphorus-silicate glass (Boro-Phospho-Si
(License-Glass = BPSG) film or Phospho-Silicate-Glass (PSG) film is formed, and its thickness is set between 3000 and 8000 mm. After the insulating film 22 is deposited, the insulating film 22 is made flat by a known thermal flow technique. The heat flow temperature is set to 850 ° C. to 950 ° C., and the heat flow time is reduced. Between 10 minutes and 40 minutes. Note that the insulating film 22 may be planarized by a known chemical mechanical polishing technique. Then, the insulating film 22 is partially etched out by photolithography and plasma etching to form a contact hole. The bottom of this contact hole is the source / drain or local wiring of the P-type silicon semiconductor wafer 20, and is electrically connected by a metal plug formed later (neither is shown). The first metal wiring 24 is made of titanium, titanium nitride, and an aluminum alloy. The titanium metal is located below the titanium nitride, and is electrically connected to the source / drain region of the metal oxide semiconductor field effect transistor. (Both not shown).

2 and 3, the first dielectric film 26
Subsequently, a second dielectric film 28 is formed, and the first dielectric film 26 is flattened by a known technique of chemical mechanical polishing. Then, a first photoresist pattern 30 is formed by photolithography. The first dielectric film 26 is usually formed by plasma enhanced chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition).
(Chemical Vapor Deposition = PECVD) to form silicon dioxide.
It is between 0 ° C. and its thickness is between 3000 ° and 6000 °. The second dielectric film 28 is usually for depositing silicon nitride by a plasma enhanced chemical vapor deposition method.
The deposition temperature is between 300 ° C. and 400 ° C. and its thickness is between 500 ° and 2000 °. As the second dielectric film 28, amorphous silicon can be deposited by plasma CVD.

In FIG. 4, using the first photoresist pattern 30 as an etch mask, the first dielectric film 26 and the second dielectric film 28 having a constant thickness are removed by plasma etching, and the surface of the first dielectric film 26 is removed. First shallow groove 3
Form one. For the anisotropic etching of the first dielectric film 26 and the second dielectric film 28, magnetron-type reactive ion etching, electron cyclotron resonance, or conventional reactive ion etching can be used. Usually, magnetron-type reactive ion etching is used, and the plasma reaction gas is generally a gas such as CH ₄ , CHF ₃ , or Ar.

In FIGS. 5 and 6, the first photoresist pattern 30 is partially removed from the side under an oxygen plasma atmosphere by a resist erosion technique to partially expose the second dielectric film 28 (see FIG. 5). (Not shown), the second dielectric film 28 exposed by the anisotropic plasma etching technique is etched out.
6, the etching is completed (see FIG. 5), and the first photoresist pattern 30 is removed (see FIG. 6). Anisotropic etching of the second dielectric film 28 uses magnetron-type reactive ion etching, and the plasma reaction gas is CH ₄ , CHF ₃ , A
gas such as r.

7 to 9, a second photoresist pattern 34 is formed by photolithography. The second photoresist pattern 34 is formed by a part of the second dielectric film 28 and a part of the first shallow groove 31. To expose a part of the second dielectric film 28 and a part of the first shallow groove 31 (see FIG. 7). Then, the first dielectric film 26 is etched out by anisotropic plasma etching using the partially exposed second dielectric film 28 and the second photoresist pattern 34 as an etch mask. At the first metal wiring 24 in the first shallow groove 31 and the first shallow groove 31
(See FIG. 8). The first deep groove 35 has a stepped shape (Ladder Shape) and provides an almost ideal step coverage. Next, if the second dielectric film 28 and the second photoresist pattern 34 are removed, a first shallow groove 31 and a first deep groove 35 are formed on the surface of the first dielectric film 26 as shown in FIG. can do. The anisotropic etching of the exposed second dielectric film 28 is also performed by magnetron-type reactive ion etching, and the plasma reaction gas is changed to CH ₄ or CH ₄ .
A gas such as F ₃ or Ar can be used.

In FIGS. 10 and 11, a metal film 38 is deposited by a chemical vapor deposition method. This metal film contains metals such as copper, titanium, tungsten, aluminum, and titanium nitride. The film 38 is embedded in the first shallow groove 31 and the first deep groove 35 (FIG. 1).
0). Finally, the metal film 38 other than the first shallow groove 31 and the first deep groove 35 is removed by plasma etch back or chemical mechanical polishing, and the first shallow groove 31 is removed.
The second metal wiring 38A is formed inside, and the first metal plug 38B is formed inside the first deep groove 35 (see FIG. 11). As shown in FIG. 11, the first metal plug 38B
Are electrically connected to the first metal wiring 24 via the first deep groove 35. The first deep groove 35 at this time corresponds to a general contact hole.

After the structure shown in FIG. 11 is completed, the above-described method is repeated to form an upper metal wiring and a metal plug. In this case, a second deep groove is formed in a general through hole. (Both not shown). That is, the method for forming a multilayer wiring of an integrated circuit according to the present invention can be applied to the manufacture of an integrated circuit by a multilayer metal wiring technique.

The present invention has been described by way of a preferred embodiment, and is not intended to limit the present invention. Also, as will be apparent to those skilled in semiconductor technology, any of them is capable of moderate and minute changes and adjustments, thereby not losing the technical idea of the present invention. Again, it must be included in the scope of the technical concept of the present invention.

[0021]

According to the present invention, a shallow groove and a deep groove with a step are formed on a dielectric film, and the shallow groove and the deep groove with a step are filled with a metal film. To achieve effective step coverage and to form a metal wiring inside a shallow groove and form a metal plug inside a deep groove with a step, to apply it to mass production of multilayer wiring integrated circuits. So you can
It has extremely high industrial utility value.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a first metal wiring formed in an embodiment of the present invention.

FIG. 2 is a sectional view showing two dielectric films formed in the embodiment of the present invention.

FIG. 3 is a sectional view showing a first photoresist pattern formed in the embodiment of the present invention.

FIG. 4 is a cross-sectional view showing an etching step in the embodiment of the present invention.

FIG. 5 is a cross-sectional view showing an etching step in the embodiment of the present invention.

FIG. 6 is a cross-sectional view showing the removal of the first photoresist pattern in the embodiment of the present invention.

FIG. 7 is a sectional view showing a second photoresist pattern formed according to the present invention.

FIG. 8 is a cross-sectional view showing an etching step in the embodiment of the present invention.

FIG. 9 shows a second dielectric film and a second dielectric film according to the embodiment of the present invention.
It is sectional drawing which shows removal with a photoresist pattern.

FIG. 10 is a sectional view showing a metal film formed in the embodiment of the present invention.

FIG. 11 is a cross-sectional view showing a state where a metal film etching step in the present invention is completed.

[Explanation of symbols]

 Reference Signs List 20 P-type silicon semiconductor wafer 22 Insulating film 24 First metal wiring 26 First dielectric film 28 Second dielectric film 30 First photoresist pattern 31 First shallow groove 34 Second photoresist pattern 35 First deep groove 38 Metal Film 38A Second metal wiring 38B First metal plug

Claims (10)

[Claims] A step of forming a first dielectric film on a surface of a silicon semiconductor wafer and providing a first conductive material on a surface of the silicon semiconductor wafer; a step of forming a second dielectric film; A resist pattern is formed, and using the first resist pattern as an etch mask, a predetermined thickness of the first dielectric film and the second
Forming a shallow groove in the surface of the first dielectric film by etching out the dielectric film; etching out a portion of the first resist pattern from a side to expose a portion of the second dielectric film; Etching the second dielectric film exposed by etching and stopping the etching at the surface of the first dielectric film; removing the first resist pattern; and forming the second resist pattern by lithography. Forming
Covering a part of the shallow groove and a part of the second dielectric film and exposing another part of the shallow groove and another part of the second dielectric film; Using the exposed portion as an etch mask, the exposed portion of the first dielectric film is etched out by etching, and the etching is stopped by a first conductive material under the first dielectric film, so that the shallow groove is deepened. Forming a metal film; forming a shallow groove and a deep groove on a surface of the first dielectric film by removing the second resist pattern and the second dielectric film; Filling the shallow groove and the deep groove with a metal film; and removing the metal film in a region other than the shallow groove and the deep groove to form an inside of the shallow groove. Forming a first metal wiring inside the deep groove, and electrically connecting the first metal plug to the first conductive material through the deep groove. A method for forming a multilayer wiring of an integrated circuit. 2. A step of forming a first dielectric film on a surface of a silicon semiconductor wafer, providing a gate oxide film, a gate electrode, and a source / drain on the surface of the silicon semiconductor wafer; and forming a second dielectric film. Forming a first resist pattern by lithography; using the first resist pattern as an etch mask;
Forming a shallow groove in the surface of the first dielectric film by etching out the dielectric film; etching out a portion of the first resist pattern from a side to expose a portion of the second dielectric film; Etching out the second dielectric film exposed by the etching and stopping the etching at the surface of the first dielectric film; removing the first resist pattern; forming a second resist pattern by lithography Covering a part of the shallow groove and a part of the second dielectric film, and exposing another part of the shallow groove and another part of the second dielectric film; and forming the second resist pattern and the second dielectric film. The exposed portion of the first dielectric film is etched by using the exposed portion of the film as an etch mask. Etching out and stopping the etching at the gate electrode under the first dielectric film to make the shallow groove a contact hole; and removing the second resist pattern and the second dielectric film. Forming the shallow groove and the contact hole on the surface of the first dielectric film; forming a metal film and filling the shallow groove and the contact hole with the metal film; The first metal wiring is formed inside the shallow groove by removing the metal film in a region other than the above, a first metal plug is formed inside the contact hole, and the first metal plug is inserted through the contact hole. Electrically connecting the gate electrode and the source / drain to the gate electrode and the source / drain. Multilayer wiring formation method of. 3. A step of forming a first dielectric film on a surface of a silicon semiconductor wafer and providing a first metal wiring on a surface of the silicon semiconductor wafer; a step of forming a second dielectric film; A resist pattern is formed, and using the first resist pattern as an etch mask, a predetermined thickness of the first dielectric film and the second
Forming a shallow groove in the surface of the first dielectric film by etching out the dielectric film; etching out a portion of the first resist pattern from a side to expose a portion of the second dielectric film; Etching out the second dielectric film exposed by the etching and stopping the etching at the surface of the first dielectric film; removing the first resist pattern; forming a second resist pattern by lithography Covering a portion of the shallow groove and a portion of the second dielectric film; exposing the first dielectric film by etching using the second resist pattern and the exposed portion of the second dielectric film as an etch mask; The etched portion is etched out, and the etching is performed on the lower layer of the first dielectric film. Stopping at the first metal wiring to form the shallow groove as a through hole; removing the second resist pattern and the second dielectric film to form the shallow groove and the through hole on the surface of the first dielectric film. Forming a hole; forming a second metal film and filling the shallow groove and the through hole with the second metal film; removing the second metal film in a region other than the shallow groove and the through hole Forming a second metal wiring inside the shallow groove, forming a first metal plug inside the contact hole, and electrically connecting the first metal plug to the first metal wiring via the through hole. Forming a multilayer wiring of an integrated circuit. 4. The silicon semiconductor wafer according to claim 1, wherein the silicon semiconductor wafer includes a field oxide film, a metal oxide semiconductor field effect transistor, a capacitor, an electric resistance, and a conductive material. 2. The method for forming a multilayer wiring of an integrated circuit according to claim 1. 5. The method according to claim 4, wherein the metal oxide semiconductor field effect transistor includes a gate oxide film, a gate electrode, and a source / drain. 6. The method according to claim 1, wherein the first dielectric film is made of two or more types of dielectric films.
12. The method for forming a multilayer wiring of an integrated circuit according to the above item. 7. The semiconductor device according to claim 1, wherein said second dielectric film is silicon nitride formed by a plasma enhanced chemical vapor deposition method, and has a thickness between 500 ° and 2000 °. 4. The method for forming a multilayer wiring of an integrated circuit according to claim 3. 8. The integrated circuit according to claim 1, wherein said second dielectric film is amorphous silicon formed by a plasma enhanced chemical vapor deposition method. Multi-layer wiring forming method. 9. The method according to claim 1, wherein the metal film is formed by a chemical vapor deposition method. 10. The removal of the metal film in a region other than the shallow groove and the deep groove is performed by performing anisotropic etch-back of the metal film by plasma etching or performing chemical mechanical polishing. 4. The method according to claim 1, wherein the method is performed.