JP2573621B2 - Method of manufacturing electrical interconnect - Google Patents

Abstract

A planar electrical interconnection system suitable for an integrated circuit is created by a process in which an insulating layer (31) having a planar upper surface is formed on a substructure after which openings (32) are etched through the insulating layer. A conductive planarizing layer (33) having a planar upper surface is formed on the insulating layer and in the openings by an operation involving isotropic deposition of a material, preferably tungsten, to create at least a portion of the planarizing layer extending from its upper surface partway into the openings. The planarizing layer is then etched down to the insulating layer. Consequently, its upper surface is coplanar with that of the material (33') in the openings. The foregoing steps are repeated to create another coplanar conductive/insulating layer (34 and 36'). If the lower openings are vias while the upper openings are grooves, the result is a planar interconnect level. Further planar interconnect levels can be formed in the same way.

Description

Description: TECHNICAL FIELD The present invention relates to a method of manufacturing an electrical interconnect particularly suitable for a semiconductor device.

BACKGROUND OF THE INVENTION Most of the electrical interconnects used in semiconductor integrated circuits are non-planar. The degree of this non-planarity increases as the number of interconnect planes increases. One disadvantage of non-planar devices is that defective step coverage of the metal can result in unwanted open circuits. Similarly, a weak portion of the insulator step coverage can cause a short circuit between different interconnect planes. Photolithography and etching severely limit the density of electronic devices because it is difficult to make thin conductive lines on rough surfaces. Planar interconnects largely solve these problems. There is a strong need for a relatively easy method for making planar connections.

GB 1,286,737 discloses a method for manufacturing planar polyhedral interconnects. Referring to FIG. 1, the starting material in GB 1,286,737 is a semiconductor body 10 adjacent to an insulating layer 11 having a planar top surface. Etch a set of openings through layer 11. A metal layer is deposited on the insulating layer 11 so as to fill the opening. The metal layer is then etched so that metal fills the opening but does not extend outside. Reference numeral 12 indicates one of the parts of the residual metal.

Another insulating layer 13 having a planar upper surface is deposited on the coplanar layer formed by the insulator 11 and the metal part 12. The openings are selectively etched through layer 13. Deposit and etch the metal layer in the same manner as the metal layer described above. The portion of the residual metal indicated by reference numeral 14 is flush with the insulating layer. These steps are repeated to form a third planar layer composed of the insulating layer 15 and the metal portion 16, and then the insulating layer 17
And a fourth planar layer comprising a metal portion 18.

The metal-filled openings in layers 11, 13, 15 and 17 are either roads or grooves. In this specification,
"Road" means a hole (including the contact opening) of approximately the same length and width. A "groove" is one whose length is much larger than its width. For example, if each opening in layer 11 is a road and each opening in layer 13 is a groove, then metal portion 12
And 14 form a first interconnect surface. Similarly, metal portions 16 and 18 form a second interconnect surface.

The interconnection of FIG. 1 is of great interest. However, in British Patent 1,286,737, the composite metal /
The details of the metal deposition / etch step to planarize each of the insulating layers are not disclosed.

Rothman's paper, "Methods for Forming Metal Interconnects with Planar Surfaces" (Process For Forming Meta
l Interconnection System with a Plnar Surface)
(J. Elec Chemical Society (J. Elec
trochemical Soc.) 「SOLID-STATE SCI. & TEC」
H.), May 1983, pp. 1131-1136) describes a lift-off method for depositing an aluminum alloy in a cavity in an insulating layer to produce a composite layer having a planar upper surface. I have. Although this lift-off method offers relatively good planarity, it requires many complex and difficult processing steps. This limits the usefulness of this method.

Low pressure chemical vapor deposition (LPCVD) of aluminum is an interesting technology. Levy et al., "Properties of LPCVD Aluminum for VLSI Processing" (J. Electrochemical Society, Solid State Science and Technology, September 1984, 2175-
2182), an aluminum layer was formed on a dielectric having a rough surface using LPCVD aluminum from a triisobutylaluminum source. The upper surface of this aluminum layer was almost planar. One disadvantage of this method is that triisobutylaluminum requires extremely careful handling.

Aluminum is a widely used metal in interconnects. However, the electromigration resistance of aluminum in pure form or when alloyed with small amounts of copper and / or silicon is relatively low. Aluminum also readily interdiffuses with silicon. The resulting silicon /
Undesirably fast device failure occurs due to the deterioration of the aluminum joint. Pure aluminum or ordinary aluminum alloys are not considered to be able to meet the required performance for future severe applications.

A promising material for interconnects is tungsten, which has much better electromigration resistance than aluminum. Tungsten has a relatively low resistivity, a high reaction temperature with silicon, a high activation energy, and a high melting point. Tungsten also acts as a diffusion barrier to silicon and can be easily etched with wet chemicals or plasma.

A common method of depositing tungsten is by LPCVD, which provides tungsten by hydrogen reduction of tungsten hexafluoride. This deposition is highly selective, with tungsten agglomerating on certain conductors and semiconductors prior to the insulator. This is described in a paper by Broadbent et al., "Selective Low Pressure Chemical Vapor Deposition of Tungsten".
r Deposition of Tungsten (J-Electro Chemical Society, Solid State Science and Technology, June 1984, 1427-14)
See page 33). Also, Saraswa
t) et al., "Selective CVD of Tungsten for VLSI Techno"
Minutes of the 2nd International Symposium (Procs.2nd In)
t′l Symp.) VLSI Science and Technology,
84-7, 1984, pp. 409-419).

Smith's paper, "CVD Tungsten Contact Plugs by In-Situ Deposition and Etching" (CVD Tungsten
Contact Plugs by In Situ Deposition and elchbac
k) (Proceedings of the 2nd International IEEEVLSI Polyhedral Interconnection Conference (P
rocs.2nd Int′l IEEE VLSI Multilev.Intercon.Con
f.), June 25-26, 1985, pages 350-356) describes the use of non-selective deposited tungsten for road filling. 2a to 2c show the processing steps. Referring to FIG. 2a, the process started with a single crystal silicon substrate 20 adjacent to a layer 21 of silicon dioxide having a planar top surface. A path 22 having substantially vertical sidewalls was etched through layer 21. The aspect ratio (ie, the width (or diameter) of the road divided by the depth of the road) varied from 1.2 to 0.3.

A thin layer 23 of tungsten silicide was deposited on the structure to increase the adhesion while avoiding the selective deposition properties of tungsten. A much thicker layer 24 of tungsten containing a small amount of silicon was deposited on layer 23. All of the above depositions were performed using a vapor consisting of WF ₆ , H ₂ and SiH _4.
Performed by PCVD, the ratio of tungsten to silicon in each of the layers 23 and 24 was controlled by adjusting the flow rate of WF _6. The upper surface of layer 24 was substantially planar as shown in FIG. 2b. However, gaps 25 occurred in layer 24 at the location of road 22 for all aspect ratios considered.
It is considered that the gap 25 was formed because the hydrogen reduced tungsten hexafluoride by silane (SiH ₄ ) in the vapor region far away from the deposition surface. Because of this, the more shadowed areas in road 22 accumulated at a lower rate.

Perform plasma etching, and as shown in FIG. 2c,
The material of the layers 23 and 24 is removed up to the upper surface of the insulator 21. Reference numerals 23 'and 24' indicate the remainder of layers 23 and 24, respectively. The gap opened to form a slot 25 'at the top of the W portion 24'. The presence of the slot 25 'is undesirable because of the difficulty in providing a step coating over the slot 25'.

SUMMARY OF THE INVENTION The present invention uses a highly planar electrical interconnect structure using an isotropic deposition of a conductive material such as tungsten when filling openings in an insulating material. It seeks to provide a way to build the body. By "isotropic deposition" is meant that the deposited material accumulates at substantially the same rate on the deposition surface, regardless of its orientation and position. The interconnect openings in this structure generally have substantially vertical sidewalls,
It is extremely thin, for example, having a width or diameter of 1 micron or less. Since the deposition is isotropic,
The conductive material in the opening can be generally said to have no gap. This is true even when the aspect ratio is much smaller than 1, for example, 0.3. Since this interconnect structure is planar, it is particularly suitable for high density semiconductor devices.

(Means for Solving the Problems) According to the present invention, a first electrically insulating layer having a substantially planar upper surface is formed on a base, and a first opening is formed in the base through the first insulating layer. In a method of etching down to produce an electrical interconnect, a relatively thin layer of Ti is deposited by sputtering, and then a relatively thin layer of W or Mo,
A relatively thin layer of the same W or Mo and the deposited layer before, SiH ₄
An operation of depositing by reducing WF ₆ or MoF ₆ in a low-pressure H ₂ atmosphere having no surface, a first conductive planarizing layer having a substantially planar upper surface is formed on the first insulating layer and the first conductive layer. Forming a relatively uniform thickness of the first planarization layer up to the upper surface of the first insulating layer; and forming a second surface having a substantially planar upper surface. Forming an electrical insulating layer on the first insulating layer and on the material in the first opening; and forming a second insulating layer through the second insulating layer up to the material in the first opening. A second conductive planarizing layer having a substantially planar top surface by etching the opening of the second planarizing layer and depositing the same steps as used for depositing the first planarizing layer. Forming on the second insulating layer and in the second opening; And removing the selected material of the planarizing layer, with it, characterized in that a step of leaving the remainder of the second planarizing layer in the desired pattern.

(Embodiment) Hereinafter, an embodiment of the present invention will be described with reference to the drawings. For simplicity of illustration, FIGS. 4 and 6 are not cross-sectional views, but are hatched. Used.

In the drawings and the description of the embodiments, the same reference numerals are used to indicate the same or similar members.

3a to 3n illustrate the steps for making a dihedral, substantially planar electrical interconnect for a semiconductor device. For purposes of explanation, a surface having a roughness not exceeding 0.2 microns is referred to as "substantially planar." However, this is not a limitation of the present invention. Hereinafter, in the description of the manufacturing, that a plane (or another member) is “planar” means “substantially in a plane”.

A photoresist mask (not shown) is formed according to a usual photolithography method. An opening, which is a road or groove, is made of silicon dioxide by creating a properly patterned photoresist mask on the oxide layer and then etching with a plasma based on a fluorine-containing gas such as Freon®. Make through layers. For simplicity, the description of the cleaning process and other such standard operations will be omitted.

The aspect ratio for an opening through a layer of a material is
The minimum lateral dimension of the opening at one half of its depth divided by its depth. The above limitation of "at one half of its depth" is eliminated if the opening has substantially vertical side walls. For grooves having vertical sidewalls, the width is the smallest lateral dimension, so the aspect ratio is the width of the groove divided by the depth. Similarly, the aspect ratio for a circular path with vertical sidewalls will be the diameter of the path divided by the depth because the width of the path is direct to a circular path.

The starting material is a P-type or N-type single crystal silicon semiconductor substrate or a wafer formed with a body 30 of such a substrate on which an epitaxial layer has been grown. Various N-type and P-type regions are in the single crystal silicon. Body 30 also includes a doped polysilicon interconnect layer that selectively contacts the substrate or epitaxial layer through a path in the silicon dioxide layer. Details of the body 30 are not shown in the drawing. However, its top surface is generally non-planar, for example, as shown by the step shown at the top of body 30 in FIG. 3a.

First insulating layer of silicon dioxide having a planar top surface
31 is formed along the upper surface of the main body 30. This is generally
Silicon dioxide is deposited on the body 30, a layer of exposed photoresist is formed on this oxide, the photoresist is flowed so that its top surface is planar, and then the photoresist and silicon dioxide are substantially at the same speed. This is done by removing the photoresist layer with plasma that is etched in step (1). The etching removes a step along the top of the deposited oxide, thereby creating layer 31.

A set of generally circular paths 32 having a diameter of about 1 micron is etched through layer 31 and the body is etched as shown in FIG. 3b.
Let go down to 30. The path 32 extends to different depths due to the steps along the top of the body 30. The depth of this road is
For example, it varies from 0.4 microns to 2 microns. The side walls of the road 32 are substantially vertical. To elaborate,
The angle β between the side wall of each path 32 and the top surface of layer 31 is slightly greater than 90 °, typically about 95 °. Therefore, the aspect ratio of this path varies from about 2.5 to 0.5. FIG. 4 is a top view of FIG. 3b.

A first conductive planarization layer 33 is formed on the oxide layer 31 such that the layer 33 has a planar upper surface (see FIG. 3c). layer
33 is made by an operation involving isotropic LPCVD of tungsten by hydrogen reduction of tungsten hexafluoride. 5a
Figures to 5e illustrate a preferred method for performing this operation.

As described above, LPCVD tungsten supplied from WF ₆ aggregates (accumulates) on silicon and metal prior to silicon dioxide. It must be ensured that selective deposition characteristics do not occur before tungsten LPCVD becomes isotropic. This is achieved by first depositing a thin conductive anchoring layer. That is, the pinned layer acts as a uniform agglomeration source for tungsten and simultaneously deposits on the oxide in layer 31 and the silicon at the bottom of path 32. The thickness of the anchoring layer is much smaller than the diameter of the path 32. Due to β, the ratio of the diameter of the road to the thickness of the anchoring layer is usually at least 5, typically around 25.

The pinned layer preferably comprises a pair of layers 33A and 33B. Referring to FIG. 5a, 200 Angstroms of titanium is deposited on layer 31 and on track 3 by conventional sputtering at room temperature in a 0.003 torr argon atmosphere.
Deposited in 2 to form layer 33A. Titanium adheres well to silicon and silicon dioxide. Since sputtering is an anisotropic physical deposition method, the thickness of the titanium layer 33A varies slightly from location to location. Layer 33A is typically thinner in the hatched areas. This is not a particularly serious problem unless there is a significant break in this layer.

Titanium does not provide a good agglomerated surface for LPCVD tungsten because the fluorine in WF ₆ reacts with titanium to form TiF ₃ with high resistivity. So, under the above conditions, about 20
Sputter-deposit 0 Å of tungsten on layer 33A to form layer 33B as shown in FIG. 5b. Layer 33B
The tungsten inside adheres well to titanium and, needless to say, acts as an excellent agglomeration surface for LPCVD tungsten. As in layer 33A, some portions of W layer 33B are thinner than others. This is also a layer
As long as 33B is continuous, it is not a particularly serious problem.

Then, by reducing WF ₆ with a low pressure in a H ₂ atmosphere to form the tungsten layer 33C on the layer 33B. LPCVD
To begin operation, place a wafer having the structure of FIG. 5b into a suitable deposition reactor, reduce the pressure in the reactor,
Then, the wafer is heated to a temperature in the range of 300 ° C. to 500 ° C. The temperature of the wafer (or deposition) is preferably 425 ° C. During the above temperature rise, the reactor
Purge with ₂ or inert gas. Once the desired temperature has been reached, the purge is terminated and the reactor is typically run at 0.
Adjust pressure to less than 05 Torr.

A metered amount of WF ₆ and H ₂ is introduced into the reactor (especially avoiding SiH ₄ ). The flow rate of WF ₆ should not exceed 1,000 standard cm ³ / min (SCCM), preferably 2,000 SCCM. The flow rate of H ₂ is
Should not exceed 8,000 SCCM, 1,500 SCCM is preferred.
Control the pressure of the reactor during W deposition to 1 Torr or less. At this pressure, a consistent molecular flow occurs. Preferably, the deposition pressure is between 0.5 and 0.6 torr.

 Tungsten deposition proceeds according to the following reaction equation:

WF ₆ + 3H ₂ → W + 6HF This reaction is surface-controlled under the conditions described above. That is,
Tungsten is released at or near the surface, where it accumulates to form layer 33C. WF ₆ / H _{2 at a} location far from the above deposition surface
It is believed that very little, if any, tungsten hexafluoride is reduced in the vapor. The WF ₆ / H ₂ vapor is evenly distributed along the plane of the wafer. Also, the temperature is about the same over the entire wafer. Thus, tungsten accumulates on the deposited surface at approximately the same rate, regardless of its orientation. The deposit is isotropic.

At the preferred flow rates, temperatures and pressures, tungsten is deposited at a rate of 500-600 Å / min.
The deposition time is preferably 30 minutes. This gives approximately 1.5
An "equivalent" W thickness in microns is obtained.

Figures 5c to 5e illustrate how layer 33C is made. Since the deposition is isotropic and the sidewall angle β is slightly greater than 90 °, the sidewalls of each lower region in the path 32 approach each other in a uniform manner from the bottom up. The equivalent W thickness is 2 of the road diameter (1.0 micron)
When equal to the "contact" value, which is slightly less than a factor of one, the sidewalls of each low region just join each other. In this case,
The equivalent W thickness is about three times the contact value. Thus, the sidewalls of each low area are completely closed without gaps, thereby
33C has a planar upper surface as shown in FIG. 5e. Layers 33A, 33B and 33C of FIG. 5e correspond to planarization layer 3 of FIG. 3c.
Form 3.

After removing the structure from the deposition reactor, the structure is etched with a suitable plasma to remove the relatively uniform thickness of layer 33 down to the top surface of oxide layer 31. This involves removal of the portion of layer 33A lying on top of layer 31. Excess tungsten is etched using a fluorine-containing plasma. Excess titanium is removed by chlorine-based plasma. Either plasma can use oxygen. This etching can proceed hundreds of Angstroms below the top surface of layer 31 without significantly affecting the planarity of the structure from a practical point of view. Tier 33
The upper surface of the remaining portion 33 'is flush with the upper surface of the layer 31, as shown in FIG. 3d.

In some cases, layer 33 in FIG. 3c may have a non-negligible roughness due to the crystallization characteristics of the tungsten grains. Section 33 'typically has this roughness. The roughness can be significantly reduced by first providing layer 33 with a thin layer of photoresist having a top surface that is flatter than the top surface of the layer. The photoresist layer and the portion of the layer 33 projecting upwards are removed by etching with tungsten and an etchant which attacks the photoresist at approximately the same rate. If the etchant is the fluorine-based plasma described above, layers 33B and 33C and the photoresist layer can be etched in a single step. The layer 33A is then etched as described above to obtain the structure shown in FIG. 3d.

Silicon dioxide is deposited on layer 31 and metal portion 33 'in a conventional manner to form a second insulating layer 34 having a planar upper surface (see FIG. 3e). The thickness of the oxide layer 34 is 1.5 to 2.0
Micron.

As shown in FIG. 3f, the pattern of grooves 35 corresponding to the desired conductor pattern for the first
Etch through layer 34 to 3 '. The side wall of the groove 35 is substantially vertical, and the side wall angle β is about 95 °. The width of this groove is 1.5-2.0 microns. The depth of the groove 35 is 1.5 to 2.0
Being microns, the aspect ratio of this groove varies from about 1.0 to 0.5. In FIG. 3f, the left hand groove 35 is shown along its length, and the right hand groove 35 is shown along its width. FIG. 6 is a top view of FIG. 3f.

As shown in FIG. 3g, a second conductive planarizing layer 36 is layered.
Formed on 34. Layer 36 is preferably made in exactly the same way as layer 33. Specifically, a 200 Å sputtered titanium followed by a 200 Å sputtered tungsten underlayer is deposited on layer 34 and in trench 35. The upper layer is formed by isotropically depositing tungsten of an equivalent thickness of about 1.5 microns on the lower layer. As the tungsten is deposited, the sidewalls of each lower region in groove 35 close in a uniform manner from the bottom up. Since the equivalent W thickness is at least twice the contact value, the sidewalls of the lower region are closed without gaps, creating a planar top surface for layer 36.

The plasma used to etch layer 33 is used to remove the relatively uniform thickness of layer 36 down to the upper surface of layer 34. Again, the etching proceeds slightly below the top surface of layer 34 without significantly compromising the planarity of the structure. Metal portions 33 'and 36' together with oxide layers 31 and 34 form a planar interconnect surface.

Next, the above steps are repeated to create another planar interconnect surface as shown in FIGS. 3i to 3n. Next, the process will be described briefly.

A third electrically insulating layer 37 is deposited to a thickness of 0.7-1.5 microns and then selectively etched to form a path 38 having a diameter of about 1 micron. A third conductive planarization layer 39 having a planar upper surface is formed on layer 33 in the manner described above. The relatively uniform thickness of layer 39 is removed down to the top surface of layer 37 to create the structure shown in FIG. 3k.

A fourth electrically insulating layer 40 is deposited and then selectively etched to form a pattern of grooves 41 corresponding to the desired conductor pattern for the second interconnect surface. Groove 41 is groove
It has the same depth and width as 35. Fourth conductive planarization layer 42
Is made in the same manner as layer 36 to have a planar top surface. Tier 42
Is etched away down to the upper surface of layer 40. Along with the insulating layers 37 and 40, the respective metal remnants 39 'and 42' of the layers 39 and 42, as shown in FIG.
To form an interconnect plane.

Thus, the steps of FIGS. 3a to 3n result in a planar dihedral interconnect without gaps. Still other planar surfaces can be added in the same manner.

In some applications, planarizing the top interconnect plane does not significantly increase device density. The upper interconnect surface may be non-planar if the number of steps can be reduced.

For example, instead of the method described above, the structure of FIG.
The processing may be performed by the method shown in FIG. That is, the layer 39 is selectively etched using an appropriate photoresist mask,
Form the desired pattern for the second interconnect plane.
The etching can be performed with a wet chemical or with the plasma used to etch layer 33. The conductive residue 39 "on top of the layer 39 lies completely over the conductive residue 39 'in the path 38.

As another example, the structure shown in FIG. 3k can be completed using the steps shown in FIGS. 8a and 8b. A blanket layer 43 of a conductor such as aluminum is deposited over layer 37 and metal portion 39 '(see FIG. 8a). Unwanted portions of layer 43 are etched away using a suitable photoresist master. The conductive remainder 43 'of layer 43 constitutes the upper half of the second interconnect surface as shown in FIG. 8b.

Tungsten is particularly suitable for use in the present invention because of its excellent electromigration resistance. Many studies have been performed in the past to demonstrate the features of tungsten for semiconductor applications. However, other conductive materials can be used in the present invention as long as they can be deposited isotropically. One of them is molybdenum. Molybdenum, a tungsten congener, has similar properties. Molybdenum is available as gaseous MoF ₆ .

Although the present invention has been described with reference to the embodiments, the description is for the purpose of illustration only and does not limit the scope of the present invention. For example, an experimental structure having a gapless metal-filled groove having a width of 0.75 microns and an aspect ratio of 0.3 was made. The bottom composite conductive / insulating layer formed according to the present invention may have grooves rather than roads.

Accordingly, various modifications, changes and adaptations may be made without departing from the true scope and spirit of the invention as set forth in the appended claims.

[Brief description of the drawings]

FIG. 1 is a longitudinal sectional view showing the structure of a conventional interconnect, and FIG.
Figures, 2b and 2c are longitudinal sectional views showing steps in a conventional method for depositing tungsten in a road,
3a, 3b, 3c, 3d, 3e, 3f, 3g
Figures 3h, 3i, 3j, 3k, 3l, 3m, and 3n are longitudinal sectional views showing various steps in fabricating an interconnect device in accordance with the present invention. FIG. 4 shows the plane 3b-3b in FIG.
5a, 5b, top view of the structure drawn along
FIGS. 5c, 5d and 5e show the structure of FIG.
Fig. 3c is a longitudinal sectional view showing various steps leading to the structure shown in Fig. 3c.
FIG. 3f is a top view of the structure, taken along plane 3r-3f, FIG. 7 is a top view showing another method of finishing the structure of FIG. 3j, FIGS. 8a and 8b are FIG. 31 is a longitudinal sectional view showing other steps for finishing the structure of FIG. 3k. 30 ... body, 31,34,37,40 ... insulating layer, 32,38 ... road, 33,36,93,42 ... planarization layer, 35,41 ... groove, 43 ... blanket layer.

Claims (2)

(57) [Claims] An electrical interconnect is formed by forming a first electrically insulating layer having a substantially planar upper surface on a substrate and etching a first opening through the first insulating layer to the substrate. In a method of manufacturing a part, a relatively thin layer of Ti is deposited by sputtering,
Next, a relatively thin layer of W or Mo is deposited, and then the same relatively thin layer of W or Mo as previously deposited is reduced to WF ₆ or MoF ₆ in a low pressure H ₂ atmosphere without SiH _4. By doing
By depositing, a first conductive planarizing layer having a substantially planar upper surface is deposited on the first insulating layer and the first conductive planarizing layer.
Forming a relatively uniform thickness of the first planarization layer up to the upper surface of the first insulating layer; and forming a second surface having a substantially planar upper surface. The first electrically insulating layer
Forming on the insulating layer and on the material in the first opening; and etching the second opening through the second insulating layer to the material in the first opening. Depositing a second conductive planarizing layer having a substantially planar top surface on the second insulating layer and the second insulating layer by a deposition step similar to the steps used to deposit the first planarization layer. Forming in the second opening; and removing a selected material of the second planarization layer, thereby leaving the remainder of the second planarization layer in a desired pattern. A method of manufacturing an electrical interconnect characterized by: 2. The method of claim 1, wherein the step of removing the selected material involves removing a relatively uniform thickness of the second planarization layer down to an upper surface of the second insulating layer. The method for manufacturing an electrical interconnect according to claim 1, wherein: