JP2005038999A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device which can improve the reliability of one conductive layer by suppressing an increase in resistance value of the other conductive layer finer than the first one when simultaneously forming the plurality of conductive layers. <P>SOLUTION: An insulation film 30 is formed on a substrate 10, and a plurality of concave portions which are grooves 31 and 32 that will become conductive layer formation regions are formed in the insulation film 30, and then a first conductive layer 40 and a second conductive layer 50 are so formed as to fill in the grooves 31 and 32 formed in the insulation film 30. The grooves 31 and 32 are so formed that the second conductive layer 50 may be finer than the first conductive layer 40, and that the concentration of an additive having a migration suppressing function which is contained in the first conductive layer 40 is higher than the concentration of an additive in the second conductive layer 50. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having a buried (damascene) structure.
[0002]
[Prior art]
Along with the high integration of LSIs, the miniaturization of internal wiring has progressed, and the demand for lower resistance and improved reliability of the fine wiring has increased. Therefore, copper having a low resistance value is used instead of aluminum or aluminum alloy which has been widely used as a wiring material.
[0003]
Furthermore, in order to improve the reliability of copper wiring, it has been studied to form wiring by adding silver, aluminum or the like into copper. By including the additive, the atomic flow can be suppressed, thereby improving the electromigration resistance. In addition, it is possible to suppress defects due to stress migration occurring in wide wiring.
[0004]
FIG. 7 is a schematic cross-sectional view schematically showing a part of a conventional semiconductor device. A lower copper wiring cap layer 120 is formed on the substrate 110, an insulating film 130 is formed on the cap layer 120, and grooves 131 and 132 (hereinafter referred to as grooves) that are predetermined recesses are formed on the upper surface of the insulating film 130. Is formed. Here, there are at least two predetermined grooves 131 and 132, and the other groove 132 is formed to be finer than one groove 131. A barrier metal 133 is formed so as to cover the insulating film 130 in which the grooves 131 and 132 are formed.
A first conductive layer 140 is formed so as to fill one groove 131, and a second conductive layer 150 is formed so as to fill the other groove 132. Here, the cap layer 120 may not be formed depending on the layer structure and the material of the conductive layer used for the lower layer. The barrier metal 133 between the insulating film 130 and the first and second conductive layers 140 and 150 may not be formed according to the material of the conductive layer.
[0005]
FIG. 8 is a schematic cross-sectional view that sequentially schematically shows one example of a conventional method for manufacturing a semiconductor device.
First, as shown in FIG. 8A, a lower copper wiring cap layer 120 is formed on the upper surface of the substrate 110, and an insulating film 130 is formed on the upper surface of the cap layer 120. Next, a plurality of grooves 131 and 132 are formed in the insulating film 130. At this time, the other groove 132 is formed to be finer than the one groove 131.
Next, a barrier metal 133 is formed so as to cover the insulating film 130 as necessary. Thereafter, a seed layer 135 is formed on the upper surface of the barrier metal 133. The seed layer 135 forms, for example, a copper layer containing silver as an additive by using an ionized sputtering method with a copper-silver alloy target.
[0006]
Next, as shown in FIG. 8B, a copper buried film 136 serving as a conductive layer is formed on the insulating film 130 covered with the barrier metal 133 and the seed layer 135. The buried film 136 is formed by, for example, a plating method. At this time, in a fine groove such as the other groove 132, a plating solution is used so that the growth from the bottom side is faster than the growth from the side wall in order to prevent voids in the conductive layer region. Form. Further, the buried film 136 is formed in such a thickness that the surface is not exposed when at least the grooves 131 and 132 are completely buried and polished in a later process.
Next, as shown in FIG. 8C, the buried film 136 is polished until the interlayer insulating film 130 is exposed, and then heat treatment is performed. At this time, the additive contained in the seed layer 135 is diffused by heat treatment. As a result, as shown in FIG. 7, the first and second conductive layers 140 and 150 containing the additive are formed.
[0007]
FIG. 9 is a schematic cross-sectional view that sequentially schematically shows another example of the manufacturing method for the conventional semiconductor device.
First, as shown in FIG. 9A, the insulating film 130 is formed as in FIG. 8A, and a plurality of grooves 131 and 132 are formed on the upper surface of the insulating film 130. At this time, one groove 131 is formed to be wider than the other groove 132. Next, a barrier metal 133 is formed so as to cover the insulating film 130. Thereafter, a seed layer is formed on the upper surface of the barrier metal 133, and further, a first embedded film 136 made of copper is formed by plating or the like. Similar to the above example, the first buried film 136 is formed in such a thickness that the surface is not exposed when at least the grooves 131 and 132 are completely buried and polished in a later process.
[0008]
Next, as shown in FIG. 9B, a second buried film 137 made of copper containing silver as an additive is formed on the upper surface of the first buried film 136.
Next, as shown in FIG. 9C, heat treatment is performed to uniformly diffuse the additive contained in the second buried film 137 into the first buried film 136.
Thereafter, the buried films 136 and 137 are polished until the insulating film 130 is exposed. As a result, as shown in FIG. 7, first and second conductive layers 140 and 150 containing the additive are formed.
[0009]
As described above, as a conventional method for manufacturing a semiconductor device, copper is flown and embedded in a recess formed in an interlayer insulating film, and then an impurity material is deposited on the copper, and heat treatment is performed to remove the impurity material from the copper. A method of forming a copper alloy wiring by diffusing inside is known (for example, see Patent Document 1).
[0010]
[Patent Document 1]
JP-A-11-102909 (Page 2-6, Fig. 1-4)
[0011]
[Problems to be solved by the invention]
However, in the conventional method as described above, the resistance value of the finer second conductive layer 150 is likely to increase by containing the additive.
For example, in the former method as shown in FIG. 8, the proportion of the seed layer in the finer second conductive layer 150 is high. Therefore, the concentration of the additive in the second conductive layer 150 is higher than the concentration of the additive in the first conductive layer 140, and the resistance value is also increased. In addition, it is necessary to review the film forming process such as plating. On the other hand, in the latter method as shown in FIG. 9, it is not necessary to review the film forming process such as plating. However, the increase in the resistance value of the second conductive layer 150 finer than that of the first conductive layer 140 due to the diffusion of the additive is not as great as the former, but is unavoidable.
[0012]
The present invention has been made in view of such circumstances, and the purpose thereof is to suppress an increase in the resistance of the other conductive layer, which is finer than one conductive layer, while simultaneously forming a plurality of conductive layers, An object of the present invention is to provide a method for manufacturing a semiconductor device capable of improving the reliability of one conductive layer.
[0013]
[Means for Solving the Problems]
In order to achieve the above object, the method for manufacturing a semiconductor device according to the present invention includes a step of forming an insulating film on a substrate, a step of forming a plurality of recesses in the insulating film to form a conductive layer, Forming a first conductive layer and a second conductive layer so as to fill the recess formed in the insulating film, and the second conductive layer is finer than the first conductive layer. The concave portion is formed so as to be a conductive layer, and the concentration of the additive contained in the first conductive layer and having a migration suppressing function is higher than the concentration of the additive in the second conductive layer. Form.
[0014]
In the method of manufacturing a semiconductor device according to the present invention, an insulating film is formed on the upper surface of the substrate, a plurality of recesses that form conductive layers are formed in the insulating film, and the recesses formed in the insulating film are embedded. A first conductive layer and a second conductive layer are formed. Here, as compared with the first conductive layer, the concave portion is formed so that the second conductive layer becomes a finer conductive layer, and the concentration of the additive contained in the first conductive layer and having a function of suppressing migration Is formed higher than the concentration of the additive in the second conductive layer.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 is a plan view schematically showing the semiconductor device according to the present embodiment. A lower copper wiring cap layer 20 is formed on the substrate 10, and an insulating film 30 is formed on the cap layer 20. The insulating film 30 is formed with grooves 31 and 32 (hereinafter referred to as grooves) which are predetermined recesses. Here, there are at least two predetermined grooves 31 and 32, and the other groove 32 is formed to be finer than the one groove 31. Barrier metals 33 are formed on the side surfaces and the bottom surfaces of the grooves 31 and 32. In addition, the first conductive layer 40 is formed so as to fill one groove 31, and the second conductive layer 50 is formed so as to fill the other groove 32. Here, the cap layer 20 may not be formed according to the layer configuration and the material of the conductive layer used in the lower layer. The first and second conductive layers 40 and 50 are made of, for example, a conductive material containing copper.
[0016]
2 to 4 are schematic cross-sectional views sequentially showing main steps of the semiconductor device manufacturing method according to this embodiment.
In this embodiment, a conductive material containing copper is used as the conductive layer. In general, it is considered difficult to etch copper by reactive ion etching (RIE). Therefore, a conductive layer is formed by a damascene method in which a conductive film is embedded in the grooves 31 and 32 formed in the insulating film 30 and is flattened by a chemical-mechanical polishing (CMP) method or the like.
[0017]
First, as shown in FIG. 2A, a lower copper wiring cap layer 20 is formed on a substrate 10. As the cap layer 20 for the copper wiring, a silicon nitride film (SiN), a silicon carbide film (SiC), or the like is used. Next, an insulating film 30 to be an interlayer capacitance film and a line capacitance film is formed on the cap layer 20. As the insulating layer 30, a conventionally used silicon oxide film (SiO 2) is used to suppress an increase in inter-wiring capacitance accompanying the miniaturization of the wiring, that is, wiring delay. ₂ It is desirable that the relative dielectric constant is smaller than (). For example, siloxane-based polymers such as MSQ and HSQ (MSQ; Hydrogen Silquixane) formed by a coating method, and SiOC-based materials formed by chemical vapor deposition (CVD) method, etc. It is done.
[0018]
Next, as shown in FIG. 2B, a plurality of grooves 31 and 32 that form conductive layer formation regions are formed in the insulating film 30 using existing lithography technology, RIE technology, or the like. At this time, each of the other grooves 32 is formed to be finer than the one groove 31. For example, the width of one groove 31 is 3 μm, the width of the other groove 32 is 100 nm, and each depth is about 240 nm.
[0019]
Next, as shown in FIG. 2C, a barrier metal 33 is formed on the side and bottom surfaces of the grooves 31 and 32 for the purpose of preventing diffusion of a conductive layer to be formed later and improving adhesion. As the barrier metal, tantalum, tantalum nitride, tantalum carbide, titanium, titanium nitride, titanium tungsten, tungsten, tungsten silicate, tungsten nitride, tungsten nitride silicide, molybdenum, niobium, and a laminate thereof are used. These materials are formed by a suitable method depending on the material used, such as a CVD method or an ionized sputtering method. In the present embodiment, for example, a laminated body of tantalum nitride and tantalum is formed with a thickness of about 15 nm.
[0020]
Next, as shown in FIG. 3D, a seed film 35 is formed on the upper surface of the barrier metal 33. As the seed film 35, copper, which is the same material as the first buried film to be formed later, is formed by using, for example, ionized sputtering. The film thickness is, for example, about 60 nm.
[0021]
Next, as shown in FIG. 3E, for example, copper is embedded as the first embedded film 36 by an electrolytic plating method using a copper sulfate solution or the like using the seed film 35 as an electrode. At this time, an additive having a bottom-up property such that the growth rate from the bottom surface is higher than the growth rate from the wall surface in the plating solution in order to prevent the formation of voids in the fine grooves 32 that are difficult to fill. In addition. Therefore, a difference occurs in the filling end time depending on the line width of the grooves 31 and 32. That is, the finer groove 32 is filled faster than the wider groove 31.
The first buried film 36 is formed in such a film thickness that a part of the surface of the first buried film 36 in the wider groove 31 is positioned lower than the upper surface a of the insulating film 30. At the same time, the surface of the first buried film 36 in the finer trench 32 is formed so as to be sufficiently higher than the upper surface of the insulating film 30.
[0022]
The difference in the film thickness of the buried film according to the line width of the grooves 31 and 32 is that the plating solution having a high bottom-up property as described above is used, and the composition, concentration, temperature, electric field, etc. of the plating solution are changed. It can be formed by adjusting. For example, the minimum plating film thickness h of the first buried film in the groove 31 ₁ Is 80 nm (155 nm when combined with the barrier metal of 15 nm and the seed film of 60 nm), and the maximum depth h at which the second buried film 37 is deposited is ₂ Is about 15 nm. Further, the plating film h on the upper surface of the groove 32 at this time ₃ Is about 200 nm at the maximum.
[0023]
Next, as shown in FIG. 3F, for example, a second buried film 37 made of an additive such as silver or aluminum or an alloy thereof with copper is formed by sputtering. As the additive, a conductive material that has a function of suppressing the migration of the first buried film 36 and can be easily diffused into copper by a subsequent heat treatment is preferable. In addition to silver and aluminum, for example, tin or indium , Zirconia, and magnesium. In other words, a material capable of obtaining a diffusion rate for sufficiently dissolving in a copper film at about 300 to 400 ° C. in copper is preferable.
The second buried film 37 is formed up to a position higher than the upper surface of the insulating film 30 in the groove 31. That is, a film thickness sufficient for planarization is necessary in the subsequent removing step. In this embodiment, the additive is silver, the copper-silver alloy film is 1 wt%, and the deposited film thickness is 620 nm.
[0024]
Next, as shown in FIG. 4G, the first and second buried films 36 and 37 are removed while being planarized by CMP or the like until the insulating film 30 is exposed from above. At this time, the insulating film 30 polished by the CMP method is about 70 nm. Further, the ratio of the second buried film 37 in the groove 31 is, for example, 0.1% or less. This ratio depends on the concentration of the additive contained in the second buried film 37 and the like.
Next, as shown in FIG. 4 (h), heating is performed under the condition that the additive is sufficiently diffused in the buried film formed in the groove 31 in an inert gas atmosphere, and copper grains are grown. . The conditions at this time are, for example, an oxygen concentration of 30 ppm or less, 350 ° C., and 1 hour in an argon atmosphere, and using a hot plate, a vertical furnace, or the like. Heating can also be performed under an inert gas atmosphere other than argon, in a vacuum, a nitrogen atmosphere, or a diluted hydrogen atmosphere.
Thereby, the first conductive layer 40 and the second conductive layer 50 finer than the first conductive layer 40 can be formed. At this time, the concentration of the additive contained in the first conductive layer 40 is higher than the concentration of the additive contained in the second conductive layer 50.
[0025]
In the present embodiment, the first embedded film 36 is formed by the electrolytic plating method, but can also be formed by the electroless plating method. At this time, a solution that chemically reduces and precipitates copper is used as the plating solution.
[0026]
According to the present embodiment, when the plurality of conductive layers are simultaneously formed, the second embedded film remains only in the formation region of the first conductive layer after polishing. Therefore, the first conductive layer is formed by the subsequent heat treatment. Additives are contained only in the layer. Therefore, it can be selectively formed so that the additive concentration of the wider conductive layer is higher than the additive concentration contained in the finer conductive layer.
Therefore, the electromigration resistance and stress migration resistance of a wider conductive layer can be improved without impairing the resistance value of the fine conductive layer. As a result, the degree of freedom in circuit design, which has become more restrictive as miniaturization progresses, can be expanded, and a high-performance semiconductor device can be realized. Accordingly, the performance of computers, game machines and mobile devices can be significantly improved.
[0027]
[Modification 1]
Next, a modification of the present embodiment will be described with reference to the drawings. Here, the same parts as those in the above embodiment have the same numbers, the description thereof will be omitted, and only different parts will be described below.
In this modification, another method for manufacturing the semiconductor device according to the above embodiment will be described.
2, 3 and 5 are schematic cross-sectional views sequentially showing main steps of the method of manufacturing a semiconductor device according to this modification.
First, as in the above embodiment, a semiconductor device is formed with reference to FIGS. 2 (a) to 3 (f).
As shown in FIG. 2A, the cap layer 20 of the lower copper wiring is formed on the substrate 10, and the insulating film 30 is formed on the cap layer 20.
Next, as shown in FIG. 2B, a plurality of grooves 31 and 32 that form conductive layer formation regions are formed in the insulating film 30. At this time, each of the other grooves 32 is formed to be finer than the one groove 31. For example, the width of one groove 31 is 3 μm, the width of the other groove 32 is 100 nm, and each depth is about 240 nm.
Next, as shown in FIG. 2C, the barrier metal 33 is formed on the side surfaces and the bottom surface of the grooves 31 and 32. For example, a laminate of tantalum nitride and tantalum is formed with a thickness of about 15 nm.
[0028]
Next, as shown in FIG. 3D, a seed film 35 is formed on the upper surface of the barrier metal 33. As the seed film 35, copper, which is a main material of a conductive layer to be formed later, is formed with a film thickness of about 60 nm, for example.
Next, as shown in FIG. 3E, copper is embedded as the first embedded film 36 by an electrolytic plating method or the like. For example, the first buried film 36 is formed in such a film thickness that a part of the surface of the first buried film 36 in the wider groove 31 is lower than the upper surface a of the insulating film 30. . At the same time, the surface of the first buried film 36 in the finer trench 32 is formed so as to be sufficiently higher than the upper surface of the insulating film 30. For example, the minimum plating film thickness h of the first buried film in the groove 31 ₁ 80 nm and the maximum depth h at which the second buried film 37 is deposited ₂ Is about 15 nm. Further, the plating film h on the upper surface of the groove 32 at this time ₃ Is about 200 nm at the maximum.
Next, as shown in FIG. 3F, for example, a second buried film 37 made of an additive such as silver or aluminum or an alloy thereof with copper is formed by sputtering. The second buried film 37 is formed up to a position higher than the insulating film 30 in the trench 31. That is, a film thickness sufficient for planarization is necessary in the subsequent removing step. In this modification, the additive is silver, the copper-silver alloy film is 1 wt%, and the deposited film thickness is about 620 nm.
[0029]
Next, as shown in FIG. 5 (i), heating is performed in an inert gas atmosphere under conditions such that the additive diffuses into the first buried film 36, and copper grain growth is performed. At this time, in the fine groove 32 compared to the groove 31 and the groove 31, the height from the bottom of each groove to the boundary between the first buried film 36 and the second buried film 37 is about 200 nm. There is a difference (h in FIG. 3 (e) ₂ + H ₃ ). Therefore, in the groove 31, the additive contained in the second buried film 37 diffuses into the first buried film 36, and the additive does not reach the first buried film 36 in the finer groove 32. Heating is performed under various conditions. Alternatively, heating is performed under such a condition that the additive concentration in the buried film formed in the groove 31 is higher than the additive concentration in the buried film formed in the groove 32.
[0030]
As heating conditions, for example, an oxygen concentration of 30 ppm or less, 200 ° C., and 15 minutes is performed in an argon atmosphere, using a hot plate, a vertical furnace, or the like. Heating can also be performed under an inert gas atmosphere other than argon, in a vacuum, a nitrogen atmosphere, or a diluted hydrogen atmosphere. As a result, for example, as shown in the figure, the groove 31 is sufficiently diffused, and in the groove 32, the first buried film 36 is thick, so that the additive diffuses only to the extent indicated by the dotted line in the figure. Not.
The diffusion amount of the additive in the first buried film 36 is as follows: the thickness of the first buried film 36, the thickness of the second buried film 37, and the additive contained in the second buried film 37. The concentration can be controlled by the concentration, diffusion time, diffusion temperature, and the like. In general, the diffusion amount increases as the diffusion time is increased and the diffusion temperature is increased.
[0031]
Next, as shown in FIG. 5J, the first and second buried films 36 and 37 are removed while being planarized by CMP or the like until the insulating film 30 is exposed from above. At this time, the insulating film 30 polished by the CMP method is about 70 nm.
Thereby, the first conductive layer 40 and the second conductive layer 50 finer than the first conductive layer 40 can be formed. At this time, the concentration of the additive contained in the first conductive layer is higher than the concentration of the additive contained in the second conductive layer 50.
[0032]
In the present modification, the first buried film 36 is formed by an electrolytic plating method, but can also be formed by an electroless plating method. At this time, a solution that chemically reduces and precipitates copper is used as the plating solution. In the present modification, a part of the surface of the first buried film 36 is formed to have a thickness lower than the upper surface a of the insulating film 30, but the present invention is not limited to this. As long as the film thickness is such that it diffuses as described above.
[0033]
According to this modification, when a plurality of conductive layers are formed at the same time, they are contained in the fine second conductive layer by using the steps of the formed buried film and changing the diffusion conditions and film thickness. The first conductive layer having a wider width than the additive concentration can be selectively formed so as to have a higher additive concentration.
Therefore, it is possible to improve the electromigration resistance and stress migration resistance of a wider conductive layer without impairing the resistance value of the fine wiring. As a result, the degree of freedom in circuit design, which has become more restrictive as miniaturization progresses, can be expanded, and a high-performance semiconductor device can be realized.
[0034]
[Modification 2]
A modification of this embodiment will be described with reference to the drawings. Here, the same parts as those in the above embodiment have the same numbers, the description thereof will be omitted, and only different parts will be described below.
This modification is a method for manufacturing a semiconductor device in which an opening is formed at the bottom of the groove in the semiconductor device of the above-described embodiment and modification.
FIG. 6 is a schematic cross-sectional view schematically showing a semiconductor device according to this modification. A lower layer wiring 15 is formed on the substrate 10, and a cap layer 20 is formed on the upper surface of the substrate 10 on which the lower layer wiring 15 is formed. An insulating film 30 is formed on the upper surface of the cap layer 20, and a plurality of grooves 31 and 32 are formed in the insulating film 30. Side surfaces and bottom surfaces of the grooves 31 and 32 are covered with a barrier metal 33. In addition, the first conductive layer 40 is formed so as to fill the groove 31, and the second conductive layer 50 is formed so as to fill the groove 32. Here, an opening 16 is formed in the cap layer 20 and the insulating film 30 so that the lower layer wiring 15 is exposed at a part of the bottom of the groove 31, and the first conductive layer 40 and the lower layer wiring 15 are formed in the opening 16. It is electrically connected via.
[0035]
The opening 16 is formed at the bottom of the groove 31 by a known lithography technique or RIE technique. Further, a barrier metal 33 and a seed film 35 are formed on the side surface and the bottom surface of the groove 31 having the opening 16 and the side surface and the bottom surface of the opening 16. Thereafter, a first buried film 36 is formed so as to fill the grooves 31, 32 and the opening 16, and a second buried film 37 is formed on the first buried film 36. Subsequently, a conductive layer in which an additive is diffused in the groove 31 and the opening 16 is formed by using a method as in the embodiment or the modification.
[0036]
In this modification, the opening 16 is formed in the groove 31, but the opening 16 may be formed in a finer groove 32. At that time, a lower layer wiring electrically connected to the groove 32 through the opening 16 may be provided.
[0037]
According to this modification, the additive concentration contained in a finer conductive layer when forming a plurality of conductive layers simultaneously, as in the above-described embodiment and modification in a semiconductor device having a multilayer wiring structure The additive concentration of the wider conductive layer can be formed to be higher than that.
[0038]
The present invention is not limited to the above embodiment.
For example, in this embodiment, it can change from silver to aluminum as an additive which suppresses migration.
In addition, various modifications can be made without departing from the scope of the present invention.
[0039]
【The invention's effect】
As described above, according to the present invention, when a plurality of conductive layers are formed simultaneously in a method for manufacturing a semiconductor device, an increase in resistance of the other conductive layer, which is finer than one conductive layer, is suppressed. The reliability of one of the conductive layers can be improved.
[Brief description of the drawings]
FIG. 1 is a schematic plan view schematically showing a part of a semiconductor device according to an embodiment of the present invention and Modification 1;
2A is a schematic cross-sectional view schematically showing main steps of a method of manufacturing a semiconductor device according to an embodiment of the present invention and Modification 1 in order, and FIG. FIGS. 2A and 2B are schematic cross-sectional views sequentially illustrating main steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention and Modification 1 and FIG. 2C illustrates the embodiment of the present invention and Modification 1; It is a schematic sectional drawing which shows typically the main process of the manufacturing method of a semiconductor device one by one typically.
FIG. 3D is a schematic cross-sectional view schematically showing in sequence the main steps of the method for manufacturing a semiconductor device according to the embodiment of the present invention and Modification 1, and FIG. FIGS. 3A and 3B are schematic cross-sectional views sequentially showing main steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention and Modification 1 and FIG. 3F is an embodiment according to the present invention and Modification 1. It is a schematic sectional drawing which shows typically the main process of the manufacturing method of a semiconductor device one by one typically.
FIG. 4 (g) is a schematic cross-sectional view sequentially showing main steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention, and FIG. It is a schematic sectional drawing which shows typically the main process of the manufacturing method of the semiconductor device concerning a form one after another.
FIG. 5 (i) is a schematic cross-sectional view schematically showing in sequence the main steps of the method for manufacturing a semiconductor device according to the first modification of the present invention, and FIG. FIG. 10 is a schematic cross-sectional view schematically sequentially illustrating main steps of a method for manufacturing a semiconductor device according to Modification 1.
FIG. 6 is a schematic cross-sectional view schematically showing a part of a semiconductor device according to Modification 2;
FIG. 7 is a schematic cross-sectional view schematically showing a part of a conventional semiconductor device.
FIG. 8A is a schematic cross-sectional view sequentially showing main steps of a method for manufacturing a semiconductor device according to a conventional technique, and FIG. 8B is a semiconductor according to the conventional technique. FIG. 8C is a schematic cross-sectional view schematically showing the main steps of the device manufacturing method in order, and FIG. 8C is a schematic diagram showing the main steps of an example of a conventional method for manufacturing a semiconductor device in order. It is sectional drawing.
FIG. 9A is a schematic cross-sectional view sequentially illustrating main steps of a conventional method for manufacturing a semiconductor device, and FIG. 9B is a semiconductor according to the related art. FIG. 9C is a schematic cross-sectional view schematically showing the main steps of the device manufacturing method in order, and FIG. 9C is a schematic cross-sectional view showing the main steps of the conventional method for manufacturing a semiconductor device in sequence. It is.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 ... Substrate, 15 ... Lower layer wiring, 16 ... Opening, 20 ... Cap film, 30 ... Insulating film, 31, 32 ... Recess (groove), 33 ... Barrier metal, 35 ... Seed film, 36 ... First buried film , 37 ... second embedded film, 40 ... first conductive layer, 50 ... second conductive layer, 110 ... substrate, 120 ... cap film, 130 ... insulating film, 131, 132 ... recess (groove), 133 ... Barrier metal, 135 ... seed film, 136 ... first buried film, 137 ... second buried film, 140 ... first conductive layer, 150 ... second conductive layer

Claims (6)

Forming an insulating film on the substrate;
Forming a plurality of recesses to be conductive layer forming regions in the insulating film;
Forming a first conductive layer and a second conductive layer so as to embed the recess formed in the insulating film,
Forming the recess so that the second conductive layer is finer than the first conductive layer;
A method for manufacturing a semiconductor device, wherein a concentration of an additive contained in the first conductive layer and having a migration suppressing function is formed to be higher than a concentration of the additive in the second conductive layer. The step of forming the first conductive layer and the second conductive layer includes:
Forming a first embedded film so as to embed the recess;
Forming a second buried film containing the additive on the upper surface of the first buried film;
Removing the first buried film and the second buried film from above until the insulating film is exposed;
Heating so that the additive contained in the second buried film diffuses into the first buried film,
In the step of forming the first buried film, at least a part of the surface of the first buried film formed in the recess in the formation region of the first conductive layer is lower than the upper surface of the insulating film. Forming,
In the step of removing the first and second buried layers, the first buried film and the second buried film are left in a formation region of the first conductive layer, and the second conductive layer The method of manufacturing a semiconductor device according to claim 1, wherein the first buried film is removed so as to remain in the formation region. The step of forming the first conductive layer and the second conductive layer includes:
Forming a first embedded film so as to embed the recess;
Forming a second buried film containing the additive on the upper surface of the first buried film;
Heating so that the additive contained in the second buried film is diffused into the first buried film;
Removing the first buried film and the second buried film from above until the insulating film is exposed,
2. The heating is performed in the heating step under a condition that the additive diffuses into the first buried film in the formation region of the first conductive layer and does not diffuse into the formation region of the second conductive layer. 2. A method of manufacturing a semiconductor device according to 1. The method of manufacturing a semiconductor device according to claim 1, wherein the recess includes an opening formed at a bottom of the recess. 3. The method of manufacturing a semiconductor device according to claim 2, wherein the additive is a conductive substance that easily diffuses into the first buried film by the heating step. 4. The method of manufacturing a semiconductor device according to claim 3, wherein the additive is a conductive substance that easily diffuses into the first buried film by the heating step.

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