JP2008153569A - Interconnection forming method and semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an interconnection forming method in which the Cu polishing rate is increased by strengthening at least a factor of a chemical mechanism or of a mechanical mechanism, and a semiconductor device. <P>SOLUTION: In the interconnection forming method for forming buried interconnects 7 by chemical mechanical polishing, a substance 4 that brings an effect of increasing the polishing rate is added at least to a Cu-based conductive material 3 to be polished and composed of Cu or a Cu alloy mainly composed of Cu, or to an abrasive 6. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a wiring forming method and a semiconductor device, and in particular, an embedded wiring structure using a Cu-based conductive material made of Cu or a Cu alloy containing Cu as a main component is formed by a CMP (Chemical Mechanical Polishing) method. In particular, the present invention relates to a wiring formation method and a semiconductor device characterized by a configuration for improving the Cu polishing rate.

In recent years, Cu wiring with low resistance and high electromigration resistance has been applied as a wiring material for CMOS LSIs that are miniaturized and speeded up.
Unlike conventional Al wiring, this Cu is difficult to process by dry etching. Therefore, a trench or a via hole is formed in the insulating film, and a damascene method in which Cu is embedded therein, or a wiring layer and a via are integrally formed. A dual damascene method has been developed (see, for example, Patent Document 1).

Here, an example of a wiring formation method using a conventional damascene method will be described. First, for example, a via trench and a trench having a wiring layer portion (interlayer thickness) of 440 nm and a minimum via trench diameter of 90 nm A via hole is formed in the interlayer insulating film.
In this case, a low-k material or the like is used as an interlayer insulating material.

  Next, a barrier metal having a thickness of about 10 to 15 nm and a Cu seed having a thickness of about 50 to 100 nm are formed by PVD or CVD using Ta, Ti, W, Zr or the like or a nitride thereof.

  Next, electrolytic plating with copper sulfate plating solution is performed until the plating film thickness reaches about 1 μm, and via holes and trenches are filled. Then, an excess layer is polished by CMP to flatten the wiring. I do.

Then, the planarized buried wiring layer or via surface is capped with a film such as SiC, SiO ₂ , SiOC, SiO ₂ + SiC, or SiN to form one layer.
Thereafter, this is repeated as many times as necessary to form a multilayer structure.
JP 2006-303179 A

  As described above, when a Cu film is polished by CMP to create a wiring portion, improvement of the Cu polishing rate is a big issue from the viewpoint of improvement of throughput and cost. Here, FIGS. The polishing principle of the CMP method will be described with reference to FIG.

See FIG.
FIG. 24 is a conceptual structural explanatory diagram of the CMP method. In general, CMP supplies a slurry 102 onto a polishing cloth called a polishing pad 101 while a wafer 104 to be polished fixed to a polishing head 103 is fixed. This is a technique of polishing while pressing against the polishing pad 101.

Therefore, for the improvement of the CMP polishing rate,
a. Polishing pad b. Slurry c. It can be approached from three viewpoints of the film to be polished.

As shown in Table 1, the slurry 102 used in this CMP is composed of an oxidizing agent, a complexing agent (organic acid), a surfactant, an anticorrosive agent, abrasive grains, and the like.
At present, the oxidant 105 is mainly H ₂ O ₂ from the viewpoint of stability and operation.

See FIG.
The CMP mechanism can be classified into chemical and mechanical. The chemical mechanism oxidizes Cu 106 as a wiring material with an oxidant 105 constituting the slurry 102, and the Cu oxide 107 formed by the oxidation is chemically treated with components constituting the slurry 102. It is a method to dissolve it.

See FIG.
On the other hand, the mechanical mechanism is a method in which Cu 106 is oxidized and Cu oxide 107 formed by the oxidation is physically scraped by sliding friction between polishing pad 101 and Cu 106.
In either mechanism, the element of making the Cu oxide 107 is indispensable, and increasing this oxidation amount leads to an improvement in the polishing rate.

  Accordingly, an object of the present invention is to enhance the Cu polishing rate by strengthening at least one of the chemical mechanism and the mechanical mechanism.

FIG. 1 is a block diagram showing the principle of the present invention. Means for solving the problems in the present invention will be described with reference to FIG.
Reference numeral 1 in the figure denotes a substrate such as a silicon wafer.
Refer to FIG. 1. In order to solve the above-mentioned problem, the present invention is based on Cu or Cu alloy containing Cu as a main component to be polished in a wiring forming method in which the embedded wiring 7 is formed by chemical mechanical polishing. At least one of the Cu-based conductive material 3 or the polishing agent 6 is made to contain a substance 4 that has the effect of improving the polishing rate.

  As described above, by including the substance 4 having an effect of improving the polishing rate in at least one of the Cu-based conductive material 3 or the abrasive 6, the Cu polishing rate is improved and local excessive polishing is less likely to occur. Therefore, dishing is less likely to occur.

  In this case, when the Cu-based conductive material 3 is embedded in the recess 2, the polishing rate of the Cu-based conductive material 3 is improved after the recess 2 has been embedded in the narrow recess having a relatively small width or diameter. It is desirable to bury a wide concave portion having a relatively larger width or diameter than a narrow concave portion that has not yet been buried by adding a polishing accelerator as the substance 4 that brings about an effect.

  As shown in the upper diagram of FIG. 1, the Cu wiring after plating has a narrow concave portion, that is, an overplate 8 in which the upper portion of the aggregated portion of the fine wiring pattern rises as compared with other portions, a wide concave portion, A step such as the under plate 9 in which the thick wiring portion sinks is likely to be formed, but it is necessary to flatten the step in a process of cutting by a chemical mechanical (CMP) method.

  At this time, polishing is most easily performed at the portion in contact with the polishing cloth 5, and using these two of the overplate 8 formed after plating, a substance 4 having an effect of promoting the polishing rate is added to the portion that rises in advance. As shown in the lower diagram of FIG. 1, the polishing rate of the portion to which the substance 4 having an effect of promoting the polishing rate is added is increased, and flattening can be performed without causing dishing.

  In this case, the polishing agent 6 desirably contains at least hydrogen peroxide, whereby the surface of the Cu-based conductive material 3 is effectively oxidized, so that the Cu polishing rate is improved.

Further, as a polishing accelerator to be added to the Cu-based conductive material 3, an inorganic polishing accelerator such as a metal made of iron, silver, titanium, ruthenium, platinum, or manganese, or a sulfur compound such as thiosulfate An organic polishing accelerator which is any one of mercapto salt, persulfate and methyl sulfonate is desirable, and these may be used alone or in combination.
In particular, it is desirable to use a material having high stress migration resistance such as silver or platinum as the polishing accelerator.

  Further, as a film formation method for the Cu-based conductive material 3, at least one deposition method of a physical vapor deposition (PVD) method, a chemical vapor deposition (CVD) method, an electrolytic plating method, or an electroless plating method is used. Should be used.

  Moreover, as a width | variety or diameter of the above-mentioned narrow recessed part, 0.4 micrometer or less is a typical value, and if it is 0.4 micrometer or more, the addition effect of a polishing accelerator will become small.

On the other hand, as the substance 4 having an effect of improving the polishing rate contained in the abrasive 6, R is an organic compound having a molecular weight of 400 or less, and M is any of Na ⁺ , K ⁺ , NH ₄ ⁺ , and H ^+. A sulfur compound consisting of at least one of thiosulfate, mercaptosulfonate (M-R-SH), or disulfide sulfonate (M-R-S-S-R-M). is there.

Also in this case, it is desirable that the abrasive 6 contains at least hydrogen peroxide.
That is, in order to improve the ability of the oxidant H ₂ O ₂ , a method of adding a catalyst that promotes the decomposition of H ₂ O ₂ can be considered, but the catalyst cannot cause a reaction that cannot originally occur. .

Therefore, by using a sulfur compound, sulfur in the sulfur compound is oxidized by H ₂ O ₂ to form H ₂ SO ₄ , and this H ₂ SO ₄ makes it possible to create a stronger oxidation state of Cu. .
In this case, the pH of the abrasive 6 is desirably in the range of 3 to 5. When pH <3, the dissolution rate of Cu increases, but Cu oxidation by sulfur oxide is promoted too much, and “oxidation rate> dissolution”. On the other hand, in the case of pH> 5, the dissolution rate of Cu itself becomes low and the effect of adding sulfur oxides cannot be obtained.

  In this case, the sulfur compound contained in the polishing agent 6 may be added in the polishing agent tank in which the polishing agent 6 is stored, or connected to the polishing agent tank in which the polishing agent 6 is stored by piping. It may be accommodated in the additive tank and mixed immediately before supplying the abrasive 6 and the sulfur compound to the material to be polished.

  Alternatively, the sulfur compound contained in the abrasive 6 may be mixed in a state where the abrasive 6 and the sulfur compound are in contact with the material to be polished and the polishing cloth 5, in which case the sulfur compound is included. The solution may be preliminarily included in the polishing cloth 5 before starting polishing, and may be mixed on the polishing agent 6 and the polishing cloth 5, or a solution containing a sulfur compound may be ejected from the lower side of the polishing cloth 5. Then, the abrasive 6 and the polishing cloth 5 may be mixed.

  In addition, it is desirable to form the embedded wiring 7 in the semiconductor device by the above-described wiring forming method, thereby improving the throughput of the wiring forming process and not causing dishing. Increase in wiring resistance can be prevented.

  In particular, the semiconductor device includes an insulating film, a first wiring groove having a first width formed in the insulating film, a first conductive layer embedded in the first wiring groove, and an insulating film. A second wiring groove having a second width wider than the first width and a second conductive layer embedded in the second wiring groove, and the concentration of the polishing accelerator contained in the second conductive layer is It is characterized by being higher than the concentration of the polishing accelerator contained in one conductive layer.

  The polishing apparatus includes a polishing agent tank for storing the polishing agent 6 and a polishing agent tank and a polishing rate immediately before the polishing agent 6 is supplied to the material to be polished while being connected to the polishing agent tank and piping. It may be configured to include an additive tank for mixing with an additive that brings about an effect of improving polishing, or an additive that brings about an effect of improving the polishing rate is ejected from the back side of the polishing cloth 5 You may comprise so that the additive injection mechanism to be made may be provided.

  According to the present invention, it is possible to improve the throughput by improving the Cu polishing rate, and in particular, by embedding a large wide concave portion by adding a polishing accelerator after the narrow concave portion is embedded, Since the overplate formed on the narrow recess can be quickly removed by polishing, the occurrence of dishing can be suppressed.

In the present invention, Cu or a Cu-based conductive material or a polishing agent containing Cu as a main component or an abrasive, particularly an abrasive containing H ₂ O ₂ , contains a substance that has an effect of improving the polishing rate. This improves the Cu polishing rate in CMP polishing.

In this case, as a polishing accelerator to be added to the Cu-based conductive material, an inorganic polishing accelerator such as a metal made of iron, silver, titanium, ruthenium, platinum, or manganese, or a sulfur compound such as thiosulfate Further, an organic polishing accelerator that is any one of mercapto salt, persulfate, and methyl sulfonate is used.
The content is preferably in the range of 30000 ppm (3% by weight) or less in the case of an inorganic polishing accelerator and 1000 ppm (0.1 wt%) or less in the case of an organic polishing accelerator.
The inorganic polishing accelerator can be controlled by alloy sputtering or the like. However, since the organic polishing accelerator is mainly formed by a film forming method in which the film is incorporated as an impurity, it is difficult to add a high concentration.

Further, as a polishing accelerator to be contained in the polishing agent, when R is an organic compound having a molecular weight of 400 or less and M is any of Na ⁺ , K ⁺ , NH ₄ ⁺ , H ⁺ , thiosulfate, mercaptosulfonic acid A salt (M-R-SH) or a disulfide sulfonate (M-R-S-S-R-M) is used.
Moreover, as content in this case, the range of 3000 ppm (0.3 weight%) or less is desirable.
If 0.1% by weight or more is added to the abrasive, it becomes an active component of the slurry, not the additive, and the characteristics of other surfactants in the slurry are changed.

Here, referring to FIGS. 2 to 4, first, the effect of adding the polishing accelerator will be verified.
See Figure 2
FIG. 2 is an explanatory diagram of the plating process. For example, in the plating bath 14 through the SiO ₂ film 12 and the Ta film 13 on the silicon wafer 11, for example, the plating current is obtained by electrolytic plating under the condition of 10 mA / cm ² . Cu plating is performed to form a Cu film 15 containing a polishing accelerator 16 having a thickness of 2 μm.

In the electrolytic plating process at this time, the plating bath 14 is:
Cu: 40 g / L
H ₂ SO ₄ : 10 g / L
Cl ion: 60ppm
Was used as a reference solution, and 3000 ppm of a sulfur compound shown in Table 2 and 300 ppm of polyethylene glycol having an average molecular weight of 2000 were added to this reference solution.

See Figure 3
Next, the sample was immersed in a polishing solution 17 of H ₂ O ₂ : 6% by weight and citric acid: 3% by weight, and the amount of dissolved Cu per unit time was measured by step measurement.

See Figure 4
FIG. 4 is an explanatory diagram of the measurement results of each sample. The Cu dissolution rate is higher when the sulfur compound is contained, and sodium thiosulfate (Na ₂ S ₂ O ₃ ), sodium mercaptopropanesulfonate (Na ⁺ −). It can be seen that the Cu dissolution rate of the film containing O ₃ S—CH ₂ CH ₂ CH ₂ —SH), sodium disulfide propanoate, or sodium dodecylbenzenesulfonate is increased.

This is because sulfur in the sulfur compound as the polishing accelerator 16 contained in the Cu film 15 is oxidized by H ₂ O ₂ to form H ₂ SO ₄ , and this H ₂ SO ₄ has a stronger Cu oxidation state. This is presumed to be because the additive effect is not obtained for Na ₂ SO ₄ of sample B which is already contained in the completely oxidized form of SO ₄ even if it contains sulfur. The

Next, the step elimination effect will be verified with reference to FIGS.
See Figure 5
FIG. 5 is a conceptual configuration diagram of a sample for verifying the step elimination effect. After forming the region where the narrow wiring trenches 22 are densely formed on the silicon substrate 21 and the wide wiring trench 23, the above-described conditions are satisfied. A Cu film 15 containing a polishing accelerator 16 is formed and polished by the CMP method using the above-described polishing solution 17 of H ₂ O ₂ : 6 wt% and citric acid: 3 wt%.

See FIG.
FIG. 6 is an explanatory diagram of the ability to eliminate the level difference of the samples to which the polishing accelerators of Sample A, Sample E, and Sample F described above are added, and the evaluation of the polishing power is shown in the form of how the level difference is reduced with respect to the polishing amount. The polishing amount = 0 means the initial state.
As is clear from the figure, the step difference cancellation ability of sample F is high, and the tendency coincides with the Cu dissolution rate shown in FIG.

See FIG.
FIG. 7 is a sulfur concentration distribution diagram of Cu films of Sample A, Sample E, and Sample F. Here, the analysis results by SIMS (secondary ion mass spectrometry) are shown, and in the order of A <E <F. High sulfur concentration.
Therefore, it is estimated that the step elimination effect is higher as the polishing accelerator, that is, the impurity contained in the Cu film 15 is higher.

Next, referring to FIG. 8, the S-mig (stress migration) resistance effect is verified.
See FIG.
FIG. 8 shows stress migration resistance by a 504 hour energization test at a temperature of 200 ° C. of a 3.0 μm-wide buried wiring layer to which the polishing accelerators of Sample A, Sample E, and Sample F described above are added. It can be seen that the failure rate of the wiring of the sample F having a high impurity concentration is low.

  From the above results, the step ability is eliminated by including a polishing accelerator 16 that promotes the Cu dissolution rate in the Cu film 15, that is, a sulfur compound containing S (sulfur) that is not completely oxidized. It can be seen that the failure rate of the wiring also decreases as the impurity concentration increases and the impurity concentration increases.

Next, the effect of adding metal impurities will be described with reference to FIG.
See FIG.
FIG. 9 is an explanatory diagram of a Cu dissolution rate when a metal impurity composed of Fe, Pt, Mn, and Ti is added to the Cu film. Here, the Cu film is formed by sputtering, and the addition amount is 3 Evaluated as weight percent.
As can be seen from the figure, the Cu dissolution rate is increased as compared with the case of no addition.

Next, with reference to FIG. 10, the step elimination effect when a polishing accelerator is partially added will be described.
See FIG.
FIG. 10 is a conceptual configuration diagram of a sample for explaining the step elimination effect. After forming the narrow wiring trenches 22 in the silicon substrate 21 and the wide wiring trenches 23, the above-described conditions are satisfied. First, the Cu film 24 is formed using a plating bath to which the polishing accelerator 26 is not added until the narrow wiring trench 22 is completely filled.

Next, by performing electrolytic plating using another plating bath to which the polishing accelerator 26 is added, the wide wiring trench 23 is completely filled with the Cu film 25 to which the polishing accelerator 26 is added.
However, the Cu film 24 may contain the polishing accelerator 26. In this case, the content of the polishing accelerator 26 in the Cu film 24 should be less than the content of the polishing accelerator 26 in the Cu film 25.
Further, in order to form the Cu film 24 and the Cu film 25, it is not always necessary to use a plating bath to which the polishing accelerator 26 is not added and another plating bath to which the polishing accelerator 26 is added. In the plating bath to which the agent 26 is added, the current density of the electroplating is controlled to make the content of the polishing accelerator 26 in the Cu film 24 smaller than the content of the polishing accelerator 26 in the Cu film 25. May be.
In general, it is known that when the current density of electroplating is lowered, the impurity concentration in the plating solution taken into the Cu film tends to increase.

Next, the embedded wiring 27 and the embedded wiring 28 are formed by polishing by the CMP method using the above-described polishing solution of H ₂ O ₂ : 6 wt% and citric acid: 3 wt%.

  In this case, since the polishing accelerator 26 is included in the overplane formed in the upper part of the narrow wiring trench 22 where the polishing is preferentially performed, the polishing is performed quickly. Flattening is possible without causing dishing in the region.

  Further, although the polishing accelerator 26 is still added to the embedded wiring 28, since the polishing accelerator 26 is not added to the narrow embedded wiring 27 that tends to have high resistance, good conductivity is obtained. Can keep.

Next, the effect when a polishing accelerator is added to the abrasive will be verified.
here,
Oxidizing agent H ₂ O ₂ : 6% by weight
Complexing agent Citric acid: 3% by weight
The results of comparison of pH, ORP (oxidation-reduction potential) fluctuation, and Cu dissolution rate at that time when various sulfur compounds are added to a slurry containing KOH and adjusted to pH 4 with KOH are shown.
In addition, as each chemical | medical agent, the Kanto Chemical Co., Ltd. city medicine special grade was used.

As a sulfur compound to be added in this case,
Sodium sulfate: Na ₂ SO ₄
Sodium mercaptopropanesulfonate: Na ⁺ -O ₃ S—CH ₂ CH ₂ CH ₂ —SH Sodium thiosulfate: Na ₂ S ₂ O ₃
Four types of mercaptobenzenethiazole were used.

See FIG.
FIG. 11 is an explanatory diagram of a method for measuring pH and ORP, in which the pH / ORP electrode 32 is immersed in the slurry 31 and measured while stirring the slurry 31 with the stirrer 33.
As the pH / ORP electrode 32 in this case, a Castany D51 electrode (trade name, manufactured by HORIBA) was used.
The ORP value is also an index indicating the oxidation potential, and the higher the value, the higher the oxidation potential and the stronger the oxidizing power.

  The Cu dissolution rate was calculated by observing the difference in film thickness before and after the Cu sample was immersed in the slurry 31 with SEM (S-5200: Hitachi, Ltd., product model number) and dividing the difference by the immersion time.

Table 3 summarizes the pH, ORP value, and Cu dissolution rate of the slurry when each sulfur compound is added.

As is apparent from Table 3, the effect of increasing the Cu dissolution rate by adding sodium sulfate is not observed. Further, the addition of sodium mercaptopropanesulfonate increases the ORP and Cu dissolution rate.
Sodium thiosulfate also increases the ORP and Cu dissolution rate upon addition.

On the other hand, when mercaptobenzothiazole is added, the ORP increases, but the Cu dissolution rate decreases.
This is because thiazole acts as an anticorrosive for Cu, and even if it is a sulfur compound, addition of a thiazole compound is not preferable.

See FIG.
FIG. 12 is an explanatory diagram of the effect of increasing the Cu dissolution rate by adding a sulfur compound based on Table 3, and as is apparent from the figure, when sodium mercaptopropanesulfonate or sodium thiosulfate is added, the Cu dissolution rate is increased. As a result, an increase was obtained.

Next, with reference to FIG. 13, the slurry pH dependency of the effect of increasing the Cu dissolution rate by adding a sulfur compound will be described.
See FIG.
FIG. 13 is an explanatory diagram of the slurry pH dependence of the effect of increasing the Cu dissolution rate by adding a sulfur compound, and a large addition effect was confirmed in the range of pH = 3-5.
When pH <3, the Cu dissolution rate increases, but the Cu dissolution rate without addition is originally high, and Cu oxidation by sulfur oxide is promoted too much, so that the dissolution rate rate of “oxidation rate> dissolution rate”. On the other hand, when pH> 5, the Cu dissolution rate itself becomes low, and as shown in Table 4, the effect of adding sulfur oxides cannot be obtained.

表４は、Ｃｕ溶解レート上昇率のｐＨ依存性を纏めたものであり、ｐＨ＞５、例えば、ｐＨ＝９の場合には、Ｃｕ溶解レート上昇率は３８．９％と非常に高いものの、Ｃｕ溶解レートの絶対値が小さくなるため、硫黄酸化物の添加効果が得られなくなる。

Table 4 summarizes the pH dependence of the Cu dissolution rate increase rate. When pH> 5, for example, pH = 9, the Cu dissolution rate increase rate is very high at 38.9%. Since the absolute value of the Cu dissolution rate is small, the effect of adding sulfur oxide cannot be obtained.

Next, a method for adding a polishing accelerator to the slurry will be described with reference to FIGS.
See FIG.
FIG. 14 is an explanatory diagram of a first method of adding a polishing accelerator to the slurry. When polishing is performed by pressing the wafer 44 held and fixed on the polishing head 43 against the polishing pad 42 fixed on the surface plate 41. In addition, the above-described polishing accelerator 47 is added to the slurry 46 in the slurry tank 45 and supplied onto the polishing pad 42 via the pipe 48.

See FIG.
FIG. 15 is an explanatory view of a second method of adding a polishing accelerator into the slurry, and when polishing is performed by pressing the wafer 44 held and fixed on the polishing head 43 against the polishing pad 42 fixed on the surface plate 41. Further, when the polishing accelerator 47 is accommodated in the polishing accelerator tank 49 and the slurry 46 is supplied from the slurry tank 45 to the polishing pad 42 via the pipe 48, the polishing accelerator 47 is supplied via the pipe 50. Supply at the same time.

See FIG.
FIG. 16 is an explanatory diagram of a third method of adding a polishing accelerator to the slurry. When polishing is performed by pressing the wafer 44 held and fixed on the polishing head 43 against the polishing pad 42 fixed on the surface plate 41. Further, when the polishing accelerator 47 is accommodated in the polishing accelerator tank 51 and the slurry 46 is supplied from the slurry tank 45 to the polishing pad 42 via the pipe 48, the polishing accelerator 47 is supplied via the pipe 52. It supplies simultaneously from the lower side of the polishing pad 42.

See FIG.
FIG. 17 is an explanatory diagram of a third method of adding a polishing accelerator to the slurry. When polishing is performed by pressing the wafer 44 held and fixed to the polishing head 43 against the polishing pad 42 fixed on the surface plate 41. In addition, the above-described polishing accelerator 47 is impregnated in the polishing head 43 in advance, and the slurry 46 is supplied from the slurry tank 45 to the polishing pad 42 via the pipe 48, and the polishing accelerator 47 is supplied from the polishing pad 43. And polishing.

Based on the above, the embedded wiring forming method according to the first embodiment of the present invention will now be described with reference to FIGS.
Although the illustration of the first step is omitted, first, after forming an element isolation insulating film on a p-type silicon substrate, a gate electrode is provided through the gate insulating film, and an n-type impurity is introduced using this gate electrode as a mask. Thus, an n-type extension region is formed, a sidewall is formed, and an n-type source / drain region is formed by introducing an n-type impurity again.

See FIG.
Next, after depositing Co on the entire surface, heat treatment is performed to form a Co silicide electrode. Next, after removing unreacted Co, an SiO ₂ film 61 and a BPSG film 62 are deposited on the entire surface, and then the surface is flattened. Then, a cap layer 63 made of SiOCN is formed.

  Next, via holes reaching the n-type source / drain regions are formed, W is buried through a barrier film 64 made of TiN, and unnecessary portions are removed by CMP to form a W plug 65.

  Next, an etching stopper film 66 made of SiOCN having a thickness of, for example, 50 nm, a first interlayer insulating film 67 made of SiOC having a thickness of, for example, 250 nm, and a thickness of, for example, 50 nm are formed using plasma CVD. A cap layer 68 made of a SiOCN film is sequentially deposited.

  Next, using a resist pattern (not shown) as a mask, a buried wiring trench 69 that partially exposes the W plug 65 is formed by plasma etching using a fluorocarbon-based etching gas, and then the resist pattern is removed. .

Next, after forming a barrier film 70 made of Ta by using a sputtering method, electrolytic plating is performed in a plating bath to which sodium thiosulfate is added, thereby filling the embedded wiring trench 69 with the Cu layer 71, and then The first Cu embedded wiring 72 is formed by removing unnecessary portions by CMP.
In this CMP step, since the Cu layer 71 contains sodium thiosulfate as a polishing accelerator, the polishing rate increases, and the polishing stops at the position of the cap layer 68 as a stopper in a short time.

See FIG.
Next, again using the plasma CVD method, for example, an etching stopper film 73 made of SiOCN having a thickness of 50 nm, a second interlayer insulating film 74 made of SiOC having a thickness of, for example, 400 nm, and a thickness of, for example, A cap film 75 made of SiOCN of 50 nm is sequentially deposited.

  Next, a via hole 76 reaching the first Cu embedded wiring 72 is formed by plasma etching using a fluorocarbon-based etching gas again using the resist pattern (not shown) as a mask, and embedded wiring grooves 77 and 78 are formed. After the formation, the resist pattern is removed, and then a barrier film 79 made of Ta is formed again using the sputtering method.

See FIG.
Next, again, electrolytic plating is performed in a plating bath to which sodium thiosulfate is added, thereby filling the via hole 76 and the embedded wiring grooves 77 and 78 with the Cu layer 80.

Next, after unnecessary portions are removed by CMP, Cu vias 81 and second Cu buried wirings 82 and 83 are formed, and then a diffusion prevention film made of SiOCN having a thickness of, for example, 50 nm using plasma CVD again. 84 is deposited.
Even in this CMP process, since the second Cu embedded wirings 82 and 83 contain sodium thiosulfate as a polishing accelerator, the polishing rate increases, and the polishing is stopped at the cap layer 75 serving as a stopper in a short time. To do.

  Thereafter, the diffusion prevention film 84 is used as an etching stopper film according to the required number of multilayer wiring layers, an interlayer insulating film and cap layer deposition process, a wiring trench and via hole forming process, and via and embedded wiring The semiconductor device is completed by repeating the formation process.

  Thus, in Example 1 of the present invention, sodium thiosulfate, which is a polishing accelerator in the CMP process, is added to the Cu layer and the Cu via, so that the polishing rate is improved and the throughput is improved. Occurrence of dishing in the under plate portion is suppressed.

Next, a method for forming a buried wiring according to the second embodiment of the present invention will be described with reference to FIGS.
Although the illustration of the first step is omitted, exactly as in the first embodiment, first, after forming an element isolation insulating film on a p-type silicon substrate, a gate electrode is provided via the gate insulating film, and this gate An n-type extension region is formed by introducing an n-type impurity using the electrode as a mask, and after forming a sidewall, an n-type impurity is again introduced to form an n-type source / drain region.

See FIG.
Next, after depositing Co on the entire surface, heat treatment is performed to form a Co silicide electrode. Next, after removing unreacted Co, an SiO ₂ film 61 and a BPSG film 62 are deposited on the entire surface, and then the surface is flattened. Then, a cap layer 63 made of SiOCN is formed.

  Next, via holes reaching the n-type source / drain regions are formed, W is buried through a barrier film 64 made of TiN, and unnecessary portions are removed by CMP to form W plugs 65.

  Next, an etching stopper film 66 made of SiOCN having a thickness of, for example, 50 nm, a first interlayer insulating film 67 made of SiOC having a thickness of, for example, 250 nm, and a thickness of, for example, 50 nm are formed using plasma CVD. A cap layer 68 made of a SiOCN film is sequentially deposited.

  Next, using a resist pattern (not shown) as a mask, a buried wiring trench 69 that partially exposes the W plug 65 is formed by plasma etching using a fluorocarbon-based etching gas, and then the resist pattern is removed. .

  Next, after a barrier film 70 made of Ta is formed by sputtering, electrolytic plating is performed in a normal sulfuric acid-based plating bath to fill the embedded wiring trench 69 with the Cu layer 90.

Next, the first Cu embedded wiring 92 is formed by removing unnecessary portions by CMP using the slurry 91 added with sodium thiosulfate shown in Table 2 above.
In this CMP step, since the slurry 91 contains sodium thiosulfate as a polishing accelerator, the polishing rate increases, and the polishing stops at the position of the cap layer 68 as a stopper in a short time.

See FIG.
Next, again using the plasma CVD method, for example, an etching stopper film 73 made of SiOCN having a thickness of 50 nm, a second interlayer insulating film 74 made of SiOC having a thickness of, for example, 400 nm, and a thickness of, for example, A cap film 75 made of SiOCN of 50 nm is sequentially deposited.

  Next, using the resist pattern (not shown) as a mask again, via holes 76 reaching the first Cu embedded wiring 92 are formed by plasma etching using a fluorocarbon-based etching gas, and embedded wiring grooves 77 and 78 are formed. After the formation, the resist pattern is removed, and then a barrier film 79 made of Ta is formed again using the sputtering method.

See FIG.
Next, the via hole 76 and the buried wiring grooves 77 and 78 are buried with the Cu layer 93 again by performing electrolytic plating in a normal sulfuric acid plating bath.

Next, unnecessary portions are removed by CMP using the slurry added with sodium thiosulfate shown in Table 2 above to form Cu vias 94 and second Cu buried wirings 95 and 96, and then plasma CVD is performed again. A diffusion preventing film 84 made of SiOCN having a thickness of, for example, 50 nm is formed by using this method.
Even in this CMP step, since the slurry contains sodium thiosulfate as a polishing accelerator, the polishing rate increases, and the polishing stops at the cap layer 75 as a stopper in a short time.

  Thereafter, the diffusion prevention film 84 is used as an etching stopper film according to the required number of multilayer wiring layers, an interlayer insulating film and cap layer deposition process, a wiring trench and via hole forming process, and via and embedded wiring The semiconductor device is completed by repeating the formation process.

  As described above, in Example 2 of the present invention, since sodium thiosulfate serving as a polishing accelerator is added to the slurry used in the CMP process, the polishing rate is improved, the throughput is improved, and the underplate portion is increased. Occurrence of dishing in is suppressed.

  The embodiment and each example of the present invention have been described above, but the present invention is not limited to the configurations, conditions, and numerical values shown in the embodiment and each example, and various modifications are possible. For example, although the wiring and the via are made of Cu, it is not limited to pure Cu, and a Cu alloy containing silver, platinum or the like may be used.

  In Example 1, sodium thiosulfate is used as a polishing accelerator to be added to Cu. However, other sulfur compounds in which the sulfur shown in the above embodiment is not completely oxidized may be used. Or a metal such as Fe, Ag, Ti, Ru, Pt, or Mn may be added. When a metal is added, a polishing accelerator composed of a sulfur compound is added to the slurry. It may be added.

For example, other sulfur compounds in which sulfur is not completely oxidized include thiosulfate, mercaptosulfonate (M-R-SH), or disulfide sulfonate (M-R-S-S-R--). M).
Here, R is an organic compound having a molecular weight of 400 or less, and M is any one of Na ⁺ , K ⁺ , NH ₄ ⁺ , and H ⁺ .

Here, referring to FIG. 1 again, the detailed features of the present invention will be described again.
Again see Figure 1
(Supplementary Note 1) In the wiring forming method in which the embedded wiring 7 is formed by chemical mechanical polishing, at least the Cu-based conductive material 3 or the polishing agent 6 made of Cu or a Cu alloy containing Cu as a main component is polished. A wiring forming method characterized by containing a substance 4 that brings about an effect of improving the polishing rate on one side.
(Appendix 2) When the Cu-based conductive material 3 is embedded in the recess 2, the Cu-based conductive material 3 is polished after the recess 2 has been embedded in the narrow recess having a relatively small width or diameter. The wiring according to appendix 1, wherein a polishing accelerator is added as the substance 4 having an effect of improving the speed, and a wide concave portion having a relatively larger width or diameter than that of the narrow concave portion which has not been embedded yet is embedded. Forming method.
(Additional remark 3) The wiring formation method of Additional remark 1 or 2 characterized by the above-mentioned abrasive | polishing agent 6 containing hydrogen peroxide at least.
(Supplementary note 4) The wiring formation method according to supplementary note 2, wherein the polishing accelerator added to the Cu-based conductive material 3 is one or more kinds.
(Additional remark 5) The wiring formation method of Additional remark 5 characterized by the polishing promoter added to the said Cu type electrically-conductive material 3 being the metal which consists of iron, silver, titanium, ruthenium, platinum, or manganese.
(Supplementary note 6) The wiring formation method according to supplementary note 5, wherein the polishing accelerator added to the Cu-based conductive material 3 is a sulfur compound.
(Supplementary note 7) The wiring forming method according to supplementary note 7, wherein the sulfur compound is any one of thiosulfate, mercapto salt, persulfate, and methylsulfonate.
(Appendix 8) The Cu-based conductive material 3 is deposited using at least one deposition method of physical vapor deposition, chemical vapor deposition, electrolytic plating, or electroless plating. The wiring formation method according to any one of appendices 1 to 7.
(Additional remark 9) The width | variety or diameter of the said narrow recessed part is 0.4 micrometer or less, The wiring formation method of any one of Additional remark 1 thru | or 8 characterized by the above-mentioned.
(Supplementary Note 10) The 4 resulting in the effect of improving the polishing rate to be contained in the polishing agent 6, molecular weight R is 400 or less of the organic compound, the ^{M Na +, K +, NH} 4 +, and either H ⁺ In this case, the sulfur compound is composed of at least one of thiosulfate, mercaptosulfonate (M-R-SH), or disulfide sulfonate (M-R-S-S-R-M). 10. The wiring forming method according to any one of appendices 1 to 9, which is characterized by the following.
(Additional remark 11) The said abrasive | polishing agent 6 contains hydrogen peroxide at least, The wiring formation method of Additional remark 10 characterized by the above-mentioned.
(Additional remark 12) pH of the said abrasive | polishing agent 6 is 3-5, The wiring formation method of Additional remark 11 characterized by the above-mentioned.
(Appendix 13) An insulating film, a first wiring groove having a first width formed in the insulating film, a first conductive layer embedded in the first wiring groove, and formed in the insulating film, A concentration of a polishing accelerator included in the second conductive layer, the second wiring groove having a second width wider than the first width; and a second conductive layer embedded in the second wiring groove. Is higher than the concentration of the polishing accelerator contained in the first conductive layer.

  As a practical example of the present invention, a process of forming a buried wiring of a semiconductor integrated circuit device is typical. However, a ferroelectric optical device such as a liquid crystal device, a light deflection element, a light coil in a magnetic disk device, etc. It is also applied to the manufacturing process.

It is explanatory drawing of the fundamental structure of this invention. It is explanatory drawing of a plating process. It is explanatory drawing of the measuring method of Cu dissolution amount. It is explanatory drawing of the measurement result of each sample. It is a conceptual block diagram of the sample for verifying the level | step difference elimination effect. It is explanatory drawing of the level | step difference elimination capability of the sample which added the grinding | polishing promoter of the sample A, the sample E, and the sample F. FIG. It is a sulfur concentration distribution diagram of Cu films of sample A, sample E, and sample F. It is explanatory drawing of the stress migration tolerance of the sample A, the sample E, and the sample F. FIG. It is explanatory drawing of Cu dissolution rate at the time of adding a metal impurity in Cu film | membrane. It is a conceptual block diagram of the sample for demonstrating the level | step difference elimination effect. It is explanatory drawing of the measuring method of pH and ORP. It is explanatory drawing of the effect of Cu dissolution rate raise by addition of the sulfur compound based on Table 3. FIG. It is explanatory drawing of slurry pH dependence of the effect of Cu dissolution rate raise by addition of a sulfur compound. It is explanatory drawing of the 1st addition method of the grinding | polishing promoter in a slurry. It is explanatory drawing of the 2nd addition method of the grinding | polishing promoter in a slurry. It is explanatory drawing of the 3rd addition method of the grinding | polishing promoter in a slurry. It is explanatory drawing of the 4th addition method of the grinding | polishing promoter in a slurry. It is explanatory drawing to the middle of the embedded wiring formation method of Example 1 of this invention. It is explanatory drawing to the middle after FIG. 18 of the embedded wiring formation method of Example 1 of this invention. FIG. 20 is an explanatory diagram after FIG. It is explanatory drawing to the middle of the embedded wiring formation method of Example 2 of this invention. It is explanatory drawing to the middle after FIG. 21 of the embedded wiring formation method of Example 2 of this invention. It is explanatory drawing after FIG. 22 of the embedded wiring formation method of Example 2 of this invention. It is a conceptual structure explanatory drawing of CMP method. It is explanatory drawing of the chemical mechanism of CMP. It is explanatory drawing of the mechanical mechanism of CMP.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Substrate 2 Recess 3 Cu-based conductive material 4 Substance that brings about the effect of improving the polishing rate 5 Polishing cloth 6 Polishing agent 7 Embedded wiring 8 Overplate 9 Underplate 11 Silicon wafer 12 SiO ₂ film 13 Ta film 14 Plating bath 15 24, 25 Cu film 16 Polishing accelerator 17 Polishing liquid 21 Silicon substrate 22 Narrow wiring trench 23 Wide wiring trench 26, 47 Polishing accelerator 27, 28 Embedded wiring 31, 46 Slurry 32 pH / ORP electrode 33 Staller 41 Surface plate 42 Polishing pad 43 Polishing head 44 Wafer 45 Slurry tank 61 SiO ₂ film 62 BPSG film 63 Cap layer 64 Barrier film 65 W plug 66 Etching stopper film 67 First interlayer insulating film 68 Cap layer 69 Embedded wiring groove 70 Barrier films 71, 80, 90, 93 Cu layer 72 First Cu buried Wiring 73 Etching stopper film 74 Second interlayer insulating film 75 Cap film 76 Via hole 77, 78 Embedded wiring trench 79 Barrier film 81 Cu via 82, 83 Second Cu embedded wiring 84 Diffusion prevention film 91 Slurry 92 First Cu embedded wiring 94 Cu vias 95 and 96 Second Cu embedded wiring 101 Polishing pad 102 Slurry 103 Polishing head 104 Wafer 105 Oxidant 106 Cu
107 Cu oxide

Claims (5)

In a wiring formation method of forming embedded wiring by chemical mechanical polishing, polishing rate is improved at least one of Cu-based conductive material or polishing agent made of Cu or Cu alloy containing Cu as a main component. A wiring formation method comprising a substance that brings about an effect. A substance that, when embedding the Cu-based conductive material in the recess, brings about an effect of improving the polishing rate to the Cu-based conductive material after the embedding of the narrow recess having a relatively small width or diameter is completed. 2. A method of forming a wiring according to claim 1, wherein a polishing accelerator is added to bury a wide concave portion having a relatively larger width or diameter than the narrow concave portion that has not yet been embedded. The wiring forming method according to claim 1, wherein the abrasive contains at least hydrogen peroxide. 4. The polishing accelerator to be added to the Cu-based conductive material is one of iron, silver, titanium, ruthenium, platinum, a metal made of manganese, or a sulfur compound. The wiring formation method according to Item 1. An insulating film; a first wiring groove having a first width formed in the insulating film; a first conductive layer embedded in the first wiring groove; and the first width formed in the insulating film. A second wiring groove having a second width wider than the second wiring groove, and a second conductive layer embedded in the second wiring groove, wherein the concentration of the polishing accelerator contained in the second conductive layer is A semiconductor device, wherein the concentration is higher than the concentration of the polishing accelerator contained in one conductive layer.

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