KR100363696B1 - Method for forming mutilayered metal line in semiconductor device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a multi-layered metal wiring in a semiconductor device, and in particular, this method forms a planarized interlayer insulating film on the entire surface of the substrate on which the lower metal wiring is formed, and after forming the first photoresist pattern on the substrate, activates CxFy. After forming a step by thin trench etching the interlayer insulating film under the first photoresist pattern with the plasma, the first photoresist pattern is removed and an organic antireflective coating is applied on the entire surface of the resultant, and then the second photoresist pattern is formed on the organic antireflection coating. The organic anti-reflective film and the interlayer insulating film are etched using the plasma having activated CxFy to form the via and the upper wiring trench in the interlayer insulating film at the same time, and the metal is buried in the interlayer insulating film on which the via and the upper wiring trench are formed. Grind it to make the via plug and the upper wiring connected to the lower metal wiring At the same time to form. Accordingly, the present invention can implement fine patterning of the photoresist using an organic antireflection film, and like the double damascene method, the vias for plugs and the trenches for metal wirings can be simultaneously etched to improve the precision of the metal wiring patterns.

Description

Method for forming mutilayered metal line in semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a multi-layered metal wiring in a semiconductor device. In particular, a via plug for via plug and wiring area space can be obtained by a new dual damascene method which greatly secures a process margin for photosensitive film patterning in a multi-layered wiring device of a highly integrated semiconductor device. It is a technique that can simultaneously etch a trench.

In semiconductor devices, as the degree of integration of devices increases, the gap between metal interconnections becomes narrower, and as the number of metal interconnections gradually increases, a plug process for vertically connecting upper and lower metals to each other has become increasingly important.

Recently, since the size of the device is reduced and high-speed operation is required, the performance of the device itself is greatly improved in addition to manufacturing a semiconductor device using a fine fabrication technique. Accordingly, the semiconductor device uses a multilayer wiring structure to maximize the performance of the active device.

1A to 1J are process flowcharts for sequentially explaining a method of forming a multilayer metal wiring of a semiconductor device according to the prior art. Referring to this, an example of a conventional multilayer metal wiring process is as follows.

First, as shown in FIG. 1A, the first diffusion barrier film 11, such as Ti and TiN, and the Al layer (as a metal) are formed on a surface of a lower structure 10 such as a semiconductor element formed on a semiconductor substrate through a predetermined wiring process. 12) and the second diffusion barrier 13, such as Ti and TiN, are sequentially layered, and the photolithography and etching processes are performed to pattern the diffusion barriers 11 and 13 and the metal Al layer 12 to form a lower metal wiring (bl). ).

In addition, as shown in FIG. 1B, after depositing an interlayer insulating layer 14 for electrically interlayer insulating the lower metal wiring bl and the upper wiring to be formed thereafter, a polishing process, for example, chemical mechanical polishing (Chemical Mechanical Polishing) ), The surface of the interlayer insulating film 14 is polished flat. At this time, when the interlayer insulating film 14 is deposited, the upper surface of the interlayer insulating film 14 is curved according to the topology of the lower metal wiring bl, thereby removing the bending occurring on the surface of the interlayer insulating film by a polishing process and matching the thickness required by the design. .

Subsequently, as shown in FIG. 1C, a photolithography process is performed on the planarized interlayer insulating film 14 to form contact holes of vertical interconnections. The photoresist pattern 16 is deposited by exposing and developing the photoresist. Form.

Subsequently, as shown in FIG. 1D, the interlayer insulating layer 14 is selectively etched according to the photoresist pattern 16, and the interlayer insulating layer 14 is etched with an activated plasma, for example, a CxFy-activated plasma. ).

Next, as shown in FIG. 1E, a third diffusion barrier film 18 made of Ti / TiN or the like is deposited on the surface of the interlayer insulating film 14 on which the vias 17 are to be formed, and then subjected to a chemical vapor deposition (CVD) method. W 20 is embedded in via 17 as a via-plug metal layer.

In addition, as illustrated in FIG. 1F, the polishing process is performed by chemical mechanical polishing (CMP) or plasma etch back using plasma to planarize the entire surface while removing all metals in the region outside the via 17. By removing Ti, TiN 18 and W 20 in the interlayer insulating film 14, the surface is planarized to form a W plug 20 'embedded in the via 17.

Then, as shown in FIG. 1G, a fourth diffusion barrier film 21 such as Ti / TiN, Al (22) as the upper wiring metal, and a fifth diffusion barrier film such as Ti / TiN to proceed the upper wiring process. (23) is sequentially deposited.

1H and 1I, a photolithography process is performed on the surface of the fifth diffusion barrier layer 23 to form a photoresist pattern 24 for upper wiring, and an etching process using the photoresist pattern 24 is performed. Next, the fifth diffusion barrier 23, Al 22, and the fourth diffusion barrier 21 are patterned with an activated plasma, for example, a CxFy plasma gas, to form an upper metal wiring tl.

Subsequently, as shown in FIG. 1J, the upper interlayer insulating film 26 is deposited on the resultant product on which the upper metal wiring tl is formed, and the surface thereof is planarized.

By repeating this manufacturing process, a multilayer wiring of a semiconductor device can be manufactured.

However, in the case of the manufacturing method of a general metal wiring, which proceeds separately through the metal wiring and via etching, while having a stable process can be implemented, there are the following problems in process characteristics.

First, in photoresist patterning, forming a hole or pad generally requires less process margin than forming a line. And, the higher the thickness of the photosensitive film, the harder the patterning becomes. Therefore, in the conventional process method, since the via-hole is patterned in the photosensitive film having a considerably high thickness, it is difficult to realize fine patterning.

Second, when tungsten is used as the metal of the plug connecting the upper and lower wirings vertically, the electrical resistivity (Rs) is higher than that of conventional aluminum, so that the electrical resistance of the metal wiring using the tungsten plug is increased. If the wiring through which the current flows is high, the power consumption of the semiconductor device increases, which shortens the current life.

Third, in order to improve the shortcomings of the tungsten plug, a method of using copper as a metal wiring material having a small specific resistance and having advantages in improving the performance of semiconductor devices, for example, reducing RC delay time and improving reliability, has been proposed. However, copper does not produce volatile compounds well at lower temperatures than aluminum, making it difficult to etch.

Fourth, the process order of the multilayer wiring manufacturing process is generally performed by forming the metal wiring → forming the via → forming the tungsten plug → forming the metal wiring, so that the number of processes increases and the manufacturing process cost increases and the process becomes complicated. The yield of is also lowered.

Recently, a damascene method has been proposed to improve the disadvantage of the multilayer wiring manufacturing process. This damascene method is a technique of forming a metal wiring by first forming a metal wiring via in an interlayer insulating film and filling a metal in the hole instead of the conventional process method of etching a metal layer deposited on the insulating film to form a metal wiring. Since the metal wiring manufacturing process by the damascene method does not have to perform the etching process of the metal wiring, it is possible to solve the problem generated during etching of the copper wiring.

In addition, the dual damascene method developed to solve the drawbacks of the complicated wiring process simultaneously inserts the via and metal wiring contact holes into the interlayer insulating film, and then simultaneously fills the metal with the via and the contact holes to insert the plug and the metal wiring. It is a technique to complete at the same time. Such double damascene processes are known to have a process number that is reduced by about 30% compared to conventional process schemes.

Therefore, recently, in the case of a multilayer wiring and a highly integrated semiconductor device, a double damascene process capable of simultaneously forming a contact plug and a wiring is used, but there are still many problems to be solved in the manufacturing process.

An object of the present invention is to improve the precision of the metal wiring pattern by simultaneously etching the plug via and the metal wiring trench by using an organic anti-reflective coating layer used for the fine patterning of the photosensitive film during the metal wiring manufacturing process The present invention provides a method of forming a multilayer metal wiring of a semiconductor device.

1A to 1J are process flowcharts for sequentially explaining a method of forming a multilayer metal wiring of a semiconductor device according to the prior art;

2A to 2L are process flowcharts for explaining a method for forming a multilayer metal wiring of a semiconductor device according to the present invention.

Explanation of symbols on the main parts of the drawings

100: lower structure of the semiconductor substrate 104: interlayer insulating film

106: first photosensitive film pattern 107: interlayer insulating film step

108: organic antireflection film 110 ': second photosensitive film pattern

112,112a: Via 112b: trench

101,103,114: diffusion barrier 102,116: metal

118: upper interlayer insulating film p: plug

bl: bottom metal wiring

tl: upper metal wiring

In order to achieve the above object, the present invention provides a method for manufacturing a multilayer wiring of a semiconductor device, the method comprising: forming a lower metal wiring on a structure of a semiconductor substrate, and forming a planarized interlayer insulating film on the entire surface of the substrate on which the lower metal wiring is formed. And forming a step by forming a first photoresist pattern on the substrate, thinly trench-etching the interlayer insulating layer under the first photoresist pattern with CxFy-activated plasma, and removing the first photoresist pattern and removing the entire surface of the resultant. Applying an organic anti-reflection film to the organic light-emitting layer, forming a second photoresist pattern on the organic anti-reflection film, and etching the organic anti-reflection film and the interlayer insulating film in accordance with the second photoresist film pattern using CxFy-activated plasma to etch vias in the interlayer insulating film. And simultaneously forming an upper wiring trench, and forming a via and an upper wiring trench at the same time. Embedding the metal in the interlayer insulating film and polishing the metal, thereby simultaneously forming a via plug and an upper wiring connected to the lower metal wiring.

In the manufacturing method of the present invention, the thickness of the first photoresist layer pattern is (via depth + transient etch depth) / [(etch ratio of interlayer insulation layer to photoresist layer) × (interlayer insulation layer etching ratio to organic antireflection film) -1 ] It is preferable that it is more than.

In the manufacturing method of the present invention, the trench etching thickness of the interlayer insulating film under the first photoresist pattern is preferably (via depth + transient etching depth) / [(etch ratio of interlayer insulating film to organic antireflection film) -1]. Do.

In the manufacturing method of the present invention, the step of etching the organic anti-reflection film and the interlayer insulating film in accordance with the second photoresist pattern, has a high etch ratio with respect to the second photoresist and the entire surface of the organic anti-reflection film until the surface of the interlayer insulating film is exposed Performing an etching process until the organic antireflective film embedded in the trench of the interlayer insulating film is etched to form a via in the interlayer insulating film, and removing the organic antireflective film, and continuing the etching process in the interlayer insulating film. And forming a via and a top trench to reveal the bottom metallization surface.

In the manufacturing method of the present invention, the first photoresist pattern defines a via plug region connecting the lower and upper metal interconnections, and the second photoresist pattern defines a region where the via plug and the upper metal interconnection are not formed.

According to the technical principle of the present invention, the organic antireflection film has a molecular structure similar to that of the photoresist film, so that the adhesion with the photoresist film is appropriate and the curing process is not mixed with the photoresist film. In the photoresist patterning process, the photoresist may form a photoresist pattern by an exposure and development process because there is no photoresist and does not react with light. However, in the case of an organic antireflection film, the reaction does not occur even when light is irradiated, and thus a pattern cannot be formed. In addition, patterning the photoresist film after applying the photoresist film on the organic antireflection film not only improves the patterning characteristics but also increases the process margin.

Therefore, the present invention uses an organic antireflection film during the metallization manufacturing process, but forms a step in the interlayer insulating film by etching a thin trench in advance to form a trench for metal wiring, and then, an organic antireflection film is applied to facilitate photoresist patterning. By using the organic anti-reflection film remaining in the region where the trench is etched as a hard mask, the plug via and the metal wiring trench can be simultaneously etched in the interlayer insulating film so that the double damascene method can be effectively implemented and the accuracy of the metal wiring pattern can be improved. Can be.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred method for forming a metal wiring of the present invention.

2A to 2L are process flowcharts for explaining a method for forming a multilayer metal wiring of a semiconductor device according to the present invention.

First, as shown in FIG. 2A, the first diffusion barrier film 101 such as Ti and TiN and the Al layer as a metal are subjected to a predetermined wiring process on the surface of the lower structure 100 such as a semiconductor element formed on the semiconductor substrate. 102 and second diffusion barrier films 103 such as Ti and TiN are sequentially stacked and photographed and etched to form the diffusion barrier films 101 and 103 and the Al layer 102 to form a lower metal interconnect bl. do.

As shown in FIG. 2B, the surface of the interlayer insulating film 104 is smoothly polished by a polishing process after depositing an interlayer insulating film 104 for electrically insulating the lower metal wiring bl and the upper wiring to be formed later. do. However, when the lower metal wiring bl is formed by the damascene process, the polishing of the interlayer insulating film 104 may be omitted since the resultant surface is already flattened. Here, the thickness of the interlayer insulating film 104 on the lower metal wiring bl is determined as (via depth) + (upper metal wiring height).

Next, as shown in FIG. 2C, the first photoresist layer pattern 106 is formed on the interlayer insulating layer 104 by a photolithography process such as coating, exposure, and development, and the thickness t1 is (via depth + Transient etching depth) / [(etch ratio of interlayer insulating film to photoresist film) × (interlayer insulating film etching ratio to organic antireflection film) -1] or more.

In this case, the first photoresist layer pattern 106 may prevent the photoresist layer from being formed in a region other than the region where the via is formed, that is, the region where the trench etching is not performed, in the region where the upper metal wiring is to be formed.

Subsequently, as shown in FIG. 2C, a step 107 is formed by thinly etching the interlayer insulating layer 104 under the first photoresist layer pattern 106 with CxFy-activated plasma. Here, the trench etching thickness t2 of the interlayer insulating film 104 is (via depth + transient etching depth) / [(etch ratio of the interlayer insulating film to organic antireflection film) -1].

After the trench is etched, the first photoresist pattern 106 is removed.

Next, as shown in FIG. 2D, an organic antireflection film 108 is coated on the entire surface of the substrate by a spin coating method. Then, the organic antireflection film 108 is in a state where the surface thereof is flattened because of good fluidity characteristics and the step 107 of the interlayer insulating film is shallow.

2E and 2F, the second photoresist layer pattern 110 ′ is formed by applying a thick photoresist layer 110 on the organic antireflection layer 108 and performing a photo process such as exposure and development. do. Here, the second photoresist layer pattern 110 ′ prevents the photoresist layer from being present in the entire region where the upper metal wiring is made, that is, the region where the via plug and the upper metal wiring are not formed. At this time, the organic antireflection film 108 is left as it does not react with the light.

In addition, the dual damascene process of simultaneously etching the plug via and the metal wiring trench is performed according to the present invention with reference to FIGS. That is, the organic antireflection film 108 and the interlayer insulating film 104 are etched with the CxFy-activated plasma in accordance with the second photoresist layer pattern 110 ′ to simultaneously form the via and the upper wiring trench in the interlayer insulating film.

Accordingly, as shown in FIG. 2G, etching is performed using a plasma activated with CxFy, and the organic anti-reflective coating layer (II) is exposed until the surface of the interlayer insulating film 104 is exposed with a high etching ratio with respect to the second photoresist pattern 110 ′. 108 '). As a result, the organic anti-reflection film pattern 108 ′ remains in the interlayer insulating film 104 in the region where the trench is to be etched.

Next, as shown in FIG. 2H, an etching process is performed until the organic antireflection film 108 ′ embedded in the trench of the interlayer insulating film 104 is etched to form the vias 112 in the interlayer insulating film 104. At the same time, the organic antireflection film 108 'is removed. At this time, the interlayer insulating film in the trench portion of the upper metal wiring region is not etched because the organic antireflection film 108 'acts as a hard mask, but the remaining interlayer insulating film is well etched to increase the amount of etching.

Next, as shown in FIG. 2I, the etching process is continued to simultaneously form the via hole 112a and the upper wiring trench 112b in which the lower metal wiring bl surface is exposed in the interlayer insulating film. At this time, after the organic anti-reflection film 108 ′ is completely removed, the via 112a and the via 112a to the surface of the lower metal wiring bl are etched simultaneously in the interlayer insulating film. That is, the interlayer insulating film etching depth is the same.

Subsequently, as shown in FIG. 2J, Ti / TiN is deposited as the third anti-diffusion film 114 on the interlayer insulating film 104 on which the plug via 112a and the upper wiring trench 112b are formed. 116) sufficiently fills Al or Cu. Although not shown in the drawings, a diffusion barrier layer may be further stacked on the metal layer 116.

Next, as shown in FIG. 2K, CMP or plasma is used to planarize the entire surface while removing all of the metal layer 116 and the diffusion barrier layers 114 and 116 that exist on the interlayer insulating film surface other than the vias 112a and the trench 112b. The polishing process is performed by the front surface etching method by. As a result, the diffusion barrier film 114 'of Ti / TiN etched only in the vias 112a and the trenches 112b of the interlayer insulating film 104 and the metal 116' of Al or Cu are buried to form a lower metal wiring bl. The plug p and the upper metal wiring tl connected to each other are formed at the same time.

Subsequently, as shown in FIG. 2L, the surface of the resulting interlayer insulating film 118 is deposited to insulate the metal wiring to be formed later, and then the surface thereof is planarized.

By repeating such a wiring process, a multilayer wiring of the semiconductor device according to the present invention can be manufactured.

Therefore, the present invention facilitates photosensitive film patterning by applying an organic anti-reflective film after forming a step in the interlayer insulating film by etching a thin trench in advance to form a trench for metal wiring, and an organic anti-reflective film remaining in the region where the trench is etched. Is used as a hard mask to simultaneously etch the plug via and the metal wiring trench in the interlayer insulating film.

As described above, the method of forming the multi-layered metal wiring of the semiconductor device according to the present invention has the following effects.

First, the present invention can proceed with the etching of the plug via and the upper wiring trench at the same time can significantly reduce the number of manufacturing process compared to the existing wiring process can increase the yield of the manufacturing process and is effective in reducing the cost.

Second, when applied to a highly integrated semiconductor technology of 0.18㎛ or less, the use of an organic anti-reflection film can minimize misalignment with the lower patterns when patterning the photoresist and can realize a photoresist pattern having a good cross section. . That is, the photoresist patterning by exposure and development shows better results when proceeding on a flat plate and also secures process margins. In the method of the present invention, since the basic photoresist patterning is performed on the flat plate, the cross section of the photoresist pattern is good and the mismatch between the patterns of the upper part and the part can be minimized.

Third, compared to the conventional damascene method, most of the present invention concentrates on the photoresist patterning, so that the manufacturing process can be efficiently performed. That is, since general patterning of the photoresist film is difficult to accurately pattern in narrow via form rather than patterning in a wide wiring form, in the manufacturing process of the present invention, the via-type patterning is converted to trench-oriented trench patterning during photoresist patterning. Increase efficiency and process margins

Fourth, the present invention has the advantage of lowering the difficulty of photosensitive film patterning because the thickness can be reduced by the organic anti-reflection film during the photosensitive film patterning.

Claims (6)

In the multilayer wiring manufacturing method of a semiconductor device, Forming a lower metallization on the structure of the semiconductor substrate; Forming a planarized interlayer insulating film on an entire surface of the substrate on which the lower metal wiring is formed; Forming a first photoresist pattern on the substrate; Forming a step by thinly etching the interlayer insulating film under the first photoresist pattern with plasma activated CxFy; Removing the first photoresist pattern and applying an organic antireflection film to the entire surface of the resultant; Forming a second photoresist pattern on the organic antireflection film; Etching the organic anti-reflective film and the interlayer insulating film in accordance with the second photoresist pattern with a CxFy-activated plasma to simultaneously form vias and upper wiring trenches in the interlayer insulating film; And Embedding a metal in the interlayer insulating film on which the via and upper wiring trenches are formed and polishing the same, thereby forming a via plug and an upper wiring connected to the lower metal wiring at the same time. . The thickness of the first photoresist layer pattern is greater than or equal to (via depth + transient etching depth) / [(etch ratio of interlayer insulation layer to photoresist layer) × (interlayer insulation layer etching ratio to organic antireflection film) -1]. A method for forming a multilayer metal wiring in a semiconductor device, characterized in that the. The method of claim 1, wherein the trench etch thickness of the interlayer insulating layer under the first photoresist pattern is (via depth + transient etching depth) / [(etch ratio of the interlayer insulating film to the organic antireflection film) -1]. A method of forming a multi-layer metal wiring in a semiconductor device. The method of claim 1, wherein the etching of the organic anti-reflection film and the interlayer insulating film in accordance with the second photoresist film pattern comprises: Etching the entire surface of the organic antireflection film until the surface of the interlayer insulating film is exposed with a high etching ratio with respect to the second photoresist film; Performing an etching process until the organic antireflection film embedded in the trench of the interlayer insulating film is etched to form a via in the interlayer insulating film and to remove the organic antireflection film; And And continuing the etching process to form a via and an upper wiring trench in which the lower metal wiring surface is exposed in the interlayer insulating film. The method of claim 1, wherein the first photoresist layer pattern defines a via plug region connecting lower and upper metal interconnections. The method of claim 1, wherein the second photoresist pattern defines a region in which a via plug and an upper metal wiring are not formed.