JPH10229122A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of manufacturing semiconductor device by which the forming accuracy and fillability of wiring grooves and connecting holes can be improved, in simultaneously forming the wiring grooves and connecting holes by filling up the grooves and holes. SOLUTION: In a method of manufacturing semiconductor device, wiring grooves 5 for forming upper-layer wiring are formed, and at the same time, connecting holes 6 are formed in the grooves 5 so that the holes 6 may reach lower-layer wiring 6, such that an interlayer insulating film 2a and a mask layer 12 which becomes the etching mask of the wiring groves 5 are successively formed on the lower-layer wiring 1, and a resist mask 7 which becomes the etching mask of the connecting holes 6 is formed. Then the connecting holes 6 are partially formed by half-etching the insulating film 2a by using the mask 7 as an etching mask and, after the mask 7 has been removed, the insulating film 2a is further etched by using the mask layer 12 as an etching mask. After the formation, the grooves 5 and holes 6 are filled up with a wiring forming material.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method of manufacturing a semiconductor device in which a lower wiring layer and an upper wiring layer are connected by a connection hole filling technique.

[0002]

2. Description of the Related Art With the improvement in the integration of VLSI, the demands on fine processing technology are becoming more and more severe. In particular, with the recent adoption of multi-layer wirings, in devices having a wiring structure of five or six layers, development of embedded wiring technology such as dual damascene is urgently required.

In this dual damascene wiring, after forming a wiring groove for embedding a wiring and a connection hole connecting upper and lower wiring layers, both of them are buried with a wiring material, and the CMP (Che)
This is a technique of removing excess wiring material not embedded in the wiring groove by using a mechanical mechanical polish, and simultaneously forming a wiring and a plug in a connection hole.
According to this dual damascene wiring technology, the wiring and the plug can be formed at once, so that a significant reduction in process cost can be achieved.

FIG. 2 shows a method of forming a wiring by dual damascene wiring.

First, an interlayer insulating film 2a and a CMP stopper layer 3a are sequentially formed on the lower wiring 1 and a resist mask 4 is formed thereon in a pattern corresponding to the wiring groove 5 for forming the upper wiring (see FIG. 1). Figure (a). Note that the lower wiring 1
Is formed in the lower interlayer insulating film 2b, and is formed on the interlayer insulating film 2b in order to perform the CMP performed in the method of forming the upper wiring described later on the formation of the lower wiring 1. The stopper layer 3b for CMP is laminated.

Next, the interlayer insulating film 2a is etched using the resist mask 4 as an etching mask to form a wiring groove 5 (FIG. 1B).

Then, a resist mask 7 is formed in a pattern corresponding to the connection hole 6 opened in the wiring groove 5 (FIG. 1C), and the interlayer insulating film 2a is etched using the resist mask 7 as an etching mask. The connection hole 6 is formed so as to reach the lower wiring 1 (FIG. 4D).

After forming the wiring grooves 5 and the connection holes 6 in this manner,
These are buried with an upper layer wiring forming material 8 by a high-pressure reflow method or the like (FIG. 3E), and the excess wiring material 8 above the wiring groove 5 is cut off by CMP, whereby the lower layer wiring 1 and the upper layer wiring 9 are connected. The wiring structure connected by the plug 10 by filling the hole 6 is obtained (FIG. 6F).

[0009]

However, according to the conventional wiring forming method shown in FIG. 2, when forming the resist mask 7 for forming the connection hole 6, the wiring groove 5 is formed on the surface on which the resist mask 7 is formed. Therefore, there is a problem that the thickness of the resist mask 7 becomes non-uniform, resolution cannot be excellently obtained, and a desired mask pattern cannot be obtained with high accuracy.

The aspect ratio (height / diameter) of the connection hole 6 when the wiring groove 5 and the connection hole 6 are buried is substantially higher by the amount of the wiring groove 5 formed on the connection hole 6. Therefore, there is a problem that the connection hole 6 cannot be satisfactorily embedded. In particular, there is a problem in the embedding property due to the step at the corner 11 at the boundary between the connection hole 6 and the wiring groove 5.

These problems are caused by the upper wiring 9 and the plug 10
This is because existing technology cannot be applied to processing of a structure including a step of two layers.

For resolution of the resist mask 7, it is conceivable to reduce the level difference by making the interlayer insulating film 2a thin and making the wiring groove 5 shallow, but the wiring groove 5 is made shallow. Reduces the wiring cross-sectional area of the upper wiring 9,
This leads to an increase in wiring resistance. For this reason, the problem of the step cannot be solved by making the wiring groove 5 shallow.

In order to solve the problem of embedding, it is conceivable to reduce the level difference by making the wiring groove 5 shallower or to increase the diameter of the connection hole 6. As described above, the resistance of the upper wiring 9 increases, so that it cannot be used.
Increasing the diameter is not a realistic measure due to design rule constraints.

An object of the present invention is to solve the above-mentioned problems of the prior art. In a method of manufacturing a semiconductor device in which a wiring and a connection hole are simultaneously formed by filling a wiring groove and a connection hole, a method of manufacturing a semiconductor device is disclosed. It is an object of the present invention to improve the forming accuracy and the embedding property without making the groove shallow and without increasing the diameter of the connection hole.

[0015]

In order to achieve the above object, the present invention forms an interlayer insulating film on a lower wiring and serves as an etching mask for a wiring groove for forming an upper wiring on the interlayer insulating film. A mask layer is formed, and a resist mask serving as an etching mask for a connection hole opening in the wiring groove is formed thereon, and the connection hole is formed by half-etching the interlayer insulating film using the resist mask as an etching mask. By partially forming the resist mask, removing the resist mask, and further etching the interlayer insulating film using the mask layer as an etching mask, a wiring groove is formed and the connection hole is formed so as to reach the lower wiring. And a method of manufacturing a semiconductor device, wherein a connection hole is filled with a material for forming an upper layer wiring.

In the present invention, a mask layer serving as an etching mask for the wiring groove for forming the upper wiring is formed on the interlayer insulating film, and the formation position of the wiring groove is determined. Next, a resist mask serving as an etching mask for forming a connection hole is formed. The formation of this resist mask
This is performed before the wiring groove is etched in the interlayer insulating film using the mask layer. Therefore, when a resist mask for forming a connection hole is formed, the step present on the formation surface is only due to the thickness of the mask layer. It does not appear as a step. Therefore, it is possible to eliminate poor resolution caused by a step on the surface on which the resist mask is formed.

Further, in the present invention, after partially forming the connection hole, the wiring groove and the connection hole are simultaneously formed by etching the interlayer insulating film using a mask layer serving as an etching mask for the wiring groove. Thus, the connection hole reaches the lower wiring. In this etching, the end of the connection hole on the wiring groove side, which has been the corner 11 in the related art (see FIG. 2E), is exposed to ions to be etched, becomes tapered, and the opening of the connection hole is opened. The diameter increases toward the wiring groove. Therefore, in the subsequent embedding of the wiring material into the wiring groove and the connection hole, the embedding property is greatly improved.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail with reference to the drawings. In each of the drawings, the same reference numerals represent the same or equivalent components.

FIG. 1 is a process explanatory view of a manufacturing method according to one embodiment of the present invention.

In the present invention, first, an interlayer insulating film 2a is formed on the lower wiring 1, and a mask layer 12 serving as an etching mask for the wiring groove 5 for forming the upper wiring is formed on the interlayer insulating film 2a.

Here, the material for forming the lower wiring 1, the interlayer insulating film 2a, and the upper wiring 9 described later is not particularly limited, and a material conventionally used in a high-density multilayer wiring board such as an LSI may be used. Can be. In forming them, a base layer may be formed as necessary. For example,
The lower wiring 1 and the upper wiring 9 are made of Al, Al-Cu, Al-
Al alloys such as Si, Al-Si-Cu, Al-Ge, A
It can be formed by forming a wiring material such as g, Cu, Cu-Zr, Ti, and TiN by a sputtering method or the like. In this case, the wiring layer may have a stacked structure of a plurality of types of wiring layers.

In the present invention, the lower wiring 1 includes not only a normal wiring layer but also a contact pad of a substrate.

As the interlayer insulating film 2a, for example, p-T
EOS (p-Tetraethyloxysilan
e), BPSG (Borophosphoslica)
teglass), PSG, BSG, AsSG, NSG
SiO ₂ based film and, fluorinated polyallyl ethers etc., polytetrafluoroethylene, BCB (Benzocycl
low dielectric constant organic material such as an organic compound. In particular, SiO such as p-TEOS, BPSG, etc.
₂ based film and fluorinated polyallyl ethers, low dielectric constant organic material such as polytetrafluoroethylene is preferable.

The mask layer 12 can be formed using a material having a high etching selectivity with respect to the interlayer insulating film 2a. Preferably, it is formed from a material for forming a stopper layer of CMP, and more specifically, is formed from SiN or the like. Thus, the mask layer 1 is formed from the material for forming the CMP stopper layer.
By forming 2, after the upper wiring 9 is formed, the upper surface thereof can be polished flat by CMP.

When a CMP stopper layer is used as the mask layer 12, a method of forming the mask layer 12 into a predetermined pattern so as to serve as an etching mask for the wiring groove 5 for forming the upper layer wiring is performed by a known CMP stopper layer. As shown in FIG. 1A, a solid stopper layer (mask layer 12) is formed on the interlayer insulating film 2a, and a resist mask 4 having a pattern corresponding to the wiring groove 5 is formed thereon. Then, using the resist mask 4 as an etching mask, the stopper layer (mask layer 12) may be etched as shown in FIG.

After that, the resist mask 4 is removed, and as shown in FIG.
A resist mask 7 is formed so as to serve as an etching mask. In the formation of the resist mask 7, the step existing on the formation surface is only due to the thickness of the mask layer 12. Therefore, this step does not cause a resolution failure in the resist mask 7 and does not lower the precision of forming the connection holes 6.

Next, as shown in FIG. 1D, the connection hole 6 is partially formed by half-etching the interlayer insulating film 2a using the obtained resist mask 7 as an etching mask. At this time, the etching depth h1 of the interlayer insulating film 2a is larger than the height h2 of the plug 10 formed by filling the connection hole 6, and the interlayer insulating film 2a
Thickness h3. If the depth h1 of the half-etching of the connection hole 6 is not enough, the connection hole 6 will remain in the lower layer wiring 1 even after the wiring groove 5 is etched as described later.
Do not reach.

If the depth h1 of the half etching is larger than the height h2 of the plug 10 formed by filling the connection hole 6, the bottom of the connection hole 6 is etched until the wiring groove 5 is etched to a predetermined depth. In this case, the lower wiring 1 is over-etched, but by appropriately setting the etching selectivity between the lower wiring 1 and the interlayer insulating film 2a, the problem of over-etching at the bottom of the connection hole 6 can be avoided. it can.

Next, as shown in FIG. 2E, the resist mask 7 is removed, and the interlayer insulating film 2a is further etched using the mask layer 12 (stopper layer) as an etching mask. As shown in ()), the wiring groove 5 is formed, and the connection hole 6 reaches the lower layer wiring 1.
The wiring groove 5 and the connection hole 6 thus obtained are the ends of the connection hole 6 on the wiring groove 5 side, as shown in the figure, and the portion which has conventionally been the corner 11 (see FIG. 2E) , And the diameter of the opening of the connection hole 6 increases toward the wiring groove 5. Here, the tapered end of the connection hole 6 on the side of the wiring groove 5 can be obtained under any etching method or any etching condition performed for etching the interlayer insulating film 2a. The degree of the taper can be changed by an etching method or etching conditions.

After the wiring groove 5 and the connection hole 6 are formed, a wiring material is buried therein by a high-pressure reflow method, a high-temperature sputtering method or the like, and if necessary, unnecessary wiring above the wiring groove 5 is formed by, for example, CMP. The material is shaved and the substrate surface is flattened. Thus, the upper layer wiring 9 is formed in the wiring groove 5 and the plug 10 is formed in the connection hole 6. In this embedding, the end of the connection hole 6 on the wiring groove 5 side is tapered as described above. Therefore, the embedding property of the wiring material into the wiring groove 5 and the connection hole 6 is greatly improved.

During the process of forming the upper wiring 9 and the plug 10 by filling the wiring groove 5 and the connection hole 6 as described above, a preheating treatment, an oxide film removal treatment, and the like can be appropriately performed as necessary.

The method of the present invention can be applied to the case where the lower wiring 1 and the upper wiring 9 are connected, and then the upper wiring 5 and the upper wiring are connected.

[0033]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be specifically described below based on embodiments.

Example 1 According to the process shown in FIG. 1, a multilayer wiring structure of a semiconductor device was formed as follows.

(1) As a sample substrate, the lower wiring 1
A low dielectric (organic polymer) as an interlayer insulating film 2a and SiN as a mask stopper 12 as a CMP stopper
(Layer thickness: 0.2 μm), and further, a resist mask 4 was laminated in a pattern corresponding to the wiring groove 5 to produce a product.

Here, the total thickness of the interlayer insulating film 2a and the mask layer 12 is 1.5 μm, and this thickness is equal to the depth h 4 (0.5 μm) of the upper wiring 9 formed in this embodiment. ) And the height h2 of the plug 10 (1.0 μm).

(2) The mask layer 12 (SiN layer) of the sample substrate was etched using a magnetron type etching apparatus under the following conditions, and a pattern corresponding to the wiring groove 5 was opened (FIG. 1 (b)). )). Etching conditions RF 1000 W Pressure 3 Pa Substrate temperature 20 ° C. Etching gas CHF ₃ / CO / Ar = 30/100 /
100sccm

(3) The resist mask 4 having a pattern corresponding to the wiring groove 5 was peeled off, and a resist mask 7 was newly formed in a pattern corresponding to the connection hole 6.

(4) Using an ECR type etching apparatus under the following conditions, the connection hole 6 was partially formed by half-etching the interlayer insulating film 2a using the resist mask 7 as an etching mask (etching depth h).
1 = 1.2 μm) (FIG. 1 (d)). Etching conditions Microwave 800 W Pressure 0.5 Pa Substrate temperature −50 ° C. Etching gas C ₄ F ₈ / O ₂ / Ar = 2/50/100
sccm

(5) The resist mask 7 was removed. Then, under the same etching conditions as in (4) above, the interlayer insulating film 2a is further etched using the mask layer 12 (SiN layer) as an etching mask to form the wiring groove 5, and the connection hole 6 reaches the lower wiring 1. (Figure 1
(F)). The connection hole 6 thus obtained is connected to the wiring groove 5
The end on the side became tapered, and the opening diameter of the connection hole 6 was widened toward the wiring groove 5.

(6) Al—Cu is buried in the wiring groove 5 and the connection hole 6 as a wiring material.
By P, the desired multilayer wiring structure was obtained.

Example 2 A multilayer wiring structure of a semiconductor device was formed as follows in the same manner as in Example 1 except that p-TEOS was used as the interlayer insulating film 2a.

(1) p-TEO as interlayer insulating film 2a
A sample substrate was produced in the same manner as in Example 1 except that S was used.

(2) The mask layer 12 (SiN layer) of the sample substrate was etched by using a magnetron type etching apparatus under the same conditions as in Example 1 (2), and a pattern corresponding to the wiring groove 5 was opened. (FIG. 1 (b)).

(3) The resist mask 4 having a pattern corresponding to the wiring groove 5 was peeled off, and a resist mask 7 was newly formed in a pattern corresponding to the connection hole 6.

(4) Using a magnetron-type etching apparatus under the following conditions, the interlayer insulating film 2a is half-etched using the resist mask 7 as an etching mask to partially form the connection hole 6 (etching depth h1). = 1.2 μm) (FIG. 1 (e)). Etching conditions RF 1000 W Pressure 3 Pa Substrate temperature 20 ° C. Etching gas C ₄ F ₈ / CO / Ar / O ₂ = 10/20
0/100 / 5sccm

(5) The resist mask 7 was removed. Then, using the same magnetron type etching apparatus as in the above (4), under the following etching conditions, p-T is used with the mask layer 12 (SiN layer) as an etching mask.
The interlayer insulating film 2a made of EOS is further etched,
The wiring groove 5 was formed, and the connection hole 6 reached the lower wiring 1 (FIG. 1F). Etching conditions RF 1000 W Pressure 3 Pa Substrate temperature 20 ° C. Etching gas C ₄ F ₈ / CO / Ar / O ₂ = 10/20
0/100 / 20sccm

The connection hole 6 thus obtained has a tapered end on the side of the wiring groove 5, and the opening diameter of the connection hole 6 increases toward the wiring groove 5.

(6) Al-Cu is buried in the wiring groove 5 and the connection hole 6 as a wiring material, and the upper part thereof is CM
By P, the desired multilayer wiring structure was obtained.

[0050]

According to the present invention, in a method of manufacturing a semiconductor device in which a wiring and a connection hole are simultaneously formed by embedding the wiring groove and the connection hole, the wiring groove is not made shallow and the diameter of the connection hole is reduced. It is possible to improve the forming accuracy and the embedding property without increasing the size.

[Brief description of the drawings]

FIG. 1 is a process explanatory view of the present invention.

FIG. 2 is a process explanatory view of a conventional example.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Lower wiring, 2a ... Interlayer insulating film, 3a ... CMP stopper layer, 4 ... Resist mask, 5 ... Wiring groove, 6 ... Connection hole, 7 ... Resist mask, 8 ... Upper wiring forming material, 9 ...
Upper wiring, 10 plug, 11 corner, 12 mask layer (CMP stopper layer)

Claims (7)

[Claims] An interlayer insulating film is formed on a lower wiring, a mask layer serving as an etching mask for a wiring groove for forming an upper wiring is formed on the interlayer insulating film, and an opening is formed in the wiring groove. Forming a resist mask that serves as an etching mask for the connection hole to be formed, partially forming the connection hole by half-etching the interlayer insulating film using the resist mask as an etching mask, removing the resist mask, and removing the mask layer. A semiconductor, characterized in that a wiring groove is formed by further etching the interlayer insulating film as an etching mask, a connection hole is formed so as to reach a lower wiring, and the wiring groove and the connection hole are buried with an upper wiring forming material. Device manufacturing method. 2. The method according to claim 1, wherein the mask layer comprises a CMP stopper layer. 3. After the wiring trenches and the connection holes are buried, CMP is performed.
3. The method according to claim 2, wherein the surface is flattened. 4. The method according to claim 1, wherein the interlayer insulating film is made of a SiO ₂ material. 5. The method according to claim 1, wherein the SiO ₂ material is p-TEOS or BP.
The method according to claim 4, wherein the method is selected from SG. 6. The method according to claim 1, wherein the interlayer insulating film is made of a low dielectric constant organic material having a dielectric constant of 4 or less. 7. The method according to claim 6, wherein the low dielectric constant organic material is selected from fluorinated polyallyl ether and polytetrafluoroethylene.