KR20090024854A - Metal line and method for fabricating metal line of semiconductor device - Google Patents

Metal line and method for fabricating metal line of semiconductor device Download PDF

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Publication number
KR20090024854A
KR20090024854A KR1020070089738A KR20070089738A KR20090024854A KR 20090024854 A KR20090024854 A KR 20090024854A KR 1020070089738 A KR1020070089738 A KR 1020070089738A KR 20070089738 A KR20070089738 A KR 20070089738A KR 20090024854 A KR20090024854 A KR 20090024854A
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KR
South Korea
Prior art keywords
film
metal wiring
forming
interlayer insulating
trench
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KR1020070089738A
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Korean (ko)
Inventor
정영석
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주식회사 동부하이텍
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Priority to KR1020070089738A priority Critical patent/KR20090024854A/en
Publication of KR20090024854A publication Critical patent/KR20090024854A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The embodiment relates to a method for forming metal wiring of a semiconductor device, and more particularly, to a method for forming metal wiring of a semiconductor device in which a scratch on a surface of a copper wiring is prevented from causing a short failure of copper wirings formed in a subsequent process. . In the method of forming a metal wiring of a semiconductor device according to the embodiment, forming an interlayer insulating film on a semiconductor substrate, selectively removing the interlayer insulating film so as to expose a portion of the surface of the semiconductor substrate to form via holes and trenches, Forming a metal film on the entire surface including the trench and the via hole, forming a metal wiring on the inside of the trench and the via hole by first polishing the front surface of the metal film, and forming a compensation film on the entire surface of the semiconductor substrate on which the metal wiring is formed And secondly polishing the entire surface of the compensation layer to planarize the metal wiring.

Description

Metallization of Semiconductor Devices and Formation Method {METAL LINE AND METHOD FOR FABRICATING METAL LINE OF SEMICONDUCTOR DEVICE}

The embodiment relates to metal wiring of a semiconductor device and a method of forming the same.

In general, in semiconductor devices, electronic devices, and the like, a conductor film such as aluminum (Al) or tungsten (W) is deposited on an insulating film as a wiring forming technique, and then the conductor film is subjected to a conventional photolithography process and a dry method. A technology of forming a wiring by patterning through a dry etching process has been established and widely used in this field. In particular, in recent years, a low resistivity metal such as copper (Cu) instead of aluminum (Al) or tungsten (W) as a part of reducing RC delay time centering on logic devices that require high speed among semiconductor devices. Has been studied to use a wire as a wiring.

However, in the wiring forming process using copper (Cu), the copper (Cu) patterning process is more difficult than that of aluminum (Al) or tungsten (W). After the trench is formed, the trench is buried to form wiring. The so-called 'Damascene' process is used.

In the damascene process, after forming a via hole, filling the via conductor again, forming a wiring trench to fill the wiring, a single damascene process, and forming a via hole and a trench, At the same time, there is a dual damascene process in which wiring materials are refilled in via holes and wiring trenches to form wiring. In general, the dual damascene process is superior to the single damascene process in terms of process simplification.

In the dual damascene process, a pre-via method for forming a trench after forming a via hole first, and a post-via method for forming a via hole after forming a wiring trench are known. In general, the sun via method is superior to the post via method to ensure electrical contact with the lower layer.

1 to 3 are cross-sectional views illustrating a method of forming a copper wiring according to the prior art.

As shown in FIG. 1, when the lower layer 1, which is a conductive region, is formed on the semiconductor substrate, a first interlayer insulating layer 10 is formed on the lower layer 1, and then a via hole is formed by a dual damascene process. And form a trench. The dual niacin process is a photolithography process in which a photoresist, a photosensitive material, is coated, patterned, and then etched using the mask as a mask.

Although not shown in the drawing, the first interlayer insulating layer 10 has a structure in which an etch stop layer and an insulating layer are sequentially stacked like the second interlayer insulating layer to be formed in a later process.

When the via hole and the trench are formed on the lower layer 10 as described above, the barrier layer is formed by using Ti, TiN, Ta, or TaN on the entire structure including the via hole and the inner surface of the trench (ie, including the inner surface or the lower surface). Form a layer (not shown).

Then, a copper seed layer (not shown) is formed on the barrier layer to form copper wiring, and copper is embedded in the via hole and the trench region according to an ECP (Erectrode Copper Plating) process.

As such, when copper is embedded in the via hole and the trench, annealing is performed to crystallize the copper formed by electroplating, followed by chemical mechanical polishing (CMP), and finally the first copper wiring. 20 is formed.

In the CMP process, the surface is polished so that copper exists only in the via hole and the trench region formed on the lower layer 1, and the deposited copper is removed in other regions.

However, unlike the case of using tungsten (W) or aluminum (Al) wiring, there is a problem that frequent scratches 30 occur on the surface of the first copper wiring 20 due to the ductile copper properties. Such a scratch 30 defect causes a short defect of the copper wirings formed later.

2 and 3, when the first copper wiring 20 is formed, an etch stopper layer 115a and a first insulating film are formed on the lower layer 1 on which the first copper wiring 20 is formed. 15b), the second insulating film 15c, and the third insulating film 15d are sequentially deposited in accordance with a chemical vapor deposition process to form a second interlayer insulating layer 15.

In this case, since the insulating layers are formed along the scratches 30 generated on the surface of the first copper wiring 20, grooves (notches) are formed on the surface corresponding to the scratches 30, which are subsequently transferred to thereby It is shown as a groove 31 on the second interlayer insulating layer 15.

If the groove 31 is formed on the second interlayer insulating layer 15 as described above, when the metal is formed by the ECP process after the via hole and the trench are formed, not only the via hole and the trench region but also the inside of the groove 31 remain. Remain copper 45 is formed.

The remaining copper 45 formed inside the groove 31 is a bridge for shorting between the second copper wires 40 when the second copper wires 40 are formed by the copper crystallization process and the CMP process. It will play a role.

As such, scratches generated on the surface of the flexible copper wiring affect subsequent wiring processes and short circuits formed in a later process, resulting in a decrease in the yield of semiconductor devices.

The embodiment provides a method for metal wiring and formation of a semiconductor device capable of recovering scratches on metal wiring.

The embodiment provides a method for forming a metal wiring of a semiconductor device in which a scratch generated on a surface of a copper wiring during a semiconductor manufacturing process is prevented from being transferred to a subsequent process, thereby preventing short defects between wirings.

In the method of forming a metal wiring of a semiconductor device according to the embodiment, forming an interlayer insulating film on a semiconductor substrate, selectively removing the interlayer insulating film so as to expose a portion of the surface of the semiconductor substrate to form via holes and trenches, Forming a metal film on the entire surface including the trench and the via hole, forming a metal wiring on the inside of the trench and the via hole by first polishing the front surface of the metal film, and forming a compensation film on the entire surface of the semiconductor substrate on which the metal wiring is formed And secondly polishing the entire surface of the compensation layer to planarize the metal wiring.

The metallization of the semiconductor device according to the embodiment may include an interlayer insulating film formed on a semiconductor substrate, a via hole formed to expose a portion of the surface of the semiconductor substrate to the interlayer insulating film, and a trench formed to a predetermined depth in a region adjacent thereto, and the via hole. And a metal wiring formed in the tweezers and having a groove formed in a part of the surface thereof, and a compensation film pattern formed in the groove to planarize the surface of the metal wiring.

In the embodiment, since the scratches generated in the metal wiring can be recovered, the device yield is improved, and the performance of the device is improved.

Hereinafter, exemplary embodiments will be described in detail with reference to the accompanying drawings. However, one of ordinary skill in the art who understands the spirit of the present invention may easily propose another embodiment by adding, adding, deleting, or modifying elements within the scope of the same spirit, but this also belongs to the scope of the present invention. I will say.

With reference to the accompanying drawings will be described in detail the metal wiring and the method of forming the semiconductor device according to the embodiments. Hereinafter, when referred to as "first", "second", and the like, this is not intended to limit the members but to show that the members are divided and have at least two. Thus, when referred to as "first", "second", etc., it is apparent that a plurality of members are provided, and each member may be used selectively or interchangeably. In addition, the size (dimensions) of each component of the accompanying drawings are shown in an enlarged manner to help understanding of the invention, the ratio of the dimensions of each of the illustrated components may be different from the ratio of the actual dimensions. In addition, not all components shown in the drawings are necessarily included or limited to the present invention, and components other than the essential features of the present invention may be added or deleted. In the description of an embodiment according to the present invention, each layer (film), region, pattern or structure is "on / above / over / upper" of the substrate, each layer (film), region, pad or patterns or In the case described as being formed "down / below / under / lower", the meaning is that each layer (film), region, pad, pattern or structure is a direct substrate, each layer (film), region, It may be interpreted as being formed in contact with the pad or patterns, or may be interpreted as another layer (film), another region, another pad, another pattern, or another structure formed in between. Therefore, the meaning should be determined by the technical spirit of the invention.

4 through 11 are cross-sectional views illustrating a method of forming metal wirings in a semiconductor device in accordance with an embodiment.

Here, the substrate 100 may be a semiconductor substrate on which wells and junctions are formed, an insulating film including a lower metal wiring 110 in a multilayer metal wiring structure, or a semiconductor including a conductive pattern used as an electrode of other semiconductor devices. It may be a substrate.

As shown in FIG. 4, an interlevel dielectric 114 is formed on the substrate 100.

For example, the interlayer insulating layer 114 may be deposited to a thickness of 6500 kV to 8500 kV.

The lower metal wiring 110 may be formed on the substrate 100 in a multi-layer metal wiring structure, and the lower metal wiring 110 and the copper metal wiring to be formed later are connected through the interlayer insulating layer 114. It may be formed into a structure.

The interlayer insulating layer 114 is formed by depositing a material having a low dielectric constant such as fluorinated silicate glass (FSG) by plasma enhanced chemical vapor deposition (PECVD).

Meanwhile, an etching stop layer 112 may be formed on the substrate 100 to prevent etching before forming the interlayer insulating layer 114.

The etch stop layer 112 may include silicon nitride (SiN).

A photoresist pattern is formed on the interlayer insulating layer 114, and the via hole 116 is formed by etching the interlayer insulating layer 114 using the photoresist pattern as a mask.

The via hole 116 may expose a portion of the lower metal wire 110 to be electrically connected, for example.

A protective layer made of a novolac or bottom anti-reflective coating (BARC) is formed in the via hole 116.

The interlayer insulating layer 114 is etched to form a trench 119 on the via hole 116 to remove the protective layer.

The interlayer insulating layer 114 on which the via hole 116 and the trench 119 are formed exposes a portion of the etch stop layer 112.

The via hole 116 and the trench 119 may be formed by etching the interlayer insulating layer 114 by a plasma etching process. In the etching process, an F-based gas (eg, CF 4, etc.) may be used, or CO or oxygen may be used or a mixture thereof may be used.

The photoresist pattern that may remain on the interlayer insulating layer 114 on which the via holes 116 and the trench 119 are formed may be removed by an ashing process. The etching process is performed by plasma etching according to a set ashing rate.

As shown in FIG. 5, a portion of the exposed etch stop layer 112 is etched.

As illustrated in FIG. 6, a first barrier layer 122 is formed on the interlayer insulating layer 114 on which the via hole 116 and the trench 119 are formed.

The first barrier layer 122 may be formed of one material selected from the group of TiSiN, TaSiN, Ta, TaN, TaAlN, TaSiN, Ti, TiN, WN, TiSiN, TCu, and the like.

 The first barrier layer 122 may be formed by physical vapor deposition or chemical vapor deposition, and may be deposited to a thickness of 10 kV to 1000 kV.

The first barrier film 122 serves to prevent copper atoms from the later formed copper metal film from diffusing into the interlayer insulating film 34.

The first barrier film 122 serves to prevent copper atoms from the copper metal film formed later from diffusing into the interlayer insulating film 114.

As shown in FIG. 7, a seed film 123 is formed on the first barrier film 122. The seed film 123 includes at least one selected from the group consisting of Al, Cu, Ti, and Ta.

As shown in FIG. 8, a copper metal film 124 is formed on the interlayer insulating film 114 on which the seed film 123 is formed.

The copper metal film 124 may be formed by, for example, electroplating, or may be formed by PVD or CVD (chemical vapor deposition).

Thereafter, as shown in FIG. 9, the copper metal layer 124 is planarized to form a copper metal interconnection 124a in the via hole 116 and the trench 119.

That is, the first barrier layer pattern 122a, the seed layer pattern 123a, and the copper remaining in the via hole 116 and the trench 119 by chemical mechanical polishing of the copper metal layer 124. The metal wiring 124a can be formed.

In the chemical mechanical polishing process, the first barrier film 122 and the seed film 123 formed on the interlayer insulating film 114 are also polished and removed, so that the interlayer insulating film is formed in a region other than the copper metal wiring 124a. The top surface of 114 is exposed.

At this time, the copper metal wire 124a may have a groove 145 due to scratches on the surface of the copper metal wire 124a due to abrasive particles or particles due to the property of copper having ductility.

As shown in FIG. 10, a second barrier layer 125 is formed on the copper metal wire on which the groove 145 is generated.

The compensation layer 126 is formed on the second barrier layer 125.

The second barrier layer 125 may be made of one material selected from the group of TiSiN and TaSiN, Ta, TaN, TaAlN, TaSiN, Ti, TiN, WN, TiSiN, TCu, etc. Can be done.

The compensation layer 126 fills the groove 145 generated on the surface of the copper metal wiring 124a by a scratch or the like to flatten the surface of the copper metal wiring 124a and compensate for the missing portion.

The compensation layer 126 may include, for example, copper. The compensation film 126 may be a copper seed film or a copper metal film.

The compensation layer 126 may be formed by, for example, electroplating or the like, or may be formed by a PVD method or a chemical vapor deposition (CVD) method.

The second barrier layer 125 may have a thickness of 50 μs to 1000 μs. The compensation film 126 may have a thickness of about 50 kPa to about 2000 kPa.

The thickness of the second barrier layer 125 and the compensation layer 126 may be determined by the depth of the groove 145 formed on the surface of the copper metal wire 124a.

The second barrier layer pattern 125a and the compensation layer are formed in the groove 145 by chemical mechanical polishing of the entire surface of the semiconductor substrate on which the second barrier layer 125 and the compensation layer 126 are formed. Pattern 126a may be formed.

In the chemical mechanical polishing process, the second barrier layer 125 and the compensation layer 126 formed on the interlayer insulating layer 114 are also polished to expose the top surface of the interlayer insulating layer 114.

Accordingly, the second barrier layer pattern 125a and the compensation layer pattern 126a are formed in the groove 145 of the copper metal interconnection 124a, and the entire upper surface of the copper metal interconnection 124a is flat and scratches are restored. ) Can be formed.

Although described above with reference to the embodiments, which are merely examples and are not intended to limit the present invention. Those skilled in the art to which the present invention pertains are not exemplified above without departing from the essential characteristics of the present invention. It will be appreciated that many variations and applications are possible. For example, each component specifically shown in the embodiment of the present invention can be modified. And differences relating to such modifications and applications will have to be construed as being included in the scope of the invention defined in the appended claims.

1 to 3 are cross-sectional views illustrating a method of forming a copper wiring according to the prior art.

4 through 11 are cross-sectional views illustrating a method of forming metal wirings in a semiconductor device in accordance with an embodiment.

<Description of Signs of Major Parts of Drawings>

100: substrate 110: lower metal wiring

112: etch stop film 114: interlayer insulating film

116: via hole 119: trench

122: first barrier film 123: seed film

124: copper metal film 124a: copper metal wiring

125: second barrier film 125a: second barrier film pattern

126: compensation film 126a: compensation film pattern

145: home

Claims (10)

Forming an interlayer insulating film on the semiconductor substrate; Selectively removing the interlayer insulating layer to expose a portion of the surface of the semiconductor substrate to form via holes and trenches; Forming a metal film on the entire surface including the trench and the via hole; First grinding the entire surface of the metal film to form metal wirings in the trench and the via hole; Forming a compensation film on an entire surface of the semiconductor substrate on which the metal wiring is formed; And And polishing the entire surface of the compensation layer to planarize the metal wiring. The method of claim 1, The thickness of the compensation film is 50 kW to 2000 kW metal wiring forming method of a semiconductor device, characterized in that. The method of claim 1, Before forming the compensation film, Forming a barrier film on the entire surface of the semiconductor substrate on which the metal wiring is formed. The method of claim 3, wherein And the barrier film has a thickness of 50 kV to 1000 kV. The method of claim 1, A groove is formed in a part of the surface of the metal wiring during the primary polishing, and the compensation film pattern is formed in the groove during the secondary polishing. The method of claim 1, The barrier film may include at least one selected from TiSiN, TaSiN, Ta, TaN, TaAlN, TaSiN, Ti, TiN, WN, TiSiN, and TCu. An interlayer insulating film formed on the semiconductor substrate; A trench formed in the interlayer insulating layer so as to expose a predetermined portion of the surface of the semiconductor substrate and a trench formed in a region adjacent to the via hole; A metal wiring formed in the via hole and the trench and having a groove formed in a portion of a surface thereof; And And a compensation film pattern formed in the groove and planarizing the surface of the metal wiring. The method of claim 7, wherein The metal wiring of the semiconductor device, characterized in that the metal wiring and the compensation layer pattern comprises copper. The method of claim 7, wherein A first barrier film pattern formed between the interlayer insulating film and the metal wiring; And a second barrier layer pattern formed between the metal line and the compensation layer pattern. The method of claim 9, The thickness of the second barrier layer pattern is 50 kW to 1000 kW metal wiring of the semiconductor device.
KR1020070089738A 2007-09-05 2007-09-05 Metal line and method for fabricating metal line of semiconductor device KR20090024854A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102971834A (en) * 2010-07-08 2013-03-13 美国国家半导体公司 Via with a substantially planar top surface
KR20170070353A (en) * 2015-12-11 2017-06-22 삼성전자주식회사 Semiconductor device and method of manufacturing the same
US20190229078A1 (en) * 2018-01-19 2019-07-25 Samsung Electro-Mechanics Co., Ltd. Semiconductor package

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102971834A (en) * 2010-07-08 2013-03-13 美国国家半导体公司 Via with a substantially planar top surface
KR20170070353A (en) * 2015-12-11 2017-06-22 삼성전자주식회사 Semiconductor device and method of manufacturing the same
US20190229078A1 (en) * 2018-01-19 2019-07-25 Samsung Electro-Mechanics Co., Ltd. Semiconductor package
KR20190088699A (en) * 2018-01-19 2019-07-29 삼성전자주식회사 Semiconductor package
US10741510B2 (en) 2018-01-19 2020-08-11 Samsung Electronics Co., Ltd. Semiconductor package
TWI712132B (en) * 2018-01-19 2020-12-01 南韓商三星電子股份有限公司 Semiconductor package

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