JP2000195951A - Manufacture of double damask structure in integrated circuit having multiple level mutually connected structures - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent a group of metallic atoms from spreading into a dielectric layer deposited on the sidewall of a double damask hole by forming an isometric barrier/an adhesive layer prior to performing the RIE treatment for exposing a metallized layer. SOLUTION: After formation of a double damask hole to expose a superposed layer 204, first an isometric barrier / an adhesive layer 216 is made, covering the whole sidewall of the double damask hole, in such a way as not to stop the double damask layer. Next, the bottom of the isometric barrier / adhesive layer 216 lying on the bottom of the double damask hole, and subsequently, the underlying section of the superposed layer 204 is removed until the metallized layer 204 is exposed by anisotropic etching processing. Lastly, conductive material 218 such as copper or the like is deposited on the residual cavity section of the double damask hole. The double damask structure is constituted of the combination of the deposited conductive material 218 and the residual section of the isotropic barrier / the adhesive layer within the double damask hole.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

FIELD OF THE INVENTION The present invention relates to semiconductor fabrication techniques and, more particularly, to a method of fabricating a dual damascene structure in an integrated circuit having a multilevel interconnect structure.

[0002]

BACKGROUND OF THE INVENTION In order to incorporate more transistor components on the same chip, high density integrated circuits are usually built on multi-level interconnect structures having more than one circuit layer.
The multilevel interconnect structure includes two or more metallization layers separated by an intermetal dielectric (IMD) layer, with adjacent metallization layers being metal plugs (also known as vias) formed between the IMD layers. (Known) groups. Conventional multilevel interconnect fabrication methods include a first step of forming a first level metallization layer and a second step of forming an IMD layer over the first level metallization layer.
Steps, a third step of forming a metal plug at a predetermined location of the IMD layer electrically connected to the first level metallization layer, and a final step of forming a second level metallization layer on the IMD layer Consists of More metallization layers can be formed on the second level metallization layer to form a multi-level interconnect structure.

In the above method, the metal plug and the metallization layer are separately formed by different steps. In a conventional method called double damascene technology, metal plugs and metallization layers are formed in one deposition step.

The feature of this technology is that, within the same IMD layer,
A horizontally extending groove and a vertically extending via hole are formed together, and metal is deposited in this groove through the via hole,
That is, the metal deposited in the via hole functions as a metal plug, and the metal deposited in the groove functions as a metallization layer. A structure combining a metal plug and a metallization layer is called a double damascene structure. This technique allows for easier and simpler fabrication of multilevel interconnect structures and lowers manufacturing costs.

A conventional method of manufacturing a double damascene structure in an integrated circuit is shown in detail in FIGS. 1 to 5 below. In a first step shown in FIG. 1, a semiconductor substrate 100 is prepared. Next, a first level metallization layer 102 is formed at a predetermined location in the semiconductor substrate 100, preferably with copper. Next, a first overlaid layer 104 is formed on the semiconductor substrate 100. This first overlying layer 104 covers the first level metallization layer 102 so that the metal atoms in the first level metallization layer 102 are formed in a subsequently formed dielectric layer (ie, as shown in FIG. 2). Diffusion to the dielectric layer 106).

In a second step, shown in FIG. 2, a thick dielectric layer 106 is formed over the first overlying layer 104. Next, a selective removal process is performed and the dielectric layer 106 is removed.
A double damascene hole 107 is formed in the first overlying layer 1.
The portion of 04 above the first level metallization layer 102 is exposed. Since this selective removal process is a conventional technique,
A detailed description of that step is omitted. The double damascene hole 107 provides a wide top 11 for forming the second metallization layer.
4 and a narrow bottom 112 for forming a metal plug. Since the second level metallization layer and the metal plug are formed together, the structure of these combinations will be referred to hereinafter as a double damascene structure.

In the third step shown in FIG.
An anisotropic etching process such as a (reactive ion etching) process is performed, and the exposed portion of the first overlying layer 104 is etched until the first level metallization layer 102 is exposed. This process further extends the narrow bottom 112 of the double damascene hole 107 to expose the first level metallization 102.

In a fourth step, shown in FIG. 4, double damascene holes 107 in dielectric layer 106 and exposed portions of first level metallization layer 102 are The conformal barrier / adhesive layer 116 over the exposed surface of the wafer, including the sidewalls of FIG.
Is formed to a predetermined thickness. Next, a metal such as copper is deposited to fill the remaining space of the double damascene hole 107 (FIG. 2) and cover the top surface of the conformal barrier / adhesive layer 116 with a predetermined thickness. The conductive layer 118 is formed by the deposited metal.

In a fifth step, shown in FIG. 5, a chemical mechanical polishing (CMP) process is performed to form a portion of the conductive layer 118 formed on the uppermost surface of the dielectric layer 106 with the conformal barrier /
The adhesive layer 116 is polished. This process flattens the top surface of all the wafers and provides a conformal barrier / adhesion layer 116.
And the remaining portion of the conductive layer 118 are left only in the double damascene hole 107 (FIG. 2) in the dielectric layer 106 that has already been formed. The structure combining the rest of the conformal barrier / adhesion layer 116 and the rest of the conductive layer 118 is
Construct the desired double damascene structure. As shown, the dual damascene structure extends through the dielectric
It is formed to be electrically connected to the level metallization layer 102. The wide upper portion of the conduction layer 118 is the first level metallization layer 1
02 functions as a second level metallization layer. The narrow bottom of the conductive layer 118 functions as a metal plug interconnecting the second level metallization and the first level metallization 102. Thereafter, the conductive layer 118 is spread over the entire upper surface of the wafer.
A second overlying layer 120 is formed to cover the first layer. Second overlying layer 120 prevents the atoms in conductive layer 118 from being diffused upward into a dielectric layer (not shown) that will be formed over the wafer.

[0010]

The above-mentioned conventional method has one disadvantage. If an RIE process is used to remove a portion of the first overlying layer 104 and expose the first level metallization layer 102, the exposed surface of the first level metallization layer 102 may be exposed to the high energy energy used in the RIE process. That is, it is exposed to the impact of ions. This causes the metal atoms in the first level metallization layer 102 to be knocked out and deposited on the side walls of the narrow bottom 112 of the double damascene hole 107.
In a subsequent heat treatment, the deposited metal is
06 affect the overall electrical properties of the manufactured wafer. The IC device manufactured in this manner is likely to be defective and needs to be discarded. This drawback reduces the production rate of wafer fabrication.

[0011] Accordingly, the present invention provides an integrated circuit that can overcome the disadvantages of the prior art described above by forming a conformal barrier / adhesion layer before using an RIE process to expose the metallization layer. It is an object to provide a method for manufacturing a double damascene structure. According to the above and other objects of the present invention, a new method of manufacturing a double damascene structure in an integrated circuit is provided.

[0012]

The feature of this method is that after forming the double damascene hole, the double damascene hole is not filled first so as to cover the entire sidewall of the double damascene hole.
This means that an adhesive layer is formed. Next, the bottom of the conformal barrier / adhesive layer lying on the bottom of the double damascene hole is removed,
Subsequently, the underlying portion of the overlying layer is removed by anisotropic etching until the metallization layer is exposed. Finally, a conductive material such as copper is deposited in the remaining cavity of the double damascene hole. The combination of the deposited conductive material and the rest of the conformal barrier / adhesion layer in the double damascene hole constitutes the desired dual damascene structure. The conformal barrier / adhesion layer acts as a diffusion barrier to protect the dielectric layer, and the metal atoms deposited on the sidewalls of the double damascene hole from the metallization layer during the RIE (Reactive Ion Etching) process become Prevents diffusion into layers.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS With reference to FIGS. 6 to 12, an embodiment of a method for manufacturing a double damascene structure in an integrated circuit according to the present invention will be described in detail. In this specification only, the term wafer will be used hereinafter for both unprocessed wafers, partially manufactured wafers at any stage of manufacture, and manufactured wafers.

In a first step shown in FIG. 6, a semiconductor substrate 200 is prepared. Next, a first level metallization layer 202 is formed in place in the semiconductor substrate 200, preferably with copper. Next, a first overlaid layer 204 is formed on the semiconductor substrate 200. This first additional layer 2
04 covers the first level metallization layer 202.
At this time, it is desirable to form the first additional layer 204 from silicon nitride (SiN _x ) by a chemical vapor deposition (CVD) process. Thereafter, a first dielectric layer 206 is formed on the first additional layer 204. At this time, it is desirable to form the first dielectric layer 206 from silicon nitride by a CVD process. Next, the top surface of the first dielectric layer 206 is removed until the remaining portion of the first dielectric layer 206 has a predetermined thickness equal to the specified depth of the target metal plug portion of the double damascene structure. A chemical mechanical polishing (CMP) process for planarizing is performed. Next, an etch end layer 2 is formed on the first dielectric layer 206.
08 is formed. At this time, it is desirable to form the etch end layer 208 from silicon nitride by a CVD process.

Next, in the second step shown in FIG.
A selective removal process, such as a photolithography and etching process, is performed to remove a selected portion of the etch end layer 208 at a location just above the first level metallization layer 202. This allows opening 20 in etch end layer 208.
9 is formed. Thereafter, a second layer is formed on the etch end layer 208.
A dielectric layer 210 is formed. At this time, it is desirable to form the second dielectric layer 210 from silicon nitride by a CVD process. Next, the remaining portion of the second dielectric layer 210 has a predetermined thickness equal to the specified depth of the desired metallization layer portion of the dual damascene structure (ie, the depth of the second level metal layer). Until the CMP process is performed to planarize the uppermost surface of the second dielectric layer 210.

Next, in a third step shown in FIG.
A selective removal process, such as photolithography and etching, is performed to remove selected portions of the second dielectric layer 210 until the etch end layer 208 is exposed. This forms a cavity 214 (which will be a metallization layer groove) in the second dielectric layer 210. The cavity 214 is wider than the opening 209 (FIG. 2) formed in the etch end layer 208.

Subsequently, an etching process is performed using the etch end layer 208 as a mask, and the first overlying layer 20 is formed.
The portion of the first dielectric layer 206 not covered by the mask is removed until the number reaches 4. As a result, a cavity 212 (to be a via hole) is formed in the first dielectric layer 206. The width of the via hole 212 in the first dielectric layer 206 is smaller than the width of the metallization layer groove 214 formed in the second dielectric layer 210. A via hole 212 in the first dielectric layer 206 and a second
The metallization groove 214 formed in the dielectric layer 210 forms a double damascene hole.

In the fourth step shown in FIG. 9, the metallized layer groove 214 and the via hole 212 of the double damascene hole 207 are formed.
The conformal barrier / adhesion layer 216 has a predetermined thickness over the entire exposed surface of the wafer, including the exposed portion of the first overlayer 204 and the entire sidewall of the double damascene hole 207. Formed. Conformal barrier / adhesive layer 2
Numeral 16 is formed of a barrier / adhesive material selected from the group consisting of tantalum, tantalum nitride, and titanium nitride. The first layer formed on the metallization layer 202
It is part of the features of the present invention that the conformal barrier / adhesion layer 216 is formed before removing the exposed portions of the overlayer 204. The conformal barrier / adhesion layer 216 includes a barrier structure that prevents metal atoms from diffusing into the first dielectric layer 206 and the second dielectric layer 210, and a double damascene hole 20.
7 and serves as an adhesive structure that enhances the bond between the metal subsequently deposited in the first dielectric layer 206 and the second dielectric layer 210.

In the fifth step shown in FIG.
An anisotropic etching process such as an E (reactive ion etching) process is performed and the bottom 213 of the conformal barrier / adhesive layer 216 at the bottom of the via hole 212 of the double damascene hole 207.
Is removed, followed by the portion under the first overlying layer 204 until the metallization layer 202 is exposed. This process further extends the via hole 212 of the double damascene hole 207 downward, exposing the first level metallization layer 202.

During the anisotropic etching process, it seems that portions other than the bottom 213 of the conformal barrier / adhesive layer 216 are also etched, but because of the step coverage,
The bottom 213 of the conformal barrier / adhesive layer 216 is thinner than the portion other than the bottom 213 of the conformal barrier / adhesive layer 216. Therefore,
After the bottom 213 is completely removed, the double damascene hole 20 is removed.
7 remain covered by the rest of the conformal barrier / adhesive layer 216. If the sidewalls of the conformal barrier / adhesion layer 216 have been etched away to expose the first dielectric layer 206 or the etch end layer 208, a further selective deposition process is performed and the metallization layer grooves 214 Via Hole 21
A conformal barrier / adhesive material (ie, tantalum, tantalum nitride, or titanium) is deposited in an area other than the area occupied by 2. As a result, the side wall of the conformal barrier / adhesion layer 216 can be formed even thicker. The protection of the conformal barrier / adhesion layer 216 allows the dual damascene holes 207 to be removed from the metallization layer 202 during the RIE process exposure as in the prior art.
Metal atoms deposited on the side walls of the first and second dielectric layers 2
It hardly diffuses into the channels 06 and 210. By using the method of the invention in this way, the disadvantages of the prior art are overcome.

In the sixth step shown in FIG. 11, the remaining cavity of the double damascene hole 207 is completely filled,
A metal such as copper is deposited to cover the top surface of the conformal barrier / adhesion layer 216. Through this process, the conductive layer 218 is formed from the deposited metal.

In the seventh step shown in FIG.
A surface removal process such as a P process is performed to remove all portions of the conformal barrier / adhesion layer 216 and the conductive layer 218 that are on the top surface of the second dielectric layer 210. This process allows the remaining portion of conformal barrier / adhesive layer 216 and conductive layer 21
8 is a double damascene hole 20 already formed.
7 (FIG. 10). The combined structure of the remaining portion of the conformal barrier / adhesion layer 216 and the remaining portion of the conductive layer 218 functions as a target dual damascene structure. As shown, the dual damascene structure is formed to be electrically connected to the first level metallization layer 202. The wide top of conductive layer 218 functions as a second level metallization layer above first level metallization layer 202 and the narrow bottom of conductive layer 218 has a second level metallization layer and first level metallization layer 20.
2 serves as a metal plug interconnecting the two. After this,
A second overlying layer 220 is formed from silicon nitride, preferably by a CVD process, over the entire upper surface of the wafer and covers conductive layer 218. The second overlay layer 220 is a conductive layer 218
Of dielectric layers in which atoms are later formed on the wafer
(Not shown) to prevent diffusion upward. This completes the fabrication of the double damascene structure.

The present invention is not limited to the dual damascene structure described above, but can be applied to any semiconductor manufacturing process including a damascene structure electrically connected to the metallization layer.

[0024]

In conclusion, the method of the present invention has the following advantages over the prior art.

(1) First, the present invention provides a method for providing diffusion protection for the first and second dielectric layers 206 and 210 on the bottom and side walls of the double damascene hole after the double damascene hole is formed. The first and second groups of metal atoms that function as a layer and are deposited on the sidewalls of the double damascene hole 207 from the metallization layer 202 during the RIE process.
The feature is that a conformal barrier / adhesion layer is formed to prevent diffusion into the dielectric layers 206 and 210. The IC device manufactured in this way has better operation reliability. Therefore, the production rate of wafer manufacturing is improved.

(2) Second, according to the method of the present invention, the completed double damascene structure is in direct contact with the metallization layer 202. On the other hand, in the prior art, the completed double damascene structure is formed through the bottom of the conformal barrier / adhesion layer 116 through the metallization layer 1.
02 (see FIG. 5). Thus, according to the method of the present invention, the resistance of the electrical connection between the double damascene structure and the metallization layer 202 is lower than in the prior art. As described above, the present invention has been described using the embodiments, but the scope of the present invention is not limited to the above embodiments. On the contrary, the scope of the present invention includes various modifications and changes to the above-described embodiment, and forms of the same arrangement. Therefore,
The appended claims are to be given the broadest interpretation including such modified or changed forms or similar arrangements.

[Brief description of the drawings]

FIG. 1 is a schematic cross-sectional view showing steps performed in a conventional method of manufacturing a double damascene structure.

FIG. 2 is a schematic cross-sectional view showing steps performed in a conventional method of manufacturing a double damascene structure.

FIG. 3 is a schematic cross-sectional view showing steps performed in a conventional method of manufacturing a double damascene structure.

FIG. 4 is a schematic cross-sectional view showing steps performed in a conventional method of manufacturing a double damascene structure.

FIG. 5 is a schematic cross-sectional view showing steps performed in a conventional method of manufacturing a double damascene structure.

FIG. 6 is a schematic cross-sectional view showing steps performed in a method for manufacturing a double damascene structure according to the present invention.

FIG. 7 is a schematic cross-sectional view illustrating steps performed in a method of manufacturing a double damascene structure according to the present invention.

FIG. 8 is a schematic cross-sectional view illustrating steps performed in a method of manufacturing a dual damascene structure according to the present invention.

FIG. 9 is a schematic cross-sectional view showing steps performed in a method of manufacturing a double damascene structure according to the present invention.

FIG. 10 is a schematic cross-sectional view illustrating steps performed in a method of manufacturing a dual damascene structure according to the present invention.

FIG. 11 is a schematic cross-sectional view illustrating steps performed in a method for manufacturing a double damascene structure according to the present invention.

FIG. 12 is a schematic cross-sectional view showing steps performed in a method of manufacturing a double damascene structure according to the present invention.

[Explanation of symbols]

 100: Semiconductor substrate 102: First level metallization layer 104: First overlying layer 106: Dielectric layer 107: Double damascene hole 112: Narrow bottom 114: Wide bottom 116: Conformal barrier / adhesion layer 118: Conductive layer 120 : Second overlying layer 200: Semiconductor substrate 202: First level metallization layer 204: First overlying layer 206: First dielectric layer 207: Double damascene hole 208: Etch end layer 209: Opening 210: Second dielectric Layer 212: Via Hole 213: Bottom 218: Conductive Layer 220: Second Overlay Layer

 ──────────────────────────────────────────────────続 き Continued on the front page F-term (reference) 4M104 BB04 BB17 BB30 BB32 DD07 DD17 DD66 FF16 FF22 HH09 HH12 5F033 HH11 HH21 HH32 HH33 JJ11 JJ21 JJ32 JJ33 KK11 MM02 MM05 MM12 MM13 Q19 Q19 Q16 QQ48 RR06 SS11 TT02 XX01 XX14

Claims (19)

[Claims] 1. A method of manufacturing a damascene structure in an integrated circuit structure already formed by a metallization layer at a predetermined location on a semiconductor substrate and an overlying layer formed on the semiconductor substrate and covering the metallization layer. Forming a dielectric layer on the overlying layer; forming a damascene hole in the dielectric layer that exposes the overlying layer; all sidewalls of the damascene hole without filling the damascene hole. Forming a conformal barrier / adhesive layer to a predetermined thickness over the exposed portion of the overlying layer and over the surface of the dielectric layer; and the damascene just above the overlying layer. Removing the bottom of the conformal barrier / adhesive layer overlying the bottom of the hole and subsequently performing an etching process to remove the underlying portion of the overlying layer until the metallization layer is exposed; Said Depositing the remaining hollow portion of the mask holes,
Forming a desired damascene structure with the deposited conductive material and the remaining portion of the conformal barrier / adhesive layer. 2. The method of claim 1, wherein the conformal barrier / adhesion layer is formed of a material selected from the group consisting of tantalum, tantalum nitride, and titanium nitride.
3. A method for manufacturing a damascene structure according to claim 1. 3. The method according to claim 1, wherein the conductive material is copper. 4. The method according to claim 1, wherein the etching process is an anisotropic etching process. 5. The method according to claim 4, wherein the anisotropic etching is RIE. 6. The method of claim 1, further comprising forming an overlying layer on the dielectric layer. 7. A method of fabricating a dual damascene structure in an integrated circuit structure already formed by a metallization layer in place on a semiconductor substrate and an overlying layer formed on the semiconductor substrate and covering the metallization layer. Forming a dielectric layer on the overlying layer; forming a double damascene hole in the dielectric layer that exposes the overlying layer; without filling the double damascene hole; Forming a conformal barrier / adhesive layer to a predetermined thickness over all sidewalls of the double damascene hole, over exposed portions of the overlying layer, and over the surface of the dielectric layer; Etching to remove the bottom of the conformal barrier / adhesive layer overlying the bottom of the double damascene hole directly above the overlying layer and subsequently removing the underlying portion of the overlying layer until the metallization layer is exposed Step to execute processing Depositing a conductive material in the remaining cavity of the dual damascene hole, and forming the desired dual damascene structure with the deposited conductive material and the remaining portion of the conformal barrier / adhesive layer. Double damascene structure manufacturing method. 8. The conformal barrier / adhesive layer of claim 7, wherein the conformal barrier / adhesive layer is formed from a conformal barrier / adhesive material selected from the group consisting of tantalum, tantalum nitride, and titanium nitride. Manufacturing method of double damascene structure. 9. The method according to claim 7, wherein the conductive material is copper. 10. The method according to claim 7, wherein the etching process is an anisotropic etching process. 11. The method according to claim 10, wherein the anisotropic etching is RIE. 12. The method of claim 7, further comprising forming an overlying layer on the dielectric layer. 13. A method of fabricating a double damascene structure in an integrated circuit structure already formed by a metallization layer in place on a semiconductor substrate and an overlying layer formed on the semiconductor substrate and covering the metallization layer. Forming a first dielectric layer on the overlying layer; forming an etch end layer on the first dielectric layer; and in the etch end layer just above the metallization layer. Forming an opening at a predetermined location; forming a second dielectric layer over the etch end layer; etching a selected portion of the second dielectric layer until the etch end layer is reached. Forming a metallization groove in the first dielectric layer directly above the metallization layer, and removing portions of the first dielectric layer that are not masked by the etched layer. The first additional layer Etching away until exposed, thereby forming a via hole in the first dielectric layer, the via hole in the first dielectric layer and the metallization groove in the second dielectric layer. Forming a double damascene hole by a combination of: forming a conformal barrier over all sidewalls of the double damascene hole and over a surface of the second dielectric layer without filling the double damascene hole. Forming the adhesive layer to a predetermined thickness; removing the bottom of the conformal barrier / adhesive layer overlying the bottom of the double damascene hole directly above the first overlying layer; Performing an etching process that removes the underlying portion of the first overlying layer until the layer is exposed; and conducting conductive material over the remaining cavity of the dual damascene hole and over the conformal barrier / adhesive layer. Deposit to the specified thickness Performing a surface removal process to remove a portion of the conductive layer and the conformal barrier / adhesive layer formed on the second dielectric layer, and to form a conformal portion with the remaining portion of the conductive layer. Constructing the desired dual damascene structure by combining the remaining portion of the barrier / adhesive layer; and forming a second overlying layer over the second dielectric layer to cover the double damascene structure. The manufacturing method of the double damascene structure provided with. 14. The method of claim 13, wherein the conductive layer is formed of copper. 15. The method according to claim 13, wherein the conductive material is formed by a CVD process. 16. The method according to claim 13, wherein the first additional layer is formed of silicon nitride. 17. The method of claim 17, wherein the conformal barrier / adhesion layer is tantalum.
14. The method of claim 13, wherein the damascene structure is formed of a conformal barrier / adhesive material selected from the group consisting of tantalum nitride and titanium nitride. 18. The etching process according to claim 13, wherein the etching process for removing a bottom portion of the conformal barrier / adhesive layer and a lower portion of the first overlying layer is an anisotropic etching process.
3. The method for manufacturing a double damascene structure according to item 1. 19. The method according to claim 18, wherein the anisotropic etching is RIE.