CN103515234B - The method forming FinFET - Google Patents
The method forming FinFET Download PDFInfo
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- CN103515234B CN103515234B CN201210211019.1A CN201210211019A CN103515234B CN 103515234 B CN103515234 B CN 103515234B CN 201210211019 A CN201210211019 A CN 201210211019A CN 103515234 B CN103515234 B CN 103515234B
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- layer
- hard mask
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- quasiconductor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Thin Film Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The invention discloses a kind of method forming FinFET, the method forms the depression of exposure semiconductor base by etching certain thickness hard mask, and form quasiconductor fin in the valley by extension, it is with without forming quasiconductor fin by etching semiconductor substrate, when therefore avoiding etching semiconductor substrate formation quasiconductor fin in prior art, its surface topography roughness is higher, silicon crystallization is produced the problem destroyed, and simplify manufacturing process flow, blend with existing CMOS technology, save production cost.
Description
Technical field
The application relates to field of semiconductor manufacture, particularly relates to a kind of formation FinFET(FinField-
Effecttransistor, fin field-effect transistor) method.
Background technology
Along with the development of semiconductor technology, as the metal oxide semiconductor transistor of one of its development mark
(MOSFET) characteristic size is followed Moore's Law always and is constantly reduced.In order to adapt to integrated circuit miniaturization and high performance want
Asking, in the last few years, three-dimensional integration technology earns widespread respect, and as a example by MOS, i.e. develops horizontal multiaspect grid structure, longitudinally the most
The three dimensional structures such as face grid structure.
The multiple-gate MOSFET of three dimensional structure can be divided into intuitively according to the position relationship that grid are parallel or vertical with substrate
Horizontal multiple-gate MOSFET (Planar DG) and longitudinal multiple-gate MOSFET.It addition, according to the relation of current direction Yu substrate
Longitudinal multiple-gate MOSFET is divided into again FinFET(FinField-effecttransistor, fin field-effect transistor) structure (electricity
Flow path direction is parallel to substrate) and Sidewall structure (sense of current is perpendicular to substrate).
Fig. 1 a ~ Fig. 1 d shows typical FinFET structure manufacturing process, as shown in Figure 1a, it is provided that semiconductor base 10,
Predefined on described semiconductor base 10 have multiple quasiconductor fin-shaped object location, sequentially forms liner oxygen on semiconductor base 10
Change layer 11 and hard mask layer (not shown), patterned hard mask layer, make hard mask layer 12 correspondence of patterning be covered in described pre-
Multiple quasiconductor fin-shaped object locations of definition；As shown in Figure 1 b, with the hard mask layer 12 of described patterning for shielding, etching is described
Semiconductor base 10, to form quasiconductor fin 13, and forms depression 14 between each quasiconductor fin 13；Such as Fig. 1 c
Shown in, remove hard mask layer and pad oxide layer, with dielectric material 15, such as high-density plasma (HDP) oxide, tetrem
TMOS (TEOS) oxides etc., fill depression 14；As shown in Figure 1 d, return carve described in be filled in the dielectric material of described depression 14
Material, to expose the quasiconductor fin 13 of predetermined altitude, and forms gate medium in the oxidation of described quasiconductor fin 13 surface heat
Layer 16, last deposit polycrystalline silicon layer 17, it is perpendicular to described quasiconductor fin 13 side of extension to be formed on semiconductor base 10
To grid 17.
In the actual manufacture process of FinFET structure, the material of semiconductor base 10 is generally monocrystal silicon, performs etching
Easily the crystalline texture of monocrystal silicon is produced when forming quasiconductor fin and destroy, and then produce defect so that carrier mobility
Rate step-down, and due to etching be difficult to accurately control, quasiconductor fin formed time surface (surface after Ke Shi) coarse
Spend higher, and then cause the gate dielectric layer formed on its surface exists charge-trapping trap, and then affect device performance.Again
Person, in the manufacture method of existing FinFET structure, technological process is the most loaded down with trivial details, therefore, how to simplify its technological process, with
It is also problem demanding prompt solution that existing CMOS technology merges.
Summary of the invention
In view of the defect of prior art, the present invention provides a kind of method forming FinFET, is simplifying existing technique stream
While journey, it is to avoid its surface topography roughness is higher when forming quasiconductor fin, silicon crystallization is produced destruction and asks
Topic.
The technological means that the present invention uses is as follows: a kind of method forming FinFET, including:
Semiconductor base is provided, described semiconductor base is predefined with in active area, and described predefined active area pre-
Definition has the position of quasiconductor fin；
Described semiconductor base is sequentially formed with cushion oxide layer and hard mask layer；
Forming the optical resistance glue layer of patterning on described hard mask layer, the optical resistance glue layer window of patterning is corresponding to described pre-
The quasiconductor fin-shaped object location of definition；
With the optical resistance glue layer of described patterning for shielding, it is sequentially etched hard mask layer and cushion oxide layer, recessed to be formed
Falling into, described concave bottom exposes described semiconductor substrate surface；
By extension, at the semiconductor substrate surface that described concave bottom exposes, form semiconductor layer, described quasiconductor
Layer fills described depression；
It is sequentially etched removal described hard mask layer and cushion oxide layer, with the described semiconductor layer that exposes for quasiconductor fin-shaped
Thing；
Gate dielectric layer is formed in the oxidation of described quasiconductor fin surface heat；
Deposit polycrystalline silicon layer on a semiconductor substrate, forms the grid being perpendicular to quasiconductor fin bearing of trend.
Further, after described semiconductor base is sequentially formed with cushion oxide layer and hard mask layer, formed described
Before window is corresponding to the patterning photoresistance glue of described predefined quasiconductor fin-shaped object location, also include that etching forms shallow trench
The step of isolation, this step includes:
It is sequentially etched described cushion oxide layer and hard mask layer, with the semiconductor base in described predetermined active area both sides
Middle formation shallow trench；
Deposition of dielectric materials on described semiconductor base, and carry out cmp, so that described dielectric material table
Face flushes with described hard mask surface；
When etching described cushion oxide layer, also include that etching removal is positioned at the upper part of described semiconductor substrate surface
The step of described dielectric material.
Further, the degree of depth of described depression is 5nm to 60nm.
Further, the width of the optical resistance glue layer window of described patterning is 5nm to 30nm.
Further, use dry etching remove described hard mask, the parameter of described dry etching includes, with difluoromethane,
Sulfur hexafluoride, nitrogen and helium are etching gas, and power is 550 to 650 watts, and bias is 55 to 65 watts, pressure be 2 to
10mTorr。
Further, the material of described semiconductor base is monocrystal silicon, and the material of described semiconductor layer is monocrystal silicon or doping
Monocrystal silicon, described in be epitaxially formed the temperature of semiconductor layer and be 600 to 800 degrees Celsius.
The method that the formation FinFET of present invention offer is provided, it is not necessary to form quasiconductor fin-shaped by etching semiconductor substrate
Thing, when therefore avoiding etching semiconductor substrate formation quasiconductor fin in prior art, its surface topography roughness is higher,
Silicon crystallization is produced the problem destroyed, and simplifies manufacturing process flow, blend with existing CMOS technology, save life
Produce cost.
Accompanying drawing explanation
Fig. 1 a ~ Fig. 1 d is the Structure and Process schematic diagram that prior art forms FinFET method；
Fig. 2 is a kind of method flow diagram forming FinFET disclosed by the invention；
Fig. 3 a ~ Fig. 3 g is a kind of Structure and Process schematic diagram forming FinFET method of the present invention.
Detailed description of the invention
Being described principle and the feature of the present invention below in conjunction with accompanying drawing, example is served only for explaining the present invention, and
Non-for limiting the scope of the present invention.
As in figure 2 it is shown, the invention provides a kind of method forming FinFET, step includes:
Semiconductor base is provided, described semiconductor base is predefined with in active area, and described predefined active area pre-
Definition has the position of quasiconductor fin；
Described semiconductor base is sequentially formed with cushion oxide layer and hard mask layer；
Forming the optical resistance glue layer of patterning on described hard mask layer, the optical resistance glue layer window of patterning is corresponding to described pre-
The quasiconductor fin-shaped object location of definition；
With the optical resistance glue layer of described patterning for shielding, it is sequentially etched hard mask layer and cushion oxide layer, recessed to be formed
Falling into, described concave bottom exposes described semiconductor substrate surface；
By extension, at the semiconductor substrate surface that described concave bottom exposes, form semiconductor layer, described quasiconductor
Layer fills described depression；
It is sequentially etched removal described hard mask layer and cushion oxide layer, with the described semiconductor layer that exposes for quasiconductor fin-shaped
Thing；
Gate dielectric layer is formed in the oxidation of described quasiconductor fin surface heat；
Deposit polycrystalline silicon layer on a semiconductor substrate, forms the grid being perpendicular to quasiconductor fin bearing of trend.
As a kind of exemplary embodiments of the present invention, below in conjunction with accompanying drawing 3a ~ 3g, the technological means of the present invention is carried out in detail
Thin elaboration.
As shown in Figure 3 a, it is provided that semiconductor base 20, its material is preferably monocrystal silicon, and semiconductor base 20 has been predefined with
Source region (does not indicates), and the predefined position (not shown) having quasiconductor fin in predefined active area；Semiconductor-based
Being sequentially formed with cushion oxide layer 21 and hard mask layer 22, wherein the material of hard mask layer 22 is preferably silicon nitride at the end 20, and
Preferably employ dry etching etch hard mask 22, the parameter of dry etching includes, with difluoromethane, sulfur hexafluoride, nitrogen and
Helium is etching gas, and power is 550 to 650 watts, and bias is 55 to 65 watts, and pressure is 2 to 10mTorr；
With reference to Fig. 3 b, it is sequentially etched cushion oxide layer 21 and hard mask layer 22, with partly leading in predetermined active area both sides
Forming shallow trench 23 in body substrate 20, this process can be by first forming patterning light photoresistance glue then with light on hard mask layer 22
Resistance glue forms shallow trench 23 for shielding etching, and those skilled in the art realize also by other usual technological means, be with
Do not repeat them here；
As shown in Figure 3 c, deposition of dielectric materials 24 on semiconductor base 20, and carry out cmp, so that dielectric
Material 24 surface flushes with hard mask 22 surface, its dielectric material 24 can be high-density plasma (HDP) oxide, four
Ethoxysilane (TEOS) oxide etc.；
Forming the optical resistance glue layer of patterning on hard mask layer 22, the optical resistance glue layer window of patterning is corresponding to predefined
Quasiconductor fin-shaped object location, in the present embodiment, the width of the optical resistance glue layer window of preferred pattern is 5nm to 30nm；To scheme
The optical resistance glue layer of case is shielding, is sequentially etched hard mask layer 22 and cushion oxide layer 21, to form depression 25, removes pattern
The optical resistance glue layer changed, not shown with reference to Fig. 3 d(wherein optical resistance glue layer), wherein, cave in 25 bottom-exposed semiconductor base 20 tables
Face, in the present embodiment, the degree of depth of depression is preferably 5nm to 60nm；
As shown in Figure 3 e, by extension, semiconductor layer is formed in semiconductor base 20 surface of depression 25 bottom-exposed
26, semiconductor layer 26 fills depression 25, and wherein semiconductor layer 26 can be monocrystal silicon, it is also possible to for doping after monocrystal silicon, its
In, the temperature being epitaxially formed semiconductor layer is 600 to 800 degrees Celsius；
With reference to Fig. 3 f, it is sequentially etched removal hard mask layer 22 and cushion oxide layer 21, and etches removal and be positioned at semiconductor-based
The dielectric material 24 of the upper part on surface, the end 20, using expose semiconductor layer 26 as quasiconductor fin 26；
As shown in figure 3g, gate dielectric layer 27 is formed, on semiconductor base 28 in the oxidation of quasiconductor fin 26 surface heat
Deposit polycrystalline silicon layer 28, and form the grid 28 being perpendicular to quasiconductor fin bearing of trend, gate dielectric layer 27 and grid 28
Being formed, those skilled in the art can be realized by existing technique and conventional techniques means, does not repeats them here.
In sum, owing to the present invention is by etching the depression of certain thickness hard mask formation exposure semiconductor base,
And form quasiconductor fin in the valley by extension, it is with without forming quasiconductor fin-shaped by etching semiconductor substrate
Thing, when therefore avoiding etching semiconductor substrate formation quasiconductor fin in prior art, its surface topography roughness is higher,
Silicon crystallization is produced the problem destroyed, and simplifies manufacturing process flow, blend with existing CMOS technology, save life
Produce cost.
The foregoing is only presently preferred embodiments of the present invention, not in order to limit the present invention, all essences in the present invention
Within god and principle, any modification, equivalent substitution and improvement etc. done, within should be included in the scope of protection of the invention.
Claims (5)
1. form a FinFET method, including:
Semiconductor base is provided, described semiconductor base is predefined with in active area, and described predefined active area predefined
There is the position of quasiconductor fin；
Described semiconductor base is sequentially formed with cushion oxide layer and hard mask layer；
It is sequentially etched described cushion oxide layer and hard mask layer, with shape in the semiconductor base of described predetermined active area both sides
Become shallow trench；
Deposition of dielectric materials on described semiconductor base, and carry out cmp so that described dielectric material surface with
Described hard mask surface flushes；
Forming the optical resistance glue layer of patterning on described hard mask layer, the optical resistance glue layer window of patterning is corresponding to described predefined
Quasiconductor fin-shaped object location；
With the optical resistance glue layer of described patterning for shielding, it is sequentially etched hard mask layer and cushion oxide layer, to form depression, institute
State concave bottom and expose described semiconductor substrate surface；
By extension, forming semiconductor layer at the semiconductor substrate surface that described concave bottom exposes, described semiconductor layer is filled out
Fill described depression；
It is sequentially etched removal described hard mask layer and cushion oxide layer, and etches removal and be positioned at the upper part of semiconductor substrate surface
Dielectric material, with expose described semiconductor layer for quasiconductor fin；
Gate dielectric layer is formed in the oxidation of described quasiconductor fin surface heat；
Deposit polycrystalline silicon layer on a semiconductor substrate, forms the grid being perpendicular to quasiconductor fin bearing of trend.
Method the most according to claim 1, it is characterised in that the degree of depth of described depression is 5nm to 60nm.
Method the most according to claim 1, it is characterised in that the width of the optical resistance glue layer window of described patterning is 5nm
To 30nm.
Method the most according to claim 1, it is characterised in that use dry etching to remove described hard mask, described dry method
The parameter of etching includes, with difluoromethane, sulfur hexafluoride, nitrogen and helium as etching gas, power is 550 to 650
Watt, bias is 55 to 65 watts, and pressure is 2 to 10mTorr.
Method the most according to claim 1, it is characterised in that the material of described semiconductor base is monocrystal silicon, described half
The material of conductor layer is the monocrystal silicon of monocrystal silicon or doping, described in be epitaxially formed the temperature of semiconductor layer be 600 to 800 Celsius
Degree.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210211019.1A CN103515234B (en) | 2012-06-25 | 2012-06-25 | The method forming FinFET |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210211019.1A CN103515234B (en) | 2012-06-25 | 2012-06-25 | The method forming FinFET |
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| Publication Number | Publication Date |
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| CN103515234A CN103515234A (en) | 2014-01-15 |
| CN103515234B true CN103515234B (en) | 2016-12-21 |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6835618B1 (en) * | 2003-08-05 | 2004-12-28 | Advanced Micro Devices, Inc. | Epitaxially grown fin for FinFET |
| CN1930671A (en) * | 2004-01-16 | 2007-03-14 | 英特尔公司 | Tri-gate transistors and methods to fabricate same |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100286736B1 (en) * | 1998-06-16 | 2001-04-16 | 윤종용 | How to form trench isolation |
| JP2005064500A (en) * | 2003-08-14 | 2005-03-10 | Samsung Electronics Co Ltd | Multi-structured silicon fin and manufacturing method for the same |
| CN100372069C (en) * | 2004-05-19 | 2008-02-27 | 上海宏力半导体制造有限公司 | Method for forming T type polycrystalline silicon gate through double inlaying process |
| US7517764B2 (en) * | 2006-06-29 | 2009-04-14 | International Business Machines Corporation | Bulk FinFET device |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6835618B1 (en) * | 2003-08-05 | 2004-12-28 | Advanced Micro Devices, Inc. | Epitaxially grown fin for FinFET |
| CN1930671A (en) * | 2004-01-16 | 2007-03-14 | 英特尔公司 | Tri-gate transistors and methods to fabricate same |
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