CN103515234B - A method of forming a FinFET - Google Patents

A method of forming a FinFET Download PDF

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CN103515234B
CN103515234B CN201210211019.1A CN201210211019A CN103515234B CN 103515234 B CN103515234 B CN 103515234B CN 201210211019 A CN201210211019 A CN 201210211019A CN 103515234 B CN103515234 B CN 103515234B
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layer
semiconductor
semiconductor substrate
hard mask
forming
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CN103515234A (en
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赵猛
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中芯国际集成电路制造(上海)有限公司
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Abstract

本发明公开了一种形成FinFET的方法,该方法通过刻蚀一定厚度的硬掩膜形成暴露半导体基底的凹陷,并通过外延在凹陷中形成半导体鳍状物,是以无需通过刻蚀半导体基底形成半导体鳍状物,因此避免了现有技术中刻蚀半导体基底形成半导体鳍状物时其表面形貌粗糙度较高,对硅结晶产生破坏的问题,并且简化了制造工艺流程,与现有的CMOS工艺相融合,节省了生产成本。 The present invention discloses a method of forming a FinFET, the method of exposing a semiconductor substrate a recess is formed by etching a thickness of the hard mask, and forming a semiconductor fin in the depression by epitaxial, is formed by etching a semiconductor substrate without the semiconductor fins, thus avoiding high roughness surface topography which when the prior art etching the semiconductor substrate of the semiconductor fin is formed, problems of damage to the silicon crystal, and simplifies the manufacturing process, the conventional CMOS process integration, saving the cost of production.

Description

形成FinFET的方法 A method of forming a FinFET

技术领域 FIELD

[0001 ] 本申请涉及半导体制造领域,尤其涉及一种形成FinFET(FinField-ef fecttrans istor,鳍式场效晶体管)的方法。 [0001] The present application relates to semiconductor manufacturing, and more particularly relates to a method of FinFET (FinField-ef fecttrans istor, fin field-effect transistor) is formed.

背景技术 Background technique

[0002]随着半导体技术的发展,作为其发展标志之一的金属氧化物半导体晶体管(MOSFET)的特征尺寸一直遵循摩尔定律不断缩小。 [0002] With the development of semiconductor technology, wherein the size of the metal oxide semiconductor transistor (MOSFET) as one of its development has followed Moore's Law flag shrinking. 为了适应集成电路小型化和高性能的要求,近些年来,三维集成技术得到广泛重视,以MOS为例,即发展出水平多面栅结构、纵向多面栅结构等三维结构。 In order to accommodate IC miniaturization and high performance requirements, in recent years, three-dimensional integration technology extensive attention to MOS example, that the development of a horizontal multi-gate structure surface, longitudinal multi-gate structure or the like three-dimensional structure surface.

[0003]三维结构的多面栅MOSFET可根据栅与衬底平行或是垂直的位置关系直观的分为水平多面栅M0SFET(Planar DG)以及纵向多面栅M0SFET。 [0003] The three-dimensional polygon-gate MOSFET structure can be visually divided into horizontal multi-gate surface M0SFET (Planar DG) and the longitudinal gate M0SFET polygon from the positional relationship of the gate perpendicular or parallel to the substrate. 另外,根据电流流向与衬底的关系纵向多面栅MOSFET又分为FinFET(FinField-effecttransistor,鳍式场效晶体管)结构(电流方向平行于衬底)和Sidewa11结构(电流方向垂直于衬底)。 Further, according to the relationship between the current flowing to the surface of the substrate longitudinal multi-gate MOSFET is divided into FinFET (FinField-effecttransistor, a fin field effect transistor) structure (current direction parallel to the substrate) and Sidewa11 structure (current direction perpendicular to the substrate).

[0004]图1a〜图1d示出了典型的FinFET结构制造流程,如图1a所示,提供半导体基底10,所述半导体基底10上预定义有多个半导体鳍状物位置,在半导体基底10上依次形成衬垫氧化层11和硬掩膜层(未示出),图案化硬掩膜层,使图案化的硬掩膜层12对应覆盖于所述预定义的多个半导体鳍状物位置;如图1b所示,以所述图案化的硬掩膜层12为屏蔽,刻蚀所述半导体基底10,以形成半导体鳍状物13,并在各个半导体鳍状物13之间形成凹陷14;如图1c所示,去除硬掩膜层及衬垫氧化物层,以介电材料15,如高密度等离子体(HDP)氧化物、四乙氧基硅烷(TEOS)氧化物等,填充凹陷14;如图1d所示,回刻所述填充于所述凹陷14的介电材料,以暴露预定高度的半导体鳍状物13,并在所述半导体鳍状物13表面热氧化形成栅介质层16,最后沉积多晶硅层17,以在半导体基底10上形成垂直于所述半导 [0004] FIG 1a~ Figure 1d shows a typical process of manufacturing FinFET structure, shown in Figure 1a, a semiconductor substrate 10, 10 on the predefined semiconductor substrate a plurality of semiconductor fins position, in the semiconductor substrate 10 are sequentially formed on the pad oxide layer 11 and the hard mask layer (not shown), patterned hard mask layer, a patterned hard mask layer 12 corresponding to the plurality of semiconductor fins in a position to cover the predefined ; shown in Figure 1b, the hard mask layer 12 is patterned mask, the semiconductor substrate 10 is etched to form a semiconductor fin 13, and a semiconductor is formed between the respective fins 13 recess 14 ; shown in FIG. 1C, removing the hard mask layer and the pad oxide layer, dielectric material 15, such as high density plasma (HDP) oxide, tetraethoxysilane (TEOS) oxide or the like, filling the recess 14; FIG. 1d, etching back said dielectric material is filled in the recess 14, to expose a predetermined height of the semiconductor fin 13, and forming a gate dielectric layer on the semiconductor fin 13 thermally oxidizing the surface 16, a polysilicon layer 17 is deposited last, to form a vertical on the semiconductor substrate 10 to the semiconductor 体鳍状物13延伸方向的栅极17。 The gate member 17 extending in the direction of the fin 13.

[0005]在FinFET结构的实际制造过程中,半导体基底10的材料一般为单晶硅,进行刻蚀形成半导体鳍状物时容易对单晶硅的结晶结构产生破坏,进而产生缺陷,使得载流子迀移率变低,且由于刻蚀的难以精确控制,半导体鳍状物形成时的表面(即刻蚀后的表面)粗糙度较高,进而导致其表面上形成的栅介质层中存在电荷捕获陷阱,进而影响器件性能。 [0005] In the actual manufacture of the FinFET structure, the material of the semiconductor substrate 10 is typically monocrystalline silicon, single crystal silicon be prone to damage during etching of the crystal structure of the semiconductor fin is formed, thereby generating defects, so that the carrier Gan sub shift becomes low, and because of difficult to precisely control the etching, the surface (i.e., the surface after etching) when forming a semiconductor fin roughness higher, leading to the gate dielectric layer formed on the surface present in the charge trapping trap, thereby affecting device performance. 再者,在现有的FinFET结构的制造方法中,工艺流程过于繁琐,因此,如何简化其工艺流程,与现有CMOS工艺融合也是亟待解决的问题。 Moreover, in the conventional method of manufacturing FinFET structures, the process is too cumbersome, and therefore, how to simplify their processes, integration problems are to be solved with existing CMOS process.

发明内容 SUMMARY

[0006]鉴于现有技术的缺陷,本发明提供一种形成FinFET的方法,在简化了现有工艺流程的同时,避免了在形成半导体鳍状物时其表面形貌粗糙度较高,对硅结晶产生破坏的问题。 [0006] In view of the deficiencies of the prior art, the present invention provides a method of forming a FinFET, the conventional simplified process flow, while avoiding high roughness surface morphology at the time of forming the semiconductor fin, silicon crystallization problems damage.

[0007]本发明采用的技术手段如下:一种形成FinFET的方法,包括: [0007] The technical means adopted by the invention as follows: A method of forming a FinFET, comprising:

[0008]提供半导体基底,所述半导体基底上预定有有源区,且所述预定义的有源区中预定义有半导体鳍状物的位置; [0008] providing a semiconductor substrate, a predetermined active region on the semiconductor substrate, the active region and the predefined predefined position where the semiconductor fin;

[0009]在所述半导体基底上依次形成有衬垫氧化层和硬掩膜层; [0009] is formed with a pad oxide layer and a hard mask layer are sequentially formed on the semiconductor substrate;

[0010]在所述硬掩膜层上形成图案化的光阻胶层,图案化的光阻胶层窗口对应于所述预定义的半导体鳍状物位置; [0010] subbing layer forming a photoresist pattern on the hard mask layer, the adhesive layer patterned photoresist window corresponds to the predefined position of the semiconductor fin;

[0011]以所述图案化的光阻胶层为屏蔽,依次刻蚀硬掩膜层以及衬垫氧化层,以形成凹陷,所述凹陷底部暴露所述半导体基底表面; [0011] In the adhesive layer of the patterned photoresist mask is sequentially etching the hard mask layer and the pad oxide layer to form a recess, the recess bottom surface of said semiconductor substrate exposed;

[0012]通过外延,在所述凹陷底部暴露的半导体基底表面处形成半导体层,所述半导体层填充所述凹陷; [0012] formed at the surface of the semiconductor layer exposed at the bottom of the recess of the semiconductor substrate by epitaxy, the semiconductor layer filling said recess;

[0013]依次刻蚀去除所述硬掩膜层和衬垫氧化层,以暴露的所述半导体层为半导体鳍状物; [0013] In order to remove the hard mask layer, and etching the pad oxide layer of the semiconductor layer to expose the semiconductor fin;

[0014]在所述半导体鳍状物表面热氧化形成栅介质层; [0014] forming a gate dielectric layer on the surface of the thermal oxidation of the semiconductor fin;

[0015]在半导体基底上沉积多晶硅层,形成垂直于半导体鳍状物延伸方向的栅极。 [0015] depositing a polysilicon layer on the semiconductor substrate, forming a gate extending perpendicular to a direction of the semiconductor fin.

[0016]进一步,在所述半导体基底上依次形成有衬垫氧化层和硬掩膜层之后,形成所述窗口对应于所述预定义的半导体鳍状物位置的图案化光阻胶之前,还包括刻蚀形成浅沟槽隔离的步骤,该步骤包括: Before After [0016] Further, on the semiconductor substrate are sequentially formed on the pad oxide layer and a hard mask layer, forming a patterned photoresist gum window corresponding to the predefined position of the semiconductor fin, further comprising the step of forming shallow trench isolation etching, comprising the steps of:

[0017]依次刻蚀所述衬垫氧化层和硬掩膜层,以在所述预定的有源区两侧的半导体基底中形成浅沟槽; [0017] sequentially etching the oxide layer of the pad and the hard mask layer to the semiconductor substrate in a predetermined active region on both sides of the shallow trench is formed;

[0018]在所述半导体基底上沉积介电材料,并进行化学机械研磨,以使所述介电材料表面与所述硬掩膜表面齐平; [0018] depositing a dielectric on the semiconductor substrate dielectric material, and a chemical mechanical polishing such that the surface of the dielectric material and the hard mask flush with the surface;

[0019]在刻蚀所述衬垫氧化层时,还包括刻蚀去除位于所述半导体基底表面之上部分的所述介电材料的步骤。 [0019] When etching the pad oxide layer, further comprising the step of said dielectric material over the surface of the semiconductor substrate is removed by etching portion located.

[0020] 进一步,所述凹陷的深度为5nm至60nm。 [0020] Further, the depth of the recess is 5nm to 60nm.

[0021 ] 进一步,所述图案化的光阻胶层窗口的宽度为5nm至30nmo [0021] Further, the width of the patterned photoresist windows subbing layer is 5nm to 30nmo

[0022]进一步,采用干法刻蚀去除所述硬掩膜,所述干法刻蚀的参数包括,以二氟甲烷、六氟化硫、氮气以及氦气为刻蚀气体,电源功率为550至650瓦,偏压为55至65瓦,压力为2至1mTorr0 [0022] Further, dry etching using the hard mask is removed, the dry etching process parameters comprises to difluoromethane, sulfur hexafluoride, nitrogen and helium as the etching gas, a power of 550 to 650 W, a bias of 55 to 65 watts, a pressure of 2 to 1mTorr0

[0023]进一步,所述半导体基底的材料为单晶硅,所述半导体层的材料为单晶硅或掺杂的单晶硅,所述外延形成半导体层的温度为600至800摄氏度。 [0023] Further, the material of the semiconductor substrate is single crystal silicon material of the semiconductor layer is doped monocrystalline silicon or single crystal silicon, the epitaxial semiconductor layer forming temperature of 600 to 800 degrees Celsius.

[0024]采用本发明提供的形成FinFET的方法,无需通过刻蚀半导体基底形成半导体鳍状物,因此避免了现有技术中刻蚀半导体基底形成半导体鳍状物时其表面形貌粗糙度较高,对硅结晶产生破坏的问题,并且简化了制造工艺流程,与现有的CMOS工艺相融合,节省了生产成本。 [0024] The method of forming a FinFET according to the present invention provides, without the semiconductor fin is formed by etching a semiconductor substrate, thus avoiding the prior art, when etching the semiconductor substrate forming a semiconductor fin high roughness surface morphology , a problem of damage to the silicon crystal, and simplifies the manufacturing process to blend with the existing CMOS process, production cost is saved.

附图说明 BRIEF DESCRIPTION

[0025]图1a〜图1d为现有技术形成FinFET方法的结构流程示意图; [0025] FIG 1a~ FIG. 1d forming a FinFET structure process flow of the prior art is a schematic diagram;

[0026]图2为本发明公开的一种形成FinFET的方法流程图; [0026] FIG 2 discloses a flow chart of a method of forming a FinFET present invention;

[0027]图3a〜图3g为本发明一种形成FinFET方法的结构流程示意图。 Structural schematic flow diagram [0027] Figure 3g FIG 3a~ present an inventive method of forming a FinFET.

具体实施方式 Detailed ways

[0028]以下结合附图对本发明的原理和特征进行描述,所举实例只用于解释本发明,并非用于限定本发明的范围。 [0028] The following drawings in conjunction with the principles and features of this invention will be described, The examples are only for explaining the present invention and are not intended to limit the scope of the invention.

[0029 ]如图2所示,本发明提供了一种形成FinFET的方法,步骤包括: [0029] 2, the present invention provides a method of forming a FinFET, comprises:

[0030]提供半导体基底,所述半导体基底上预定有有源区,且所述预定义的有源区中预定义有半导体鳍状物的位置; [0030] providing a semiconductor substrate, a predetermined active region on the semiconductor substrate, the active region and the predefined predefined position where the semiconductor fin;

[0031 ]在所述半导体基底上依次形成有衬垫氧化层和硬掩膜层; [0031] is formed with a pad oxide layer and a hard mask layer are sequentially formed on the semiconductor substrate;

[0032]在所述硬掩膜层上形成图案化的光阻胶层,图案化的光阻胶层窗口对应于所述预定义的半导体鳍状物位置; [0032] subbing layer forming a photoresist pattern on the hard mask layer, the adhesive layer patterned photoresist window corresponds to the predefined position of the semiconductor fin;

[0033]以所述图案化的光阻胶层为屏蔽,依次刻蚀硬掩膜层以及衬垫氧化层,以形成凹陷,所述凹陷底部暴露所述半导体基底表面; [0033] In the adhesive layer of the patterned photoresist mask is sequentially etching the hard mask layer and the pad oxide layer to form a recess, the recess bottom surface of said semiconductor substrate exposed;

[0034]通过外延,在所述凹陷底部暴露的半导体基底表面处形成半导体层,所述半导体层填充所述凹陷; [0034] formed at the surface of the semiconductor layer exposed at the bottom of the recess of the semiconductor substrate by epitaxy, the semiconductor layer filling said recess;

[0035]依次刻蚀去除所述硬掩膜层和衬垫氧化层,以暴露的所述半导体层为半导体鳍状物; [0035] The hard mask layer is removed by etching sequentially and the pad oxide layer, to expose the semiconductor layer is a semiconductor fin;

[0036]在所述半导体鳍状物表面热氧化形成栅介质层; [0036] forming a gate dielectric layer on the surface of the thermal oxidation of the semiconductor fin;

[0037]在半导体基底上沉积多晶硅层,形成垂直于半导体鳍状物延伸方向的栅极。 [0037] depositing a polysilicon layer on the semiconductor substrate, forming a gate extending perpendicular to a direction of the semiconductor fin.

[0038]作为本发明的一种典型实施例,以下结合附图3a~3g对本发明的技术手段进行详细阐述。 [0038] As an exemplary embodiment of the present invention, in conjunction with the following figures 3a ~ 3g be elaborated technical means of the present invention.

[0039]如图3a所示,提供半导体基底20,其材料优选为单晶硅,半导体基底20上预定有有源区(未标示),且预定义的有源区中预定义有半导体鳍状物的位置(未示出);在半导体基底20上依次形成有衬垫氧化层21和硬掩膜层22,其中硬掩膜层22的材料优选为氮化硅,并优选采用干法刻蚀刻蚀硬掩膜22,干法刻蚀的参数包括,以二氟甲烷、六氟化硫、氮气以及氦气为刻蚀气体,电源功率为550至650瓦,偏压为55至65瓦,压力为2至1mTorr ; [0039] As shown in FIG 3a, a semiconductor substrate 20, which is preferably a monocrystalline silicon material, the predetermined active region (not shown) on the semiconductor substrate 20, and the predefined active area in the semiconductor fin has a predefined position (not shown) thereof; sequentially formed on the semiconductor substrate 20 with a pad oxide layer 21 and the hard mask layer 22, wherein the hard mask material layer 22 is preferably silicon nitride, and preferably using a dry etch engraved etching the hard mask 22, dry etching includes parameters to difluoromethane, sulfur hexafluoride, nitrogen and helium as the etching gas, a power of 550-650 W, a bias of 55 to 65W, the pressure 2 to 1 mTorr;

[0040]参照图3b,依次刻蚀衬垫氧化层21和硬掩膜层22,以在预定的有源区两侧的半导体基底20中形成浅沟槽23,该过程可通过先在硬掩膜层22上形成图案化光光阻胶然后以光阻胶为屏蔽刻蚀形成浅沟槽23,本领域技术人员还可通过其他惯用的技术手段实现,是以在此不再赘述; [0040] Referring to Figure 3b, sequentially etching the pad oxide layer 21 and the hard mask layer 22 to the semiconductor substrate on both sides of the active region 20 in a predetermined forming a shallow trench 23, the process by the first hard mask patterned light formed on the resist film 22 and then glue gum shallow trench photoresist mask 23 is formed as an etching skilled in the art by other techniques may also be implemented conventional means, it is not repeated here;

[0041 ]如图3c所示,在半导体基底20上沉积介电材料24,并进行化学机械研磨,以使介电材料24表面与硬掩膜22表面齐平,其中介电材料24可以为高密度等离子体(HDP)氧化物、四乙氧基硅烷(TEOS)氧化物等; [0041] Figure 3c, in the semiconductor substrate 20 is deposited over dielectric material 24, and a chemical mechanical polishing so that the surface of the dielectric material 24 and flush with the surface hard mask 22, the dielectric material 24 may be high density plasma (HDP) oxide, tetraethoxysilane (TEOS) oxide or the like;

[0042]在硬掩膜层22上形成图案化的光阻胶层,图案化的光阻胶层窗口对应于预定义的半导体鳍状物位置,在本实施例中,优选图案化的光阻胶层窗口的宽度为5nm至30nm;以图案化的光阻胶层为屏蔽,依次刻蚀硬掩膜层22以及衬垫氧化层21,以形成凹陷25,去除图案化的光阻胶层,参照图3d(其中光阻胶层未示出),其中,凹陷25底部暴露半导体基底20表面,本实施例中,凹陷的深度优选为5nm至60nm; [0042] subbing layer forming a photoresist pattern on the hard mask layer 22, the position of the semiconductor fin patterned photoresist adhesive layer corresponding to the predefined window, in the present embodiment, preferably the patterned photoresist window width subbing layer is 5nm to 30 nm; subbing layer using the photoresist pattern as mask, sequentially etching the hard mask layer 22 and pad oxide layer 21, to form a recess 25, the adhesive layer patterned photoresist is removed, Referring to FIG. 3d (wherein the subbing layer of photoresist, not shown), in which recess 25 the bottom surface of the semiconductor substrate 20 is exposed, in the present embodiment, the depth of the recess is preferably 5nm to 60 nm;

[0043]如图3e所示,通过外延,在凹陷25底部暴露的半导体基底20表面处形成半导体层26,半导体层26填充凹陷25,其中半导体层26可以为单晶硅,也可以为掺杂后的单晶硅,其中,外延形成半导体层的温度为600至800摄氏度; [0043] As shown in FIG 3E, by epitaxy, formed at the surface of the semiconductor substrate 20 is exposed at the bottom of the recess 25 of the semiconductor layer 26, semiconductor layer 26 filling recess 25, which may be a single crystal silicon semiconductor layer 26 may be doped after the temperature of the silicon single crystal, wherein an epitaxial semiconductor layer formed of 600 to 800 degrees Celsius;

[0044]参照图3f,依次刻蚀去除硬掩膜层22和衬垫氧化层21,并刻蚀去除位于半导体基底20表面之上部分的介电材料24,以暴露的半导体层26作为为半导体鳍状物26; [0044] Referring to FIG. 3f, sequentially etching the hard mask layer 22 is removed and the pad oxide layer 21, and etch removes the dielectric material 24 positioned over the surface portion of the semiconductor substrate 20, semiconductor layer 26 is exposed as a semiconductor a fin 26;

[0045]如图3g所示,在半导体鳍状物26表面热氧化形成栅介质层27,在半导体基底28上沉积多晶硅层28,并形成垂直于半导体鳍状物延伸方向的栅极28,栅介质层27及栅极28的形成,本领域技术人员可通过现有工艺和惯用技术手段实现,在此不再赘述。 As shown in FIG 3g [0045], 26 formed in the surface of the thermal oxidation of the semiconductor fin gate dielectric layer 27, polysilicon layer 28 is deposited on the semiconductor substrate 28, and gate electrode 28 is formed extending in a direction perpendicular to the semiconductor fin, gate forming a dielectric layer 27 and the gate 28, one skilled in the art and may be achieved by conventional prior art techniques, not described herein again.

[0046]综上所述,由于本发明通过刻蚀一定厚度的硬掩膜形成暴露半导体基底的凹陷,并通过外延在凹陷中形成半导体鳍状物,是以无需通过刻蚀半导体基底形成半导体鳍状物,因此避免了现有技术中刻蚀半导体基底形成半导体鳍状物时其表面形貌粗糙度较高,对硅结晶产生破坏的问题,并且简化了制造工艺流程,与现有的CMOS工艺相融合,节省了生产成本。 [0046] In summary, the present invention is formed in a semiconductor substrate is exposed hard mask by etching the recessed a predetermined thickness, and the recess is formed in the semiconductor fin by epitaxial, semiconductor fin is formed without etching the semiconductor substrate by was, thus avoiding high roughness surface morphology of the prior art which when etching the semiconductor substrate of the semiconductor fin is formed, problems of damage to the silicon crystal, and simplifies the manufacturing process, the conventional CMOS process integration, saving the cost of production.

[0047]以上所述仅为本发明的较佳实施例而已,并不用以限制本发明,凡在本发明的精神和原则之内,所做的任何修改、等同替换、改进等,均应包含在本发明保护的范围之内。 [0047] The foregoing is only preferred embodiments of the present invention but are not intended to limit the present invention, all within the spirit and principle of the present invention, any changes made, equivalent substitutions and improvements should be included within the scope of protection of the present invention.

Claims (5)

1.一种形成FinFET方法,包括: 提供半导体基底,所述半导体基底上预定有有源区,且所述预定义的有源区中预定义有半导体鳍状物的位置; 在所述半导体基底上依次形成有衬垫氧化层和硬掩膜层; 依次刻蚀所述衬垫氧化层和硬掩膜层,以在所述预定的有源区两侧的半导体基底中形成浅沟槽; 在所述半导体基底上沉积介电材料,并进行化学机械研磨,以使所述介电材料表面与所述硬掩膜表面齐平; 在所述硬掩膜层上形成图案化的光阻胶层,图案化的光阻胶层窗口对应于所述预定义的半导体鳍状物位置; 以所述图案化的光阻胶层为屏蔽,依次刻蚀硬掩膜层以及衬垫氧化层,以形成凹陷,所述凹陷底部暴露所述半导体基底表面; 通过外延,在所述凹陷底部暴露的半导体基底表面处形成半导体层,所述半导体层填充所述凹陷; 依次刻蚀去除所述硬掩膜 A FinFET comprising forming: providing a semiconductor substrate, a predetermined active region on the semiconductor substrate, and the predetermined region defined in the active semiconductor fin predefined location; said semiconductor substrate there are sequentially formed on the pad oxide layer and a hard mask layer; sequentially etching the oxide layer, the pad and the hard mask layer to the semiconductor substrate in a predetermined active region on both sides of the shallow trench is formed; in the semiconductor substrate depositing a dielectric material, and chemical mechanical polishing, so that the dielectric material surface flush with the surface of the hard mask; subbing layer forming a photoresist pattern on the hard mask layer , the adhesive layer patterned photoresist window corresponds to the predefined position of the semiconductor fin; subbing layer to the patterned photoresist as a mask, successively etched hard mask layer and the pad oxide layer, to form a recess bottom surface of the exposed semiconductor substrate; forming a semiconductor layer on the bottom surface of the exposed semiconductor substrate by epitaxial recess, filling the recess of the semiconductor layer; sequentially etching the hard mask is removed 和衬垫氧化层,并刻蚀去除位于半导体基底表面之上部分的介电材料,以暴露的所述半导体层为半导体鳍状物; 在所述半导体鳍状物表面热氧化形成栅介质层; 在半导体基底上沉积多晶硅层,形成垂直于半导体鳍状物延伸方向的栅极。 And the pad oxide layer, and the etch removes the dielectric material located on a surface portion of the semiconductor substrate, the semiconductor layer is exposed to a semiconductor fin; forming a gate dielectric layer on the surface of the thermal oxidation of the semiconductor fin; depositing a polysilicon layer on the semiconductor substrate, forming a gate extending perpendicular to a direction of the semiconductor fin.
2.根据权利要求1所述的方法,其特征在于,所述凹陷的深度为5nm至60nm。 2. The method according to claim 1, wherein the depth of the recess is 5nm to 60nm.
3.根据权利要求1所述的方法,其特征在于,所述图案化的光阻胶层窗口的宽度为5nm至30nm。 3. The method according to claim 1, wherein a width of the patterned photoresist windows subbing layer is 5nm to 30nm.
4.根据权利要求1所述的方法,其特征在于,采用干法刻蚀去除所述硬掩膜,所述干法刻蚀的参数包括,以二氟甲烷、六氟化硫、氮气以及氦气为刻蚀气体,电源功率为550至650瓦,偏压为55至65瓦,压力为2至lOmTorr。 4. The method according to claim 1, wherein dry etching the hard mask is removed, the dry etching process parameters comprises to difluoromethane, sulfur hexafluoride, nitrogen, and helium gas as the etching gas, a power of 550-650 W, a bias of 55 to 65 W, a pressure of 2 to lOmTorr.
5.根据权利要求1所述的方法,其特征在于,所述半导体基底的材料为单晶硅,所述半导体层的材料为单晶硅或掺杂的单晶硅,所述外延形成半导体层的温度为600至800摄氏度。 5. The method according to claim 1, wherein the semiconductor material of the substrate is single crystal silicon material of the semiconductor layer is doped monocrystalline silicon or single crystal silicon, the epitaxial semiconductor layer is formed temperature of 600 to 800 degrees Celsius.
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