CN104124168B - The forming method of semiconductor structure - Google Patents
The forming method of semiconductor structure Download PDFInfo
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- CN104124168B CN104124168B CN201310156943.9A CN201310156943A CN104124168B CN 104124168 B CN104124168 B CN 104124168B CN 201310156943 A CN201310156943 A CN 201310156943A CN 104124168 B CN104124168 B CN 104124168B
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
A kind of forming method of semiconductor structure, including：Substrate is provided, the substrate surface has fin；The first dummy gate layer is formed in the substrate and fin portion surface, the surface of first dummy gate layer is higher than the top surface of the fin；First dummy gate layer is planarized untill the top surface of fin is exposed；After the flatening process, the second dummy gate layer is formed in first dummy gate layer and fin portion surface；The dummy gate layer of etched portions first and the second dummy gate layer are developed across the side wall of the fin and the dummy grid of top surface until exposing at the top of fin and untill sidewall surfaces.In the semiconductor structure formed, the homogeneity and accuracy of the thickness of the grid structure of fin top surface improve.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, more particularly to a kind of forming method of semiconductor structure.
Background technology
With the rapid development of semiconductor fabrication, semiconductor devices is and higher towards higher component density
The direction of integrated level is developed.Transistor is just being widely used at present as most basic semiconductor devices, therefore with semiconductor
The raising of the component density and integrated level of device, the grid size of planar transistor is also shorter and shorter, traditional planar transistor
The control ability of channel current is died down, produces short-channel effect, produces leakage current, the final electrical property for influenceing semiconductor devices
Energy.
In order to overcome the short-channel effect of transistor, suppress leakage current, prior art proposes fin formula field effect transistor
（Fin FET）, fin formula field effect transistor is a kind of common multi-gate device, refer to Fig. 1, and Fig. 1 is the fin of prior art
The dimensional structure diagram of FET, including：Semiconductor substrate 10；The fin protruded above positioned at the Semiconductor substrate 10
14；Cover the dielectric layer 11 of a part for the surface of Semiconductor substrate 10 and the side wall of fin 14, the table of the dielectric layer 11
Face is less than the top of the fin 14；Across the top of the fin 14 and the grid structure 12 of side wall, the grid structure 12
Including gate dielectric layer（It is not shown）With the gate electrode on the gate dielectric layer（It is not shown）.It should be noted that for fin
The part that formula FET, the top of fin 14 and the side wall of both sides are in contact with grid structure 12 turns into channel region, that is, has
There are multiple grid, be advantageous to increase driving current, improve device performance.
In the prior art, in order to further improve the performance of fin formula field effect transistor, the gate dielectric layer is situated between using high K
Material, the gate electrode layer use metal, i.e. fin formula field effect transistor forms high-K metal gate（High-k Metal
Gate, HKMG）Transistor, the fin formula field effect transistor of the high-K metal gate structure can use rear grid（Gate Last）Work
Skill is formed.
However, in the prior art, when later grid technique forms the fin field effect pipe with high-K metal gate structure, it is located at
With the uneven thickness one of the grid structure of some fin top surfaces in semi-conductive substrate, and the thickness of grid structure
It is unmanageable, make the electrical property for some fin formula field effect transistors to be formed inconsistent, cause formed semiconductor devices
Performance be difficult to control.
The content of the invention
The present invention solves the problems, such as to be to provide a kind of forming method of semiconductor structure, the grid of raising fin top surface
The homogeneity and accuracy of the thickness of structure.
To solve the above problems, the present invention provides a kind of forming method of semiconductor structure, including：Substrate is provided, it is described
Substrate surface has fin；The first dummy gate layer, the surface of first dummy gate layer are formed in the substrate and fin portion surface
Higher than the top surface of the fin；First dummy gate layer is planarized untill the top surface of fin is exposed；
After the flatening process, the second dummy gate layer is formed in first dummy gate layer and fin portion surface；Etched portions first
Dummy gate layer and the second dummy gate layer are developed across the side wall of the fin untill fin top and sidewall surfaces are exposed
With the dummy grid of top surface.
Optionally, in addition to：Positioned at the mask layer of fin top surface, first dummy gate layer is also deposited on described cover
Film surface, the first dummy gate layer surface are equal to or higher than the mask layer surface.
Optionally, the technique of planarization first dummy gate layer is：Described in being planarized using CMP process
First dummy gate layer is untill the top surface of mask layer is exposed；After the first dummy gate layer is planarized, institute is etched back to
The first dummy gate layer is stated until the surface of first dummy gate layer flushes with fin portion surface；It is described be etched back to technique after,
Remove the mask layer.
Optionally, the technique that is etched back to is anisotropic dry etch process, and technological parameter is：Substrate bias power is less than
100W, etching gas include CF4、SF6Or NF3。
Optionally, the etching depth for being etched back to technique is controlled by advanced process control device.
Optionally, the formation process of the fin is：Semiconductor substrate is provided, the Semiconductor substrate is body substrate；
The body substrate surface forms mask layer；Opening, adjacent apertures as body substrate described in mask etching and are formed using the mask layer
Between body substrate formed fin；First medium layer, the first medium layer covering part fin are formed in the bottom of the opening
The sidewall surfaces in portion.
Optionally, the material of the body substrate is silicon, germanium or SiGe.
Optionally, the formation process of the fin is：Semiconductor substrate is provided, the Semiconductor substrate is semiconductor-on-insulator
Conductor substrate, the semiconductor-on-insulator substrate include insulating barrier and the semiconductor layer positioned at surface of insulating layer, and described half
The material of conductor layer is silicon or germanium；Mask layer is formed in the semiconductor layer surface；Using the mask layer as described in mask etching
Semiconductor layer forms the fin being located on insulating barrier untill surface of insulating layer is exposed.
Optionally, in addition to：After fin is formed, the first oxygen is formed using sidewall surfaces of the thermal oxidation technology in fin
SiClx layer, the thickness of first silicon oxide layer is 1 nanometer~5 nanometers.
Optionally, the formation process of the mask layer is multiple graphical masking process.
Optionally, when the formation process of the mask layer is Dual graphing masking process, the formation of the mask layer
Technique is：Sacrificial film is formed in semiconductor substrate surface；Patterned layer is formed in the part surface of the sacrificial film；With institute
State patterned layer for sacrificial film described in mask etching until Semiconductor substrate is exposed untill, formation sacrifice layer；Described half
Conductor substrate and sacrificial layer surface deposition mask film；The mask film is etched back to untill Semiconductor substrate is exposed,
Mask layer is formed, and removes the sacrifice layer.
Optionally, after fin is formed, thermal anneal process is carried out, the temperature of the thermal anneal process is 900 degrees Celsius
~1100 degrees Celsius.
Optionally, the material of the mask layer is silicon nitride, silica or silicon oxynitride.
Optionally, when the material of the mask layer is silicon nitride, in addition to：The shape between the top of fin and mask layer
Into the second silicon oxide layer.
Optionally, the material of first dummy gate layer and the material of the second dummy gate layer are identical or different.
Optionally, the formation process of first dummy gate layer or the second dummy gate layer is chemical vapor deposition method or thing
Physical vapor deposition technique；The material of first dummy gate layer or the second dummy gate layer be DOPOS doped polycrystalline silicon, non-impurity-doped polysilicon,
Amorphous silicon, SiGe or amorphous carbon.
Optionally, the chemical vapor deposition method parameter of formation second dummy gate layer is：Temperature is that 200-800 is Celsius
Degree, air pressure are the support of 1 support -100, and power is 300 watts~600 watts, and gas includes HCl and H2, HCl flow for 1sccm~
1000sccm, H2Flow be 0.1slm~50slm；When the material of the second dummy gate layer is non-impurity-doped polysilicon, the gas
Body also includes silicon source gas SiH4Or SiH2Cl2, the flow of the silicon source gas is 1sccm~1000sccm；When the second dummy grid
When the material of layer is SiGe, the gas also includes silicon source gas SiH4Or SiH2Cl2With ge source gas GeH4, the silicon source gas
The flow of body is 1sccm~1000sccm, and the flow of the ge source gas is 1sccm-1000sccm.
Optionally, the formation process of the dummy grid is：Pseudo- grid mask, the pseudo- grid are formed on the second dummy gate layer surface
Mask defines the figure of dummy grid, and the material of the pseudo- grid mask is silicon nitride or silicon oxynitride；Carved with the pseudo- grid mask
The second dummy gate layer and the first dummy gate layer are lost untill fin top and sidewall surfaces are exposed.
Optionally, before the first dummy gate layer is formed, sunk in the side wall and top surface of the substrate surface and fin
The 3rd silicon oxide layer of product.
Optionally, in addition to：After dummy grid is formed, source region and leakage are formed in the fin of the dummy grid both sides
Area；After the source region and drain region is formed, second medium is formed in the side wall and top surface of the substrate surface and fin
Layer, the surface of the second dielectric layer flushes with the top surface of dummy grid；After second dielectric layer is formed, in the removal
The dummy grid simultaneously forms opening in second dielectric layer；Gate dielectric layer is formed in the opening, in the gate dielectric layer table
Face forms the gate electrode layer of the full opening of filling.
Compared with prior art, technical scheme has advantages below：
After substrate and fin portion surface deposit the first dummy gate layer, first dummy gate layer is planarized until exposing
The top of fin, the second dummy gate layer is formed then at first dummy gate layer and fin portion surface, then second dummy gate layer
Thickness can accurately be controlled by technique, and the thickness of the second dummy gate layer of diverse location in the substrate can be made equal
It is even.The side wall of fin and the puppet of top surface are developed across subsequently through second dummy gate layer and the first dummy gate layer is etched
Grid, the thickness for being formed at the dummy grid of fin top surface can be made accurate, and the dummy grid at the top of different fins is thick
Size uniformity is spent, improves the stability of formed semiconductor devices.
Further, the top surface of the fin also has mask layer, and the mask layer is used to define in preamble technique
The figure of fin, and etch to form fin with mask layer, first dummy gate layer is also deposited on the mask layer surface.It is described
The technique for planarizing the first dummy gate layer is：First dummy gate layer is polished using CMP process until exposing
Mask layer, the mask layer are used to be used as polishing stop layer, and protect injury-free at the top of fin.Use afterwards and be etched back to technique
The surface of the first dummy gate layer is set to be flushed with fin portion surface；It is described be etched back to technique can by adjust etch rate and etching when
Between and accurately control etching depth, so as to make the surface of the first dummy gate layer be flushed with fin portion surface.
Further, the etching depth for being etched back to technique is controlled by advanced process（APC, Advanced
Process Control）Device is controlled；The advanced process control device can detect positioned at substrate diverse location
One dummy gate layer surface, the high low state in the surface of the first dummy gate layer after being polished；The first measured dummy gate layer
Surface state, with reference to the parameter for being etched back to technique, such as etch rate and etch period, the of substrate diverse location can be obtained
The depth being etched back to needed for one dummy gate layer；It ensure that the surface of the first dummy gate layer after being etched back to is uniform, after then making
It is continuous be formed at the first dummy gate layer surface the second dummy gate layer surface it is uniform.
Further, when the material difference of first dummy gate layer and the second dummy gate layer, when the second pseudo- grid of etching
Pole layer is to exposing after the first dummy gate layer, it is necessary to change etching gas to continue to etch the first dummy gate layer until exposing
Untill substrate, and easy damaged has not completed the second dummy gate layer etched to the gas of etching first dummy gate layer, so as to
It ensure that the pattern of the dummy grid across fin is good, it is stable to be advantageous to formed device performance.
Brief description of the drawings
Fig. 1 is the dimensional structure diagram that prior art forms fin field effect pipe；
Fig. 2 to Fig. 4 is the cross-sectional view for the process that prior art forms fin field effect pipe；
Fig. 5 to Figure 12 is the cross-sectional view of the forming process of the semiconductor structure of embodiments of the invention.
Embodiment
As stated in the Background Art, the thickness heterogeneity and size of the grid structure of the fin top surface of prior art
Inaccurately.
In one embodiment, the forming process of high-K metal gate structure is formed as shown in Figures 2 to 4 in fin portion surface.
It refer to Fig. 2, there is provided Semiconductor substrate 10, the fin 14 protruded above positioned at the Semiconductor substrate 10 and cover
The dielectric layer 11 of the surface of Semiconductor substrate 10 and the partial sidewall of fin 14 is covered, on the surface of dielectric layer 11 and the side wall of fin 14
Dummy gate layer 15 is deposited with top surface, the dummy gate layer 15 fills the opening between full phase neighbour fin 14（It is not shown）.
Fig. 3 is refer to, dummy gate layer 15 is planarized using CMP process.
Fig. 4 is refer to, Fig. 4 is based on sections of the Fig. 3 along CC ' directions, and etched portions dummy gate layer 15 is until expose fin
Untill 14 tops and the surface of sidewall surfaces and dielectric layer 11, the side wall of the fin 14 and the puppet of top surface are developed across
Grid 15a.
After dummy grid 15a is formed, formation source region and drain region in the fin 14 of the dummy grid 15a both sides, and
The surface of dielectric layer 11, the side wall of fin 14 and top surface and dummy grid 15a surfaces depositing insulating layer；Chemical machinery
The insulating barrier is polished untill dummy grid 15a top surfaces are exposed；Afterwards, the dummy grid 15a is removed and former pseudo-
Grid 15a position forms gate dielectric layer and the gate electrode layer on gate dielectric layer surface.
Because depositing insulating layer using CMP process afterwards, it is necessary to planarize the insulating barrier until exposing
Untill dummy grid, the insulating barrier is set to replicate the shape of the dummy grid completely, and conveniently subsequently remove the dummy grid.
In order to which the top surface of the dummy grid can be completely exposed, it is necessary to make the top of the dummy grid after the insulating barrier is polished
Surface is flat, it is therefore desirable to after dummy gate layer is deposited, first dummy gate layer is planarized, then etch the dummy gate layer with shape
Into dummy grid.However, when planarizing the dummy gate layer using CMP process, it is difficult to after control polishing at the top of fin
The thickness of remaining dummy gate layer；And after a polish, the dummy gate layer positioned at same semi-conductive substrate diverse location is deposited
In difference in height, cause the thickness for the dummy gate layer that the fin top surface of same semi-conductive substrate diverse location formed
Homogeneity is poor.Therefore, the fin field effect pipe characteristic size with high-K metal gate structure formed with prior art is homogeneous
The bad and accuracy of property is poor.
Further studied by the present inventor, prior art is improved, sunk in substrate and fin portion surface
After the first dummy gate layer of product, first dummy gate layer is planarized until exposing the top surface of fin, then at described the
One dummy gate layer and fin portion surface form the second dummy gate layer, then the thickness of second dummy gate layer can be accurate by technique
Control, and the thickness positioned at the second dummy gate layer of diverse location in substrate can be made uniform.Subsequently through etching described the
Two dummy gate layers and the first dummy gate layer are developed across the side wall of fin and the dummy grid of top surface, can make to be formed at fin
The thickness of the dummy grid of top surface is accurate, and the dummy grid thickness at the top of different fins is homogeneous, improves institute's shape
Into semiconductor devices stability.
It is understandable to enable the above objects, features and advantages of the present invention to become apparent, below in conjunction with the accompanying drawings to the present invention
Specific embodiment be described in detail.
Fig. 5 to Figure 12 is the cross-sectional view of the forming process of the semiconductor structure of embodiments of the invention.
It refer to Fig. 5, there is provided substrate 200, the surface of substrate 200 have fin 201, the top table of the fin 201
Face has mask layer 202.
In the present embodiment, the substrate 200 and fin 201 are a part for the Semiconductor substrate provided, wherein, institute
The platform that substrate 200 provides subsequent technique is stated, the fin 201 is formed by etching the Semiconductor substrate；The semiconductor
Substrate includes body substrate or semiconductor-on-insulator substrate；The material of the body substrate includes silicon, germanium and SiGe；The insulator
Semiconductor substrate thereon includes substrate, the insulating barrier positioned at substrate surface and the semiconductor layer positioned at surface of insulating layer, and described half
The material of conductor layer includes silicon or germanium.
When the Semiconductor substrate is body substrate, the formation process of the fin 201 is：In the body substrate surface shape
Into mask layer 202；It is body substrate described in mask etching with the mask layer 202 and forms opening, the body lining between adjacent apertures
Bottom forms fin 201, and the remaining body substrate positioned at the bottom of fin 201 forms substrate 200.In the present embodiment, the fin 201
Formed by etching body substrate, and the remaining body substrate positioned at the bottom of fin 201 forms substrate 200.
It should be noted that when the Semiconductor substrate is body substrate, and fin 201 is formed by etching body substrate,
Etching is formed after fin 201, in the substrate 200 and the surface of fin 201 deposition first medium film；It is etched back to described first
Dielectric film is until expose the top and partial sidewall surface of fin 201, in the bottom of opening formation first medium layer
203, the surface of the first medium layer 203 is less than the sidewall surfaces of the top surface of fin 201 and covering part fin 201.
When the Semiconductor substrate is semiconductor-on-insulator substrate, the formation process of the fin is：In semiconductor
Layer surface forms mask layer 202；With the mask layer 202 for semiconductor layer described in mask etching until exposing surface of insulating layer
Untill, form the fin being located on insulating barrier.Wherein, Jie of the insulating barrier in semiconductor-on-insulator substrate as isolation fin
Matter layer, and the substrate in semiconductor-on-insulator substrate is as substrate.
In other embodiments, the fin can also be formed at provided semiconductor substrate surface, and formation process is：
The dielectric layer with opening is formed in semiconductor substrate surface, described be open defines figure and the position of fin, and exposes
Semiconductor substrate surface；Fin is formed using epitaxial deposition process in the opening, and is etched back to the dielectric layer, makes medium
Layer surface is less than fin portion surface.
In addition, after fin 201 is formed, thermal anneal process is carried out, to eliminate the defects of fin 201, makes to be formed
Fin field effect pipe channel region it is functional；The temperature of the thermal anneal process is 900 degrees Celsius~1100 degrees Celsius, is moved back
Internal heat body is hydrogen or helium.
The mask layer 202 is as mask when etching the Semiconductor substrate to form fin 201, moreover, described cover
Film layer 202 when subsequently polishing and being etched back to the first dummy gate layer, can also protect the top of fin 201 from damage.It is described
The material of mask layer 202 is silicon nitride, silica or silicon oxynitride；When the material of the mask layer 202 is silicon nitride, in order to
Strengthen the binding ability of silicon nitride and semiconductor substrate surface, can also be formed between semiconductor substrate surface and mask layer 202
Second silicon oxide layer 210, as Semiconductor substrate to the transition between mask layer 202, that is, the fin 201 and mask layer formed
There is the second silicon oxide layer 210 between 202；The formation process of second silicon oxide layer 210 is thermal oxidation technology or deposition work
Skill, the thickness of second silicon oxide layer 210 is 1 nanometer~5 nanometers.In the present embodiment, the top surface of the fin 201
Formed with the second silicon oxide layer 210, the layer surface of the second silicon oxide layer 210 is formed with the mask layer using silicon nitride as material
202。
It should be noted that the quantity of the fin 201 is single or multiple, adjacent set present embodiment illustrates 3
The fin 201 put；In order that the size of fin 201 formed is small, and the size between adjacent fin 201 is small, the mask layer
202 formation process is multiple graphical masking process, such as self-alignment duplex pattern（Self-aligned Double
Patterned, SaDP）Technique, autoregistration are triple graphical（Self-aligned Triple Patterned）Technique or from
It is graphical to be directed at quadruple（Self-aligned Double Double Patterned, SaDDP）Technique.
In the present embodiment, the formation process of the mask layer 202 is Dual graphing masking process, and formation process is：
Sacrificial film is formed in semiconductor substrate surface；Patterned layer is formed in the part surface of the sacrificial film, it is described graphical
Layer can use photoetching process, nanoimprinting process or orientation self-assembly process to be formed；Photoetching process shape is used in the present embodiment
Into the patterned layer, the material of patterned layer is photoresist；It is straight as sacrificial film described in mask etching using the patterned layer
Untill Semiconductor substrate is exposed, sacrifice layer is formed；In the Semiconductor substrate and sacrificial layer surface deposition mask film；Return
The mask film is etched untill Semiconductor substrate is exposed, forms mask layer, and remove sacrifice layer.
In addition, after fin 201 is formed, the first oxidation is formed in the sidewall surfaces of fin 201 using thermal oxidation technology
Silicon layer 211, the thickness of first silicon oxide layer 211 is 1 nanometer~5 nanometers, and first silicon oxide layer 211 can be follow-up
When etching the first dummy gate layer and the second dummy gate layer to form dummy grid, protect the sidewall surfaces of fin 201 from damage.
Fig. 6 is refer to, the first dummy gate layer is formed on the first medium layer 203, fin 201 and the surface of mask layer 202
204, the surface of first dummy gate layer 204 is equal to or the top surface higher than the mask layer 202.
First dummy gate layer 204 and the second dummy gate layer being subsequently formed are provided commonly for forming dummy grid, the puppet
Grid takes up space for the required high-K metal gate structure formed；The formation process of first dummy gate layer 204 is deposition work
Skill, including chemical vapor deposition method or physical gas-phase deposition, the material of first dummy gate layer 204 is doped polycrystalline
Silicon, non-impurity-doped polysilicon, amorphous silicon, SiGe or amorphous carbon；In addition, before the first dummy gate layer 204 is formed, described
The side wall and top surface of the surface of substrate 200 and fin 201 deposit the 3rd silicon oxide layer（It is not shown）, the 3rd silicon oxide layer
Can be further in subsequent technique, such as etching protects the sidewall surfaces of fin 201 from damage when forming dummy gate layer.
In subsequent technique, in order to ensure that the dummy grid thickness for being formed at the top of fin 201 is accurate homogeneous, it is necessary to described
First dummy gate layer 204 is polished to the surface of mask layer 202, and is etched back to the top surface of fin 201, so as to subsequently described
Uniform accurate second dummy gate layer of one dummy gate layer 204 and the surface deposit thickness of fin 201, it is therefore desirable to deposit the of formation
The surface of one dummy gate layer 204 is above the top of fin 201 and equal to or higher than the top surface of mask layer 202；And the fin
201 protrude from the surface of first medium layer 203, the formed surface of the first dummy gate layer 204 is had height difference, in order to
Ensure the top surface of the surface of the first dummy gate layer 204 after glossing not less than fin 201, it is necessary to ensure described the
The lowest part on the surface of one dummy gate layer 204 is not less than the top of mask layer 202.
Fig. 7 is refer to, planarizes first dummy gate layer 204 untill the top surface of mask layer 202 is exposed.
The flatening process is CMP process, in the CMP process, the mask layer
202 define the stop position of the glossing, and due to the protection of the mask layer 202, the top of the fin 201
It will not be sustained damage in the glossing.
However, because the glossing stops at mask layer 202, therefore the table of the first dummy gate layer 204 after polishing
Face is still higher than the top of fin 201；Moreover, the CMP process is for positioned at the surface diverse location of substrate 200
The polishing uniformity of first dummy gate layer 204 differs, and easily causes the first dummy gate layer 204 of the surface diverse location of substrate 200
It is highly inconsistent after by glossing；If pseudo- grid are formed with the first dummy gate layer 204 etching by polishing
Pole, the characteristic size of formed fin field effect pipe can be caused inconsistent, the device stability formed is deteriorated.
Therefore, it is necessary to make the first dummy gate layer 204 using technique is etched back to after the CMP process
Surface is flushed with the surface of fin 201, and the in uniform thickness second pseudo- grid are formed then at the surface of 201 and first dummy gate layer of fin 204
Pole layer, then the dummy grid size uniform that can be formed etching, the distance at dummy grid surface to the top of fin 201 are accurate.
Fig. 8 is refer to, after the first dummy gate layer 204 is planarized, is etched back to first dummy gate layer 204 until institute
The surface for stating the first dummy gate layer 204 flushes with the surface of fin 201.
The technique that is etched back to is anisotropic dry etch process, and technological parameter is：Substrate bias power is less than 100W, carves
Erosion gas includes CF4、SF6Or NF3；The anisotropic dry etch process controls etching deep by controlling etch period
Degree, and the etching depth for being etched back to technique can also be controlled by advanced process（APC, Advanced Process
Control）Device is accurately controlled.
The advanced process control device includes detection means, arithmetic unit and control device；Wherein, the detection means
For the surface state for the first dummy gate layer 204 after polishing for detecting the whole surface of substrate 200；Specific to first
The height difference on the surface of dummy gate layer 204 is detected, to determine the first dummy gate layer 204 in whole substrate 200
Height distribution；The height distribution of the first overall dummy gate layer 204 and the anisotropic dry are carved
The parameters input arithmetic unit of etching technique, to obtain etching needed for the diverse location for whole first dummy gate layer 204
Depth, to ensure that the surface of the first dummy gate layer 204 after being etched back to can flush with the top surface of fin 201；Control
Device processed is etched back to work according to being carried out the etching depth data for the diverse location of the first dummy gate layer 204 that arithmetic unit obtains
Skill, the top surface of the first dummy gate layer 204 after etching can flush with the top surface of fin 201.Using the elder generation
Being etched back to technique described in the control of system process control device can ensure that the surface of the first dummy gate layer 204 after being etched back to is uniform,
Make to be subsequently formed and equally keep uniform in the second dummy gate layer surface in uniform thickness on the first dummy gate layer surface, be subsequently formed
It is homogeneous in the thickness of the dummy grid of the fin top surface of the diverse location of substrate 200, it is ensured that the device performance formed is stable.
It should be noted that in the present embodiment, the second oxidation is also formed between the fin 201 and mask layer 203
Silicon layer 210, the thickness of second silicon oxide layer 210 is 1 nanometer~5 nanometers；The present embodiment be etched back to after the first dummy grid
The surface of layer 204 flushes with the surface of second silicon oxide layer 210, due to the very thin thickness of second silicon oxide layer 210,
The surface of the first dummy gate layer 204 can be made to be flushed with the top surface of fin 201.Second silicon oxide layer 210 can also
The top surface of fin 201 is protected to be damaged to reduce when subsequent etching forms dummy grid.
Refer to Fig. 9, it is described be etched back to technique after, remove the mask layer 202（As shown in Figure 8）And expose fin
Second silicon oxide layer 210 of the top surface in portion 201.
The technique for removing mask layer 202 is etching technics, including dry etching and wet etching；The mask layer
202 material is silicon nitride, silica or silicon oxynitride, when removing mask layer 202 using wet etching, the wet etching
Etching liquid include：Phosphoric acid（Etch silicon nitride）And/or hydrofluoric acid（Etching oxidation silicon）, when using dry etching removal mask layer
When 202, etching gas include CHF3（Etching oxidation silicon）And/or CF4（Etch silicon nitride）, the dry etching can be it is each to
The opposite sex or isotropism；Pass through the ratios of the etch liquids that adjust wet etching or the ratio of the etching gas of dry etching, control
The selection ratio of etching technics processed, to remove silicon nitride, silica or silicon oxynitride.
In the present embodiment, formed with the second silicon oxide layer 210, the mask layer 202 is formed at the top of the fin
The surface of silicon dioxide layer 210, the mask layer 202 is removed using wet-etching technology and retains second silicon oxide layer 210,
Damage of the wet-etching technology to the second silicon oxide layer 210 is smaller, and removal mask layer 202 is quickly thorough, and described second
Silicon oxide layer 210 can also protect the top surface of fin 201 when subsequent etching forms dummy grid.
Flush, go with the surface of the second silicon oxide layer 210 moreover, being etched back to the first dummy gate layer 204 in the present embodiment
After the mask layer, first dummy gate layer 204 and the entirety of the second silicon oxide layer 210 formation on the surface of fin 201
Surfacing, subsequently in first dummy gate layer 204 and fin 201 after uniform second dummy gate layer of deposit thickness,
The surfacing of second dummy gate layer, the dummy grid thickness for being advantageous to make to be formed at the top surface of fin 201 are accurately homogeneous.
Figure 10 and Figure 11 are refer to, Figure 11 is cross-sectional views of the Figure 10 along BB ' directions, is removing the mask layer
202（As shown in Figure 8）Afterwards, the second dummy gate layer 205 is formed in first dummy gate layer 204 and the surface of fin 201.
The material of second dummy gate layer 205 is DOPOS doped polycrystalline silicon, non-impurity-doped polysilicon, amorphous silicon, SiGe or nothing
Shape carbon；The material of first dummy gate layer 204 and the material of the second dummy gate layer 205 are identical or different；Especially, institute is worked as
When stating the material difference of the first dummy gate layer 204 and the second dummy gate layer 205, the dummy grid for forming subsequent etching is more beneficial for
Pattern it is good：Specifically, when the second dummy gate layer of subsequent etching 205 to after exposing the first dummy gate layer 204, it is necessary to more
Etching gas are changed, to continue to etch the first dummy gate layer 204 untill first medium layer 203 is exposed, when the described first puppet
During the material difference of the dummy gate layer 205 of grid layer 204 and second, the gas of second dummy gate layer 205 not easy damaged is etched
The second dummy gate layer 205 etched, so as to ensure that the pattern for the dummy grid for being located at the top surface of fin 201, be advantageous to institute
The device performance of formation is stable.
The formation process of second dummy gate layer 205 is chemical vapor deposition method or physical gas-phase deposition, compared with
Good is chemical vapor deposition method；Forming the chemical vapor deposition method parameter of second dummy gate layer 205 includes：Temperature
For 200-800 degrees Celsius, air pressure is the support of 1 support -100, and power is 300 watts~600 watts, and gas includes HCl and H2, HCl flow
For 1sccm~1000sccm, H2Flow be 0.1slm~50slm；When the material of the second dummy gate layer is non-impurity-doped polysilicon
When, the gas also includes silicon source gas SiH4Or SiH2Cl2, the flow of the silicon source gas is 1sccm~1000sccm；When
When the material of second dummy gate layer is SiGe, the gas also includes silicon source gas SiH4Or SiH2Cl2With ge source gas GeH4,
The flow of the silicon source gas is 1sccm~1000sccm, and the flow of the ge source gas is 1sccm-1000sccm.Describedization
The sedimentation rate of gas-phase deposition is controllable, therefore can accurately control formed second pseudo- by controlling sedimentation time
The thickness of grid layer 205.Furthermore it is possible to during the chemical vapor deposition method, by doping process in situ more
Doped p-type ion or N-type ion in crystal silicon material.
The thickness of the second dummy gate layer 205 formed using the depositing operation is uniform, and in whole substrate 200
Flushed uniformly with the surface of the second silicon oxide layer 210 by the first dummy gate layer 204 being etched back to, therefore second dummy grid
The surfacing of layer 205 is uniform, the dummy grid that the second dummy gate layer 205 described in subsequent etching and the first dummy gate layer 204 are formed
Afterwards, the dummy grid thickness positioned at the top surface of fin 201 is uniformly accurate.
On the basis of Figure 11, Figure 12 is refer to, etched portions the first dummy gate layer 204 and the second dummy gate layer 205 are straight
Untill the top of fin 204 and sidewall surfaces are exposed, the side wall of the fin 201 and the dummy grid of top surface are developed across
（It is not shown）.
The formation process of the dummy grid is：Pseudo- grid mask 212, the pseudo- grid are formed on the surface of the second dummy gate layer 205
Mask 212 defines the figure of dummy grid；Second dummy gate layer 205 and the first dummy gate layer are etched with the pseudo- grid mask 212
204（As shown in Figure 10）Untill the top of fin 201 and sidewall surfaces and first medium layer 203 is exposed, it is developed across
The side wall and top surface of the fin 201 and the dummy grid on the surface of first medium layer 203.Wherein, the pseudo- grid mask
212 material is silicon nitride or silicon oxynitride.
First dummy gate layer 204 is by CMP process and is etched back to technique, its surface and the second silicon oxide layer
210 flush, and the first dummy gate layer 204 being located in overall substrate 200 and the surface of the second silicon oxide layer 210 are flat；Second is pseudo-
The thickness of grid layer 205 can accurately be controlled and uniformly by depositing operation, positioned at the first dummy gate layer of whole substrate 200
204 and the surface of the second dummy gate layer 205 on the surface of the second silicon oxide layer 210 can also keep flat；With the second dummy gate layer 205
The top surface of the dummy grid formed with the first dummy gate layer 204 etching is uniform, and easy higher than the accurate size at the top of fin 201
Control.
It should be noted that after dummy grid is formed, source region and leakage are formed in the fin 204 of the dummy grid both sides
Area（It is not shown）；After the source region and drain region is formed, in the side wall of the surface of first medium layer 203 and fin 201 and
Top surface forms second dielectric layer（It is not shown）, the surface of the second dielectric layer flushes with the top surface of dummy grid；
Form second dielectric layer and then remove the dummy grid and opening is formed in second dielectric layer（It is not shown）；Opened described
Intraoral formation gate dielectric layer（It is not shown）, the gate electrode layer for filling the full opening is formed on the gate dielectric layer surface（Do not show
Go out）.
In the present embodiment, the first dummy gate layer 204 is formed on first medium layer 203, fin 201 and the surface of mask layer 202,
First dummy gate layer 204 is polished to exposing mask layer 202 using CMP process, then is etched back to the first pseudo- grid
Pole layer 204 flushes to the top surface of fin 201, removes mask layer 202 afterwards and in the dummy gate layer 204 of fin 201 and first
Uniform accurate second dummy gate layer 205 of surface deposit thickness, the surface uniform ground of second dummy gate layer 205, and it is high
Thickness in the top of fin 201 is accurately homogeneous, and the pseudo- grid formed are etched with the second dummy gate layer 205 and the first dummy gate layer 204
The high thickness in fin 201 is accurately homogeneous, is advantageous to make formed device performance stable.
In summary, after substrate and fin portion surface deposit the first dummy gate layer, first dummy gate layer is planarized
Until exposing the top of fin, the second dummy gate layer is formed then at first dummy gate layer and fin portion surface, then described the
The thickness of two dummy gate layers can accurately be controlled by technique, and can make the second dummy grid positioned at diverse location in substrate
The thickness of layer is uniform.Side wall and the top of fin are developed across subsequently through etching second dummy gate layer and the first dummy gate layer
The dummy grid on portion surface, the thickness for being formed at the dummy grid of fin top surface can be made accurate, and at the top of different fins
Dummy grid thickness it is homogeneous, improve the stability of formed semiconductor devices.
Further, the top surface of the fin also has mask layer, and the mask layer is used to define in preamble technique
The figure of fin, and etch to form fin with mask layer, first dummy gate layer is also deposited on the mask layer surface.It is described
The technique for planarizing the first dummy gate layer is：First dummy gate layer is polished using CMP process until exposing
Mask layer, the mask layer are used to be used as polishing stop layer, and protect injury-free at the top of fin.Use afterwards and be etched back to technique
The surface of the first dummy gate layer is set to be flushed with fin portion surface；It is described be etched back to technique can by adjust etch rate and etching when
Between and accurately control etching depth, so as to make the surface of the first dummy gate layer be flushed with fin portion surface.
Further, the etching depth for being etched back to technique is controlled by advanced process control device；The elder generation
System process control device can be detected positioned at the first dummy gate layer surface of substrate diverse location, the first pseudo- grid after being polished
The high low state in surface of pole layer；The surface state of the first measured dummy gate layer, with reference to being etched back to the parameter of technique, such as carve
Speed and etch period are lost, the depth being etched back to needed for the first dummy gate layer of substrate diverse location can be obtained；It ensure that back
The surface of the first dummy gate layer after etching is uniform, then makes to be subsequently formed in second dummy grid on the first dummy gate layer surface
Layer surface is uniform.
Further, during the material difference of first dummy gate layer and the second dummy gate layer, when etching the second dummy grid
Layer is to exposing after the first dummy gate layer, it is necessary to change etching gas to continue to etch the first dummy gate layer until exposing base
Untill bottom, and easy damaged has not completed the second dummy gate layer etched to the gas of etching first dummy gate layer, so as to protect
Demonstrate,prove that the pattern of the dummy grid across fin is good, it is stable to be advantageous to formed device performance.
Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art, this is not being departed from
In the spirit and scope of invention, it can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
The scope of restriction is defined.
Claims (18)
- A kind of 1. forming method of semiconductor structure, it is characterised in that including：Substrate is provided, the substrate surface has fin, and the top surface of the fin has mask layer；The first dummy gate layer is formed in the substrate, fin and mask layer surface, the surface of first dummy gate layer is higher than institute State the top surface of fin and be equal to or higher than the mask layer surface；First dummy gate layer is planarized untill the top surface of fin is exposed, the flatening process includes：First dummy gate layer is planarized untill the top surface of mask layer is exposed using CMP process；After CMP process planarizes the first dummy gate layer, first dummy gate layer is etched back to until described the The surface of one dummy gate layer flushes with fin portion surface；It is described be etched back to technique after, remove the mask layer；After the flatening process, the second dummy gate layer is formed in first dummy gate layer and fin portion surface；The dummy gate layer of etched portions first and the second dummy gate layer are formed horizontal until exposing at the top of fin and untill sidewall surfaces Across the side wall of the fin and the dummy grid of top surface.
- 2. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that the technique that is etched back to is anisotropy Dry etch process, technological parameter is：Substrate bias power is less than 100W, and etching gas include CF4、SF6Or NF3。
- 3. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that the etching depth for being etched back to technique It is controlled by advanced process control device.
- 4. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that the formation process of the fin is：Carry For Semiconductor substrate, the Semiconductor substrate is body substrate；Mask layer is formed in the body substrate surface；Using the mask layer as Body substrate described in mask etching simultaneously forms opening, and the body substrate between adjacent apertures forms fin；In the bottom shape of the opening Into first medium layer, the sidewall surfaces of the first medium layer covering part fin.
- 5. the forming method of semiconductor structure as claimed in claim 4, it is characterised in that the material of the body substrate is silicon, germanium Or SiGe.
- 6. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that the formation process of the fin is：Carry For Semiconductor substrate, the Semiconductor substrate is semiconductor-on-insulator substrate, and the semiconductor-on-insulator substrate includes exhausted Edge layer and the semiconductor layer positioned at surface of insulating layer, the material of the semiconductor layer is silicon or germanium；In the semiconductor layer table Face forms mask layer；It is semiconductor layer described in mask etching untill surface of insulating layer is exposed using the mask layer, is formed Fin on insulating barrier.
- 7. the forming method of semiconductor structure as described in claim 4 or 6, it is characterised in that also include：Formed fin it Afterwards, the first silicon oxide layer is formed in the sidewall surfaces of fin using thermal oxidation technology, the thickness of first silicon oxide layer is received for 1 Rice~5 nanometers.
- 8. the forming method of semiconductor structure as described in claim 4 or 6, it is characterised in that the formation process of the mask layer For multiple graphical masking process.
- 9. the forming method of semiconductor structure as claimed in claim 8, it is characterised in that when the formation process of the mask layer is During Dual graphing masking process, the formation process of the mask layer is：Sacrificial film is formed in semiconductor substrate surface；Institute The part surface for stating sacrificial film forms patterned layer；Using the patterned layer as sacrificial film described in mask etching until exposure Untill going out Semiconductor substrate, sacrifice layer is formed；In the Semiconductor substrate and sacrificial layer surface deposition mask film；It is etched back to institute Mask film is stated untill Semiconductor substrate is exposed, forms mask layer, and remove the sacrifice layer.
- 10. the forming method of semiconductor structure as described in claim 4 or 6, it is characterised in that after fin is formed, carry out Thermal anneal process, the temperature of the thermal anneal process is 900 degrees Celsius~1100 degrees Celsius.
- 11. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that the material of the mask layer is nitridation Silicon, silica or silicon oxynitride.
- 12. the forming method of semiconductor structure as claimed in claim 11, it is characterised in that when the material of the mask layer is nitrogen During SiClx, in addition to：The second silicon oxide layer is formed between the top of fin and mask layer.
- 13. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that the material of first dummy gate layer It is identical or different with the material of the second dummy gate layer.
- 14. the forming method of semiconductor structure as claimed in claim 13, it is characterised in that first dummy gate layer or second The formation process of dummy gate layer is chemical vapor deposition method or physical gas-phase deposition；First dummy gate layer or second The material of dummy gate layer is DOPOS doped polycrystalline silicon, non-impurity-doped polysilicon, amorphous silicon, SiGe or amorphous carbon.
- 15. the forming method of semiconductor structure as claimed in claim 14, it is characterised in that form second dummy gate layer Chemical vapor deposition method parameter is：Temperature is 200-800 degrees Celsius, and air pressure is the support of 1 support -100, and power is 300 watts~600 Watt, gas includes HCl and H2, HCl flow is 1sccm~1000sccm, H2Flow be 0.1slm~50slm；When the second puppet When the material of grid layer is non-impurity-doped polysilicon, the gas also includes silicon source gas SiH4Or SiH2Cl2, the silicon source gas Flow be 1sccm~1000sccm；When the material of the second dummy gate layer is SiGe, the gas also includes silicon source gas SiH4Or SiH2Cl2With ge source gas GeH4, the flow of the silicon source gas is 1sccm~1000sccm, the ge source gas Flow is 1sccm-1000sccm.
- 16. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that the formation process of the dummy grid is： Pseudo- grid mask is formed on the second dummy gate layer surface, the pseudo- grid mask defines the figure of dummy grid, the pseudo- grid mask Material is silicon nitride or silicon oxynitride；With the pseudo- dummy gate layer of grid mask etching second and the first dummy gate layer until exposing At the top of fin and untill sidewall surfaces.
- 17. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that before the first dummy gate layer is formed, The 3rd silicon oxide layer is deposited in the side wall and top surface of the substrate surface and fin.
- 18. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that also include：Formed dummy grid it Afterwards, source region and drain region are formed in the fin of the dummy grid both sides；After the source region and drain region is formed, in the substrate The side wall and top surface of surface and fin form second dielectric layer, the surface of the second dielectric layer and the top table of dummy grid Face flushes；After second dielectric layer is formed, remove the dummy grid and opening is formed in second dielectric layer；In the opening Interior formation gate dielectric layer, the gate electrode layer of the full opening of filling is formed on the gate dielectric layer surface.
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