CN104124168A - Method for forming semiconductor structure - Google Patents
Method for forming semiconductor structure Download PDFInfo
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- CN104124168A CN104124168A CN201310156943.9A CN201310156943A CN104124168A CN 104124168 A CN104124168 A CN 104124168A CN 201310156943 A CN201310156943 A CN 201310156943A CN 104124168 A CN104124168 A CN 104124168A
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 46
- 239000000463 material Substances 0.000 claims description 38
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 36
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 28
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- 229910052732 germanium Inorganic materials 0.000 claims description 12
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 12
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
A method for forming a semiconductor structure comprises the steps of providing a substrate with the surface provided with a fin part; forming a first pseudo gate layer on the substrate and the surface of the pin part, enabling the surface of the first pseudo gate layer to be higher than the top surface of the fin part; flattening the first pseudo gate layer until the top surface of the fin part is exposed; after a flattening process, forming a second pseudo gate layer on the first pseudo gate layer and the surface of the fin part; etching part of the first pseudo gate layer and the second pseudo gate layer until the top and the side wall surface of the fin part are exposed, and forming a pseudo gate striding over a side wall and the top surface of the fin part. In the formed semiconductor structure, uniformity and accuracy of the thickness of the gate structure on the top surface of the fin part are improved.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, relate in particular to a kind of formation method of semiconductor structure.
Background technology
Along with the develop rapidly of semiconductor fabrication, semiconductor device is towards higher component density, and the future development of higher integrated level.Transistor is just being widely used at present as the most basic semiconductor device, therefore along with the raising of component density and the integrated level of semiconductor device, the grid size of planar transistor is also shorter and shorter, traditional planar transistor dies down to the control ability of channel current, produce short-channel effect, produce leakage current, finally affect the electric property of semiconductor device.
In order to overcome transistorized short-channel effect, suppress leakage current, prior art has proposed fin formula field effect transistor (Fin FET), fin formula field effect transistor is a kind of common multiple-grid device, please refer to Fig. 1, Fig. 1 is the perspective view of the fin field effect pipe of prior art, comprising: Semiconductor substrate 10; Be positioned at the fin 14 protruding in described Semiconductor substrate 10; The dielectric layer 11 that covers a part for described Semiconductor substrate 10 surfaces and fin 14 sidewalls, the surface of described dielectric layer 11 is lower than the top of described fin 14; Across the top of described fin 14 and the grid structure of sidewall 12, described grid structure 12 comprises gate dielectric layer (not shown) and is positioned at the gate electrode (not shown) on described gate dielectric layer.It should be noted that, for fin field effect pipe, the top of fin 14 and the sidewall of both sides become channel region with the part that grid structure 12 contacts, and have a plurality of grid, are conducive to increase drive current, improve device performance.
In prior art, in order further to improve the performance of fin formula field effect transistor, described gate dielectric layer adopts high K dielectric material, described gate electrode layer adopts metal, be that fin formula field effect transistor forms high-K metal gate (High-k Metal Gate, HKMG) transistor, the fin formula field effect transistor of described high-K metal gate structure can adopt rear grid (Gate Last) technique to form.
Yet, in prior art, grid technique forms while having the fin field effect pipe of high-K metal gate structure later, be positioned at the uneven thickness one of the grid structure of the some fin top surfaces in same semi-conductive substrate, and the gauge of grid structure is difficult to control, make the electrical property of formed some fin formula field effect transistors inconsistent, cause the performance of formed semiconductor device to be difficult to control.
Summary of the invention
The problem that the present invention solves is to provide a kind of formation method of semiconductor structure, homogeneity and the accuracy of the gauge of the grid structure of raising fin top surface.
For addressing the above problem, the invention provides a kind of formation method of semiconductor structure, comprising: substrate is provided, and described substrate surface has fin; In described substrate and fin surface, form the first dummy gate layer, the surface of described the first dummy gate layer is higher than the top surface of described fin; The first dummy gate layer described in planarization is until expose the top surface of fin; After described flatening process, in described the first dummy gate layer and fin surface, form the second dummy gate layer; Etched portions the first dummy gate layer and the second dummy gate layer until expose fin top and sidewall surfaces, form across the sidewall of described fin and the dummy grid of top surface.
Optionally, also comprise: be positioned at the mask layer of fin top surface, described the first dummy gate layer is also deposited on described mask layer surface, and described the first dummy gate layer surface is equal to or higher than described mask layer surface.
Optionally, described in planarization, the technique of the first dummy gate layer is: described in the planarization of employing CMP (Chemical Mechanical Polishing) process, the first dummy gate layer is until expose the top surface of mask layer; After planarization the first dummy gate layer, return described in etching the first dummy gate layer until the surface of described the first dummy gate layer and fin flush; After described time etching technics, remove described mask layer.
Optionally, described time etching technics is anisotropic dry etch process, and technological parameter is: substrate bias power is less than 100W, and etching gas comprises CF
4, SF
6or NF
3.
Optionally, the etching depth of described time etching technics is controlled by advanced process control device.
Optionally, the formation technique of described fin is: Semiconductor substrate is provided, and described Semiconductor substrate is body substrate; At described body substrate surface, form mask layer; Take described mask layer as body substrate described in mask etching and form opening, the body substrate between adjacent apertures forms fin; First medium layer, the sidewall surfaces of described first medium layer cover part fin are formed on the bottom at described opening.
Optionally, the material of described body substrate is silicon, germanium or SiGe.
Optionally, the formation technique of described fin is: Semiconductor substrate is provided, described Semiconductor substrate is semiconductor-on-insulator substrate, the semiconductor layer that described semiconductor-on-insulator substrate comprises insulating barrier and is positioned at surface of insulating layer, and the material of described semiconductor layer is silicon or germanium; In described semiconductor layer surface, form mask layer; Take described mask layer as semiconductor layer described in mask etching until expose surface of insulating layer, form and be positioned at the fin on insulating barrier.
Optionally, also comprise: after forming fin, adopt thermal oxidation technology to form the first silicon oxide layer in the sidewall surfaces of fin, the thickness of described the first silicon oxide layer is 1 nanometer～5 nanometer.
Optionally, the formation technique of described mask layer is multiple graphics masking process.
Optionally, when the formation technique of described mask layer is Dual graphing masking process, the formation technique of described mask layer is: at semiconductor substrate surface, form sacrificial film; Part surface in described sacrificial film forms patterned layer; Take described patterned layer as sacrificial film described in mask etching until expose Semiconductor substrate, form sacrifice layer; At described Semiconductor substrate and sacrificial layer surface deposition mask film; Return mask film described in etching until expose Semiconductor substrate, form mask layer, and remove described sacrifice layer.
Optionally, after forming fin, carry out thermal anneal process, the temperature of described thermal anneal process is 900 degrees Celsius～1100 degrees Celsius.
Optionally, the material of described mask layer is silicon nitride, silica or silicon oxynitride.
Optionally, when the material of described mask layer is silicon nitride, also comprise: between the top of fin and mask layer, form the second silicon oxide layer.
Optionally, the material of the material of described the first dummy gate layer and the second dummy gate layer is identical or different.
Optionally, the formation technique of described the first dummy gate layer or the second dummy gate layer is chemical vapor deposition method or physical gas-phase deposition; The material of described the first dummy gate layer or the second dummy gate layer is doped polycrystalline silicon, non-impurity-doped polysilicon, amorphous silicon, SiGe or amorphous carbon.
Optionally, the chemical vapor deposition method parameter that forms described the second dummy gate layer is: temperature is 200-800 degree Celsius, and air pressure is 1 holder-100 holder, and power is 300 watts～600 watts, and gas comprises HCl and H
2, the flow of HCl is 1sccm～1000sccm, H
2flow be 0.1slm～50slm; When the material of the second dummy gate layer is non-impurity-doped polysilicon, described gas also comprises silicon source gas SiH
4or SiH
2cl
2, the flow of described silicon source gas is 1sccm～1000sccm; When the material of the second dummy gate layer is SiGe, described gas also comprises silicon source gas SiH
4or SiH
2cl
2with germanium source gas GeH
4, the flow of described silicon source gas is 1sccm～1000sccm, the flow of described germanium source gas is 1sccm-1000sccm.
Optionally, the formation technique of described dummy grid is: on the second dummy gate layer surface, form pseudo-grid mask, described pseudo-grid mask has defined the figure of dummy grid, and the material of described pseudo-grid mask is silicon nitride or silicon oxynitride; With described pseudo-grid mask etching the second dummy gate layer and the first dummy gate layer until expose fin top and sidewall surfaces.
Optionally, before forming the first dummy gate layer, at sidewall and top surface deposition the 3rd silicon oxide layer of described substrate surface and fin.
Optionally, also comprise: after forming dummy grid, in the fin of described dummy grid both sides, form source region and drain region; After forming described source region and drain region, at sidewall and the top surface formation second medium layer of described substrate surface and fin, the surface of described second medium layer flushes with the top surface of dummy grid; After forming second medium layer, at the described dummy grid of described removal and form opening in second medium layer; In described opening, form gate dielectric layer, on described gate dielectric layer surface, form the gate electrode layer of filling full described opening.
Compared with prior art, technical scheme of the present invention has the following advantages:
After substrate and fin surface deposition the first dummy gate layer, the first dummy gate layer described in planarization is until expose the top of fin, in described the first dummy gate layer and fin surface, form the second dummy gate layer again, the thickness of described the second dummy gate layer can accurately be controlled by technique, and can make to be positioned at the even thickness of the second dummy gate layer of diverse location in substrate.Follow-uply by the second dummy gate layer described in etching and the first dummy gate layer, form across the sidewall of fin and the dummy grid of top surface, the gauge of dummy grid that can make to be formed at fin top surface is accurate, and the dummy grid gauge homogeneous at different fins top, has improved the stability of formed semiconductor device.
Further, the top surface of described fin also has mask layer, and described mask layer for defining the figure of fin, and forms fin with mask layer etching in preorder technique, and described the first dummy gate layer is also deposited on described mask layer surface.The technique of described planarization the first dummy gate layer is: adopt the first dummy gate layer described in CMP (Chemical Mechanical Polishing) process polishing until expose mask layer, described mask layer is for as polishing stop layer, and protects fin top injury-free.Adopt back afterwards etching technics to make surface and the fin flush of the first dummy gate layer; Described time etching technics can accurately be controlled etching depth by adjusting etch rate and etch period, thereby can make surface and the fin flush of the first dummy gate layer.
Further, the etching depth of described time etching technics is controlled (APC, Advanced Process Control) device by advanced process and is controlled; Described advanced process control device can detect the first dummy gate layer surface that is positioned at substrate diverse location, obtains the polishing surface height state of the first dummy gate layer afterwards; The surface state of the first measured dummy gate layer, in conjunction with the parameter of returning etching technics, for example etch rate and etch period, can access the degree of depth of the required time etching of the first dummy gate layer of substrate diverse location; The surface uniform that has guaranteed time etching the first dummy gate layer afterwards, makes follow-up the second dummy gate layer surface uniform that is formed at the first dummy gate layer surface then.
Further, when the material of described the first dummy gate layer and the second dummy gate layer is different, when etching the second dummy gate layer is after exposing the first dummy gate layer, need to change etching gas to continue etching the first dummy gate layer until expose substrate, and described in etching the first dummy gate layer gas not easy damaged completed the second dummy gate layer of etching, thereby guaranteed across the pattern of the dummy grid of fin well, be conducive to formed device performance stable.
Accompanying drawing explanation
Fig. 1 is the perspective view that prior art forms fin field effect pipe;
Fig. 2 to Fig. 4 is the cross-sectional view that prior art forms the process of fin field effect pipe;
Fig. 5 to Figure 12 is the cross-sectional view of forming process of the semiconductor structure of embodiments of the invention.
Embodiment
As stated in the Background Art, the gauge heterogeneity of the grid structure of the fin top surface of prior art and size inaccuracy.
In one embodiment, the forming process that forms high-K metal gate structure on fin surface as shown in Figures 2 to 4.
Please refer to Fig. 2, Semiconductor substrate 10 is provided, is positioned at the fin 14 protruding in described Semiconductor substrate 10 and covers described Semiconductor substrate 10 surfaces and the dielectric layer 11 of fin 14 partial sidewall, in sidewall and the top surface deposition dummy gate layer 15 of dielectric layer 11 surfaces and fin 14, described dummy gate layer 15 is filled the opening (not shown) between the adjacent fin 14 of full phase.
Please refer to Fig. 3, adopt CMP (Chemical Mechanical Polishing) process planarization dummy gate layer 15.
Please refer to Fig. 4, Fig. 4 is the section along CC ' direction based on Fig. 3, and etched portions dummy gate layer 15 until expose fin 14 tops and the surface of sidewall surfaces and dielectric layer 11, forms across the sidewall of described fin 14 and the dummy grid 15a of top surface.
After forming dummy grid 15a, fin 14 interior formation source region and drain region in described dummy grid 15a both sides, and at sidewall and top surface and the dummy grid 15a surface deposition insulating barrier of described dielectric layer 11 surfaces, fin 14; Insulating barrier described in chemico-mechanical polishing is until expose dummy grid 15a top surface; Afterwards, remove described dummy grid 15a and in the position of former dummy grid 15a, form the gate electrode layer on gate dielectric layer and gate dielectric layer surface.
After depositing insulating layer, need to adopt insulating barrier described in CMP (Chemical Mechanical Polishing) process planarization until expose dummy grid, make described insulating barrier can copy the shape of described dummy grid completely, and facilitate the described dummy grid of follow-up removal.In order to expose the top surface of described dummy grid completely after insulating barrier described in polishing, need to make the top surface of described dummy grid smooth, therefore need to be after deposition dummy gate layer, first to dummy gate layer planarization, then described in etching dummy gate layer to form dummy grid.Yet, while adopting described in CMP (Chemical Mechanical Polishing) process planarization dummy gate layer, be difficult to control the gauge of the remaining dummy gate layer in fin top after polishing; And after polishing, the dummy gate layer that is positioned at same semi-conductive substrate diverse location exists difference in height, cause the gauge homogeneity of the formed dummy gate layer of fin top surface of same semi-conductive substrate diverse location poor.Therefore, bad with the formed fin field effect pipe characteristic size homogeneity with high-K metal gate structure of prior art and accuracy is poor.
Through the present inventor, further study, prior art is improved, after substrate and fin surface deposition the first dummy gate layer, the first dummy gate layer described in planarization is until expose the top surface of fin, in described the first dummy gate layer and fin surface, form the second dummy gate layer again, the thickness of described the second dummy gate layer can accurately be controlled by technique, and can make to be positioned at the even thickness of the second dummy gate layer of diverse location in substrate.Follow-uply by the second dummy gate layer described in etching and the first dummy gate layer, form across the sidewall of fin and the dummy grid of top surface, the gauge of dummy grid that can make to be formed at fin top surface is accurate, and the dummy grid gauge homogeneous at different fins top, has improved the stability of formed semiconductor device.
For above-mentioned purpose of the present invention, feature and advantage can more be become apparent, below in conjunction with accompanying drawing, specific embodiments of the invention are described in detail.
Fig. 5 to Figure 12 is the cross-sectional view of forming process of the semiconductor structure of embodiments of the invention.
Please refer to Fig. 5, substrate 200 is provided, described substrate 200 surfaces have fin 201, and the top surface of described fin 201 has mask layer 202.
In the present embodiment, the part that described substrate 200 and fin 201 are provided Semiconductor substrate, wherein, described substrate 200 provides the platform of subsequent technique, and described fin 201 is formed by Semiconductor substrate described in etching; Described Semiconductor substrate comprises body substrate or semiconductor-on-insulator substrate; The material of described body substrate comprises silicon, germanium and SiGe; The semiconductor layer that described semiconductor-on-insulator substrate comprises substrate, is positioned at the insulating barrier of substrate surface and is positioned at surface of insulating layer, the material of described semiconductor layer comprises silicon or germanium.
When described Semiconductor substrate is body substrate, the formation technique of described fin 201 is: at described body substrate surface, form mask layer 202; Take described mask layer 202 as body substrate described in mask etching and form opening, the body substrate between adjacent apertures forms fin 201, and the remaining body substrate that is positioned at fin 201 bottoms forms substrate 200.In the present embodiment, described fin 201 is formed by etching body substrate, and is positioned at the remaining body substrate formation substrate 200 of fin 201 bottoms.
It should be noted that, when described Semiconductor substrate is body substrate, and fin 201 is when formed by etching body substrate, after etching forms fin 201, at described substrate 200 and fin 201 surface deposition first medium films; Return described in etching first medium film until expose top and the partial sidewall surface of fin 201, first medium layer 203 is formed on the bottom at described opening, and the surface of described first medium layer 203 is lower than the sidewall surfaces of fin 201 top surfaces and cover part fin 201.
When described Semiconductor substrate is semiconductor-on-insulator substrate, the formation technique of described fin is: in semiconductor layer surface, form mask layer 202; Take described mask layer 202 as semiconductor layer described in mask etching until expose surface of insulating layer, form and be positioned at the fin on insulating barrier.Wherein, the insulating barrier in semiconductor-on-insulator substrate is as the dielectric layer of isolation fin, and substrate in semiconductor-on-insulator substrate is as substrate.
In other embodiments, provided semiconductor substrate surface can also be provided described fin, formation technique is: at semiconductor substrate surface, form the dielectric layer with opening, described opening has defined figure and the position of fin, and exposes semiconductor substrate surface; In described opening, adopt epitaxial deposition process to form fin, and dielectric layer described in time etching, make dielectric layer surface lower than fin surface.
In addition, after forming fin 201, carry out thermal anneal process, to eliminate the defect in fin 201, make the channel region of formed fin field effect pipe functional; The temperature of described thermal anneal process is 900 degrees Celsius～1100 degrees Celsius, and anneal gas is hydrogen or helium.
Described mask layer 202 is the mask when forming fin 201 as Semiconductor substrate described in etching, and when described mask layer 202 can also and return etching the first dummy gate layer in follow-up polishing, damage is avoided at the top of protection fin 201.The material of described mask layer 202 is silicon nitride, silica or silicon oxynitride; When the material of described mask layer 202 is silicon nitride, in order to strengthen the binding ability of silicon nitride and semiconductor substrate surface, also can between semiconductor substrate surface and mask layer 202, form the second silicon oxide layer 210, as Semiconductor substrate, to the transition between mask layer 202, between formed fin 201 and mask layer 202, there is the second silicon oxide layer 210; The formation technique of described the second silicon oxide layer 210 is thermal oxidation technology or depositing operation, and the thickness of described the second silicon oxide layer 210 is 1 nanometer～5 nanometer.In the present embodiment, the top surface of described fin 201 is formed with the second silicon oxide layer 210, and 210 layers of surface of described the second silicon oxide layer are formed with take the mask layer 202 that silicon nitride is material.
It should be noted that, the quantity of described fin 201 is single or multiple, and the fin 201 of 3 adjacent settings has been shown in the present embodiment; In order to make formed fin 201 sizes little, and the size between adjacent fin 201 is little, the formation technique of described mask layer 202 is multiple graphics masking process, autoregistration Dual graphing (Self-aligned Double Patterned for example, SaDP) technique, triple graphical (the Self-aligned Triple Patterned) technique of autoregistration or graphical (Self-aligned Double Double Patterned, the SaDDP) technique of autoregistration quadruple.
In the present embodiment, the formation technique of described mask layer 202 is Dual graphing masking process, forms technique to be: at semiconductor substrate surface, form sacrificial film; Part surface in described sacrificial film forms patterned layer, and described patterned layer can adopt photoetching process, nano print technique or directed self-assembly process to form; In the present embodiment, adopt photoetching process to form described patterned layer, the material of patterned layer is photoresist; Take described patterned layer as sacrificial film described in mask etching until expose Semiconductor substrate, form sacrifice layer; At described Semiconductor substrate and sacrificial layer surface deposition mask film; Return mask film described in etching until expose Semiconductor substrate, form mask layer, and remove sacrifice layer.
In addition; after forming fin 201; adopt thermal oxidation technology to form the first silicon oxide layer 211 in the sidewall surfaces of fin 201; the thickness of described the first silicon oxide layer 211 is 1 nanometer～5 nanometer; described the first silicon oxide layer 211 can be in subsequent etching the first dummy gate layer and the second dummy gate layer when forming dummy grid, and the sidewall surfaces of protection fin 201 is avoided damage.
Please refer to Fig. 6, at described first medium layer 203, fin 201 and mask layer 202 surfaces, form the first dummy gate layer 204, the surface of described the first dummy gate layer 204 is equal to or higher than the top surface of described mask layer 202.
The second dummy gate layer of described the first dummy gate layer 204 and follow-up formation is used to form dummy grid jointly, and the high-K metal gate structure that described dummy grid is required formation takes up space; The formation technique of described the first dummy gate layer 204 is depositing operation, comprises chemical vapor deposition method or physical gas-phase deposition, and the material of described the first dummy gate layer 204 is doped polycrystalline silicon, non-impurity-doped polysilicon, amorphous silicon, SiGe or amorphous carbon; In addition; before forming the first dummy gate layer 204; sidewall and top surface deposition the 3rd silicon oxide layer (not shown) at described substrate 200 surfaces and fin 201; described the 3rd silicon oxide layer can be further in subsequent technique; for example, when etching forms dummy gate layer, the sidewall surfaces of protection fin 201 is avoided damage.
In subsequent technique, in order to guarantee to be formed at the accurate homogeneous of dummy grid thickness at fin 201 tops, need to be polished to mask layer 202 surfaces to described the first dummy gate layer 204, and return and to be etched to fin 201 top surfaces, so that follow-up in described the first dummy gate layer 204 and accurate the second dummy gate layer of fin 201 surface deposition even thickness, therefore need the first dummy gate layer 204 surfaces that deposition forms all higher than fin 201 tops and be equal to or higher than the top surface of mask layer 202; And described fin 201 protrudes from first medium layer 203 surface, easily make formed the first dummy gate layer 204 surfaces there is height difference, in order to guarantee that the first dummy gate layer 204 surfaces after glossing are not less than the top surface of fin 201, need to guarantee that the lowest part on described the first dummy gate layer 204 surfaces is not less than the top of mask layer 202.
Please refer to Fig. 7, the first dummy gate layer 204 is until expose the top surface of mask layer 202 described in planarization.
Described flatening process is CMP (Chemical Mechanical Polishing) process; in described CMP (Chemical Mechanical Polishing) process; described mask layer 202 has defined the stop position of described glossing, and due to the protection of described mask layer 202, the top of described fin 201 can not sustain damage in described glossing.
Yet because described glossing stops at mask layer 202, so the first dummy gate layer 204 surfaces after polishing are still higher than fin 201 tops; And, described CMP (Chemical Mechanical Polishing) process differs for the polishing uniformity that is positioned at the first dummy gate layer 204 of substrate 200 surperficial diverse locations, and the first dummy gate layer 204 that easily causes substrate 200 surperficial diverse locations is through after glossing, it is highly inconsistent; If form dummy grid with described the first dummy gate layer 204 etchings through polishing, can cause the characteristic size of formed fin field effect pipe inconsistent, formed device stability variation.
Therefore, after described CMP (Chemical Mechanical Polishing) process, need to adopt back etching technics to make surface and fin 201 flush of the first dummy gate layer 204, again in the second dummy gate layer of fin 201 and the first dummy gate layer 204 surface formation even thickness, the dummy grid size uniform that can make etching form, dummy grid surface is accurate to the distance at fin 201 tops.
Please refer to Fig. 8, after planarization the first dummy gate layer 204, return described in etching the first dummy gate layer 204 until the surface of described the first dummy gate layer 204 and fin 201 flush.
Described time etching technics is anisotropic dry etch process, and technological parameter is: substrate bias power is less than 100W, and etching gas comprises CF
4, SF
6or NF
3; Described anisotropic dry etch process is controlled etching depth by controlling etch period, and the etching depth of described time etching technics can also be controlled by advanced process (APC, Advanced Process Control) device and accurately controls.
Described advanced process control device comprises checkout gear, arithmetic unit and control device; Wherein, described checkout gear is for detection of the surface state through the first dummy gate layer 204 after polishing on whole substrate 200 surfaces; Specifically the height difference for the first dummy gate layer 204 surfaces detects, to determine the height distribution that is positioned at the first dummy gate layer 204 in whole substrate 200; By the height distribution of the first dummy gate layer 204 of described integral body and the parameters of described anisotropic dry etch process input arithmetic unit, to obtain the degree of depth for the required etching of diverse location of whole the first dummy gate layer 204, to guarantee back that the surface of the first dummy gate layer 204 after etching all can flush with the top surface of fin 201; The etching depth data of the first dummy gate layer 204 diverse locations that control device obtains according to arithmetic unit are carried out the described etching technics that returns, and the top surface of the first dummy gate layer 204 after etching all can flush with the top surface of fin 201.Adopt described advanced process control device to control the described surface uniform that etching technics can guarantee back the first dummy gate layer 204 after etching that returns, make follow-up same the maintenance evenly of the second dummy gate layer surface that is formed at the even thickness on the first dummy gate layer surface, the thickness homogeneous of the dummy grid of the follow-up fin top surface that is formed at substrate 200 diverse locations, has guaranteed that formed device performance is stable.
It should be noted that, in the present embodiment, be also formed with the second silicon oxide layer 210 between described fin 201 and mask layer 203, the thickness of described the second silicon oxide layer 210 is 1 nanometer～5 nanometer; The present embodiment returns the surface of the first dummy gate layer 204 after etching and the flush of described the second silicon oxide layer 210, due to the thickness of described the second silicon oxide layer 210 as thin as a wafer, can make the surface of the first dummy gate layer 204 flush with the top surface of fin 201.Described the second silicon oxide layer 210 can also protect the top surface of fin 201 to reduce damage when subsequent etching forms dummy grid.
Please refer to Fig. 9, after described time etching technics, remove described mask layer 202(as shown in Figure 8) and expose the second silicon oxide layer 210 of the top surface of fin 201.
The technique of described removal mask layer 202 is etching technics, comprises dry etching and wet etching; The material of described mask layer 202 is silicon nitride, silica or silicon oxynitride, when adopting wet etching to remove mask layer 202, the etching liquid of described wet etching comprises: phosphoric acid (etch silicon nitride) and/or hydrofluoric acid (etching oxidation silicon), when adopting dry etching to remove mask layer 202, etching gas comprises CHF
3(etching oxidation silicon) and/or CF
4(etch silicon nitride), described dry etching can be anisotropy or isotropism; By adjusting the ratio of etching liquid of wet etching or the ratio of the etching gas of dry etching, control the selection ratio of etching technics, to remove silicon nitride, silica or silicon oxynitride.
In the present embodiment; the top of described fin is formed with the second silicon oxide layer 210; described mask layer 202 is formed at the second silicon oxide layer 210 surfaces; adopt wet-etching technology to remove described mask layer 202 and retain described the second silicon oxide layer 210; described wet-etching technology is less to the damage of the second silicon oxide layer 210; and remove mask layer 202 fast thoroughly, described the second silicon oxide layer 210 can also be protected the top surface of fin 201 when subsequent etching forms dummy grid.
And, in the present embodiment, return etching the first dummy gate layer 204 and described the second silicon oxide layer 210 flush, after removing described mask layer, described the first dummy gate layer 204 is smooth with the integral surface of second silicon oxide layer 210 formation on fin 201 surfaces, follow-up on described the first dummy gate layer 204 and fin 201 after uniform the second dummy gate layer of deposit thickness, the surfacing of described the second dummy gate layer, is conducive to make to be formed at the accurate homogeneous of dummy grid thickness of fin 201 top surfaces.
Please refer to Figure 10 and Figure 11, Figure 11 is that Figure 10 is along the cross-sectional view of BB ' direction, at the described mask layer 202(of removal as shown in Figure 8) afterwards, in described the first dummy gate layer 204 and fin 201 surfaces, form the second dummy gate layer 205.
The material of described the second dummy gate layer 205 is doped polycrystalline silicon, non-impurity-doped polysilicon, amorphous silicon, SiGe or amorphous carbon, the material of the material of described the first dummy gate layer 204 and the second dummy gate layer 205 is identical or different, especially, when the material of described the first dummy gate layer 204 and the second dummy gate layer 205 is different, more be conducive to make the pattern of the dummy grid that subsequent etching forms good: concrete, when subsequent etching the second dummy gate layer 205 is after exposing the first dummy gate layer 204, need to change etching gas, to continue etching the first dummy gate layer 204 until expose first medium layer 203, when the material of described the first dummy gate layer 204 and the second dummy gate layer 205 is different, the gas of the second dummy gate layer 205 easy damaged the second dummy gate layer 205 of etching not described in etching, thereby guaranteed to be positioned at the pattern of the dummy grid of fin 201 top surfaces, be conducive to formed device performance stable.
The formation technique of described the second dummy gate layer 205 is chemical vapor deposition method or physical gas-phase deposition, preferably chemical vapor deposition method; The chemical vapor deposition method parameter that forms described the second dummy gate layer 205 comprises: temperature is 200-800 degree Celsius, and air pressure is 1 holder-100 holder, and power is 300 watts～600 watts, and gas comprises HCl and H
2, the flow of HCl is 1sccm～1000sccm, H
2flow be 0.1slm～50slm; When the material of the second dummy gate layer is non-impurity-doped polysilicon, described gas also comprises silicon source gas SiH
4or SiH
2cl
2, the flow of described silicon source gas is 1sccm～1000sccm; When the material of the second dummy gate layer is SiGe, described gas also comprises silicon source gas SiH
4or SiH
2cl
2with germanium source gas GeH
4, the flow of described silicon source gas is 1sccm～1000sccm, the flow of described germanium source gas is 1sccm-1000sccm.The deposition rate of described chemical vapor deposition method is controlled, therefore can accurately control by controlling sedimentation time the thickness of formed the second dummy gate layer 205.In addition, can be in the process of described chemical vapor deposition method, by in-situ doped technique adulterate in polycrystalline silicon material P type ion or N-type ion.
Adopt the even thickness of the second dummy gate layer 205 of described depositing operation formation, and be positioned at, process in whole substrate 200 is returned the first dummy gate layer 204 of etching and the flush of the second silicon oxide layer 210 is even, therefore the surfacing of described the second dummy gate layer 205 is even, after the dummy grid that described in subsequent etching, the second dummy gate layer 205 and the first dummy gate layer 204 form, the dummy grid even thickness that is positioned at fin 201 top surfaces is accurate.
On the basis of Figure 11, please refer to Figure 12, etched portions the first dummy gate layer 204 and the second dummy gate layer 205 until expose fin 204 tops and sidewall surfaces, form across the sidewall of described fin 201 and the dummy grid (not shown) of top surface.
The formation technique of described dummy grid is: on the second dummy gate layer 205 surfaces, form pseudo-grid mask 212, described pseudo-grid mask 212 has defined the figure of dummy grid; With described pseudo-grid mask 212 etching the second dummy gate layer 205 and the first dummy gate layer 204(as shown in figure 10) until expose fin 201 tops and sidewall surfaces and first medium layer 203, form across the sidewall of described fin 201 and the dummy grid on top surface and first medium layer 203 surface.Wherein, the material of described pseudo-grid mask 212 is silicon nitride or silicon oxynitride.
The first dummy gate layer 204 is through CMP (Chemical Mechanical Polishing) process and return etching technics, and its surface flushes with the second silicon oxide layer 210, and the first dummy gate layer 204 and the second silicon oxide layer 210 that are positioned in whole substrate 200 have an even surface; The thickness of the second dummy gate layer 205 can accurately be controlled and evenly by depositing operation, is positioned at the first dummy gate layer 204 of whole substrate 200 and second dummy gate layer 205 surfaces on the second silicon oxide layer 210 surfaces also can keep smooth; The top surface of the dummy grid forming with the second dummy gate layer 205 and the first dummy gate layer 204 etchings is even, and accurately easily controls higher than the size at fin 201 tops.
It should be noted that, after forming dummy grid, fin 204 interior formation source region and drain region (not shown) in described dummy grid both sides; After forming described source region and drain region, at sidewall and the top surface formation second medium layer (not shown) of described first medium layer 203 surface and fin 201, the surface of described second medium layer flushes with the top surface of dummy grid; After forming second medium layer, then remove described dummy grid and in second medium layer, form opening (not shown); In described opening, form gate dielectric layer (not shown), on described gate dielectric layer surface, form the gate electrode layer (not shown) of filling full described opening.
In the present embodiment, at first medium layer 203, fin 201 and mask layer 202 surfaces form the first dummy gate layer 204, described in the polishing of employing CMP (Chemical Mechanical Polishing) process, the first dummy gate layer 204 is to exposing mask layer 202, return again etching the first dummy gate layer 204 to flushing with fin 201 top surfaces, remove afterwards mask layer 202 and in fin 201 and accurate the second dummy gate layer 205 of the first dummy gate layer 204 surface deposition even thickness, the surface uniform of described the second dummy gate layer 205 is smooth, and the accurate homogeneous of thickness higher than fin 201 tops, the dummy grid forming with the second dummy gate layer 205 and the first dummy gate layer 204 etchings is higher than the accurate homogeneous of gauge of fin 201, be conducive to make formed device performance stable.
In sum, after substrate and fin surface deposition the first dummy gate layer, the first dummy gate layer described in planarization is until expose the top of fin, in described the first dummy gate layer and fin surface, form the second dummy gate layer again, the thickness of described the second dummy gate layer can accurately be controlled by technique, and can make to be positioned at the even thickness of the second dummy gate layer of diverse location in substrate.Follow-uply by the second dummy gate layer described in etching and the first dummy gate layer, form across the sidewall of fin and the dummy grid of top surface, the gauge of dummy grid that can make to be formed at fin top surface is accurate, and the dummy grid gauge homogeneous at different fins top, has improved the stability of formed semiconductor device.
Further, the top surface of described fin also has mask layer, and described mask layer for defining the figure of fin, and forms fin with mask layer etching in preorder technique, and described the first dummy gate layer is also deposited on described mask layer surface.The technique of described planarization the first dummy gate layer is: adopt the first dummy gate layer described in CMP (Chemical Mechanical Polishing) process polishing until expose mask layer, described mask layer is for as polishing stop layer, and protects fin top injury-free.Adopt back afterwards etching technics to make surface and the fin flush of the first dummy gate layer; Described time etching technics can accurately be controlled etching depth by adjusting etch rate and etch period, thereby can make surface and the fin flush of the first dummy gate layer.
Further, the etching depth of described time etching technics is controlled by advanced process control device; Described advanced process control device can detect the first dummy gate layer surface that is positioned at substrate diverse location, obtains the polishing surface height state of the first dummy gate layer afterwards; The surface state of the first measured dummy gate layer, in conjunction with the parameter of returning etching technics, for example etch rate and etch period, can access the degree of depth of the required time etching of the first dummy gate layer of substrate diverse location; The surface uniform that has guaranteed time etching the first dummy gate layer afterwards, makes follow-up the second dummy gate layer surface uniform that is formed at the first dummy gate layer surface then.
Further, when the material of described the first dummy gate layer and the second dummy gate layer is different, when etching the second dummy gate layer is after exposing the first dummy gate layer, need to change etching gas to continue etching the first dummy gate layer until expose substrate, and described in etching the first dummy gate layer gas not easy damaged completed the second dummy gate layer of etching, thereby guaranteed across the pattern of the dummy grid of fin well, be conducive to formed device performance stable.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, so protection scope of the present invention should be as the criterion with claim limited range.
Claims (20)
1. a formation method for semiconductor structure, is characterized in that, comprising:
Substrate is provided, and described substrate surface has fin;
In described substrate and fin surface, form the first dummy gate layer, the surface of described the first dummy gate layer is higher than the top surface of described fin;
The first dummy gate layer described in planarization is until expose the top surface of fin;
After described flatening process, in described the first dummy gate layer and fin surface, form the second dummy gate layer;
Etched portions the first dummy gate layer and the second dummy gate layer until expose fin top and sidewall surfaces, form across the sidewall of described fin and the dummy grid of top surface.
2. the formation method of semiconductor structure as claimed in claim 1, it is characterized in that, also comprise: be positioned at the mask layer of fin top surface, described the first dummy gate layer is also deposited on described mask layer surface, and described the first dummy gate layer surface is equal to or higher than described mask layer surface.
3. the formation method of semiconductor structure as claimed in claim 2, is characterized in that, the technique of the first dummy gate layer is described in planarization: adopt described in CMP (Chemical Mechanical Polishing) process planarization the first dummy gate layer until expose the top surface of mask layer; After planarization the first dummy gate layer, return described in etching the first dummy gate layer until the surface of described the first dummy gate layer and fin flush; After described time etching technics, remove described mask layer.
4. the formation method of semiconductor structure as claimed in claim 3, is characterized in that, described time etching technics is anisotropic dry etch process, and technological parameter is: substrate bias power is less than 100W, and etching gas comprises CF
4, SF
6or NF
3.
5. the formation method of semiconductor structure as claimed in claim 3, is characterized in that, the etching depth of described time etching technics is controlled by advanced process control device.
6. the formation method of semiconductor structure as claimed in claim 2, is characterized in that, the formation technique of described fin is: Semiconductor substrate is provided, and described Semiconductor substrate is body substrate; At described body substrate surface, form mask layer; Take described mask layer as body substrate described in mask etching and form opening, the body substrate between adjacent apertures forms fin; First medium layer, the sidewall surfaces of described first medium layer cover part fin are formed on the bottom at described opening.
7. the formation method of semiconductor structure as claimed in claim 6, is characterized in that, the material of described body substrate is silicon, germanium or SiGe.
8. the formation method of semiconductor structure as claimed in claim 2, it is characterized in that, the formation technique of described fin is: Semiconductor substrate is provided, described Semiconductor substrate is semiconductor-on-insulator substrate, the semiconductor layer that described semiconductor-on-insulator substrate comprises insulating barrier and is positioned at surface of insulating layer, the material of described semiconductor layer is silicon or germanium; In described semiconductor layer surface, form mask layer; Take described mask layer as semiconductor layer described in mask etching until expose surface of insulating layer, form and be positioned at the fin on insulating barrier.
9. the formation method of semiconductor structure as described in claim 6 or 8, it is characterized in that, also comprise: after forming fin, adopt thermal oxidation technology to form the first silicon oxide layer in the sidewall surfaces of fin, the thickness of described the first silicon oxide layer is 1 nanometer～5 nanometer.
10. the formation method of semiconductor structure as described in claim 6 or 8, is characterized in that, the formation technique of described mask layer is multiple graphics masking process.
The 11. formation methods of semiconductor structure as claimed in claim 10, is characterized in that, when the formation technique of described mask layer is Dual graphing masking process, the formation technique of described mask layer is: at semiconductor substrate surface, form sacrificial film; Part surface in described sacrificial film forms patterned layer; Take described patterned layer as sacrificial film described in mask etching until expose Semiconductor substrate, form sacrifice layer; At described Semiconductor substrate and sacrificial layer surface deposition mask film; Return mask film described in etching until expose Semiconductor substrate, form mask layer, and remove described sacrifice layer.
12. as described in claim 6 or 8 the formation method of semiconductor structure, it is characterized in that, after forming fin, carry out thermal anneal process, the temperature of described thermal anneal process is 900 degrees Celsius～1100 degrees Celsius.
The 13. formation methods of semiconductor structure as claimed in claim 2, is characterized in that, the material of described mask layer is silicon nitride, silica or silicon oxynitride.
The 14. formation methods of semiconductor structure as claimed in claim 13, is characterized in that, when the material of described mask layer is silicon nitride, also comprise: between the top of fin and mask layer, form the second silicon oxide layer.
The 15. formation methods of semiconductor structure as claimed in claim 1, is characterized in that, the material of the material of described the first dummy gate layer and the second dummy gate layer is identical or different.
The 16. formation methods of semiconductor structure as claimed in claim 15, is characterized in that, the formation technique of described the first dummy gate layer or the second dummy gate layer is chemical vapor deposition method or physical gas-phase deposition; The material of described the first dummy gate layer or the second dummy gate layer is doped polycrystalline silicon, non-impurity-doped polysilicon, amorphous silicon, SiGe or amorphous carbon.
The 17. formation methods of semiconductor structure as claimed in claim 16, it is characterized in that, the chemical vapor deposition method parameter that forms described the second dummy gate layer is: temperature is 200-800 degree Celsius, and air pressure is 1 holder-100 holder, power is 300 watts～600 watts, and gas comprises HCl and H
2, the flow of HCl is 1sccm～1000sccm, H
2flow be 0.1slm～50slm; When the material of the second dummy gate layer is non-impurity-doped polysilicon, described gas also comprises silicon source gas SiH
4or SiH
2cl
2, the flow of described silicon source gas is 1sccm～1000sccm; When the material of the second dummy gate layer is SiGe, described gas also comprises silicon source gas SiH
4or SiH
2cl
2with germanium source gas GeH
4, the flow of described silicon source gas is 1sccm～1000sccm, the flow of described germanium source gas is 1sccm-1000sccm.
The 18. formation methods of semiconductor structure as claimed in claim 1, it is characterized in that, the formation technique of described dummy grid is: on the second dummy gate layer surface, form pseudo-grid mask, described pseudo-grid mask has defined the figure of dummy grid, and the material of described pseudo-grid mask is silicon nitride or silicon oxynitride; With described pseudo-grid mask etching the second dummy gate layer and the first dummy gate layer until expose fin top and sidewall surfaces.
The 19. formation methods of semiconductor structure as claimed in claim 1, is characterized in that, before forming the first dummy gate layer, at sidewall and top surface deposition the 3rd silicon oxide layer of described substrate surface and fin.
The 20. formation methods of semiconductor structure as claimed in claim 1, is characterized in that, also comprise: after forming dummy grid, form source region and drain region in the fin of described dummy grid both sides; After forming described source region and drain region, at sidewall and the top surface formation second medium layer of described substrate surface and fin, the surface of described second medium layer flushes with the top surface of dummy grid; After forming second medium layer, at the described dummy grid of described removal and form opening in second medium layer; In described opening, form gate dielectric layer, on described gate dielectric layer surface, form the gate electrode layer of filling full described opening.
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