CN109727976B - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN109727976B CN109727976B CN201711034035.7A CN201711034035A CN109727976B CN 109727976 B CN109727976 B CN 109727976B CN 201711034035 A CN201711034035 A CN 201711034035A CN 109727976 B CN109727976 B CN 109727976B
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Abstract
A semiconductor structure and a forming method thereof are provided, wherein the forming method comprises the following steps: the first dielectric layer is positioned on the substrate, covers the side wall of the grid electrode, is provided with a first groove, extends from the device region to the first dielectric layer of the isolation region, and the bottom of the first groove is exposed out of the top and the side wall surface of the source-drain doped layer; the metallization is positioned on the surface of the source drain doped layer exposed at the bottom of the first groove; and the second dielectric layer is positioned in the groove of the isolation region, and the second dielectric layer exposes the metallization on the top surface of the source-drain doping layer. The second dielectric layer can reduce the projection pattern area of the isolation region electric connection structure on the surface of the side wall of the grid, so that the parasitic capacitance formed by the electric connection structure, the grid and the first dielectric layer between the electric connection structure and the grid is reduced, and the performance of the formed semiconductor structure is improved.
Description
Technical Field
The present invention relates to the field of semiconductor manufacturing technologies, and in particular, to a semiconductor structure and a method for forming the same.
Background
With the continuous progress of semiconductor technology, the feature size of semiconductor devices is gradually becoming smaller. The shrinking of critical dimensions means that a greater number of transistors can be placed on a chip, while placing greater demands on the semiconductor process.
Since metal has good conductivity, in semiconductor technology, the source/drain doped region is often electrically connected to an external circuit through a metal plug. However, since the fermi level difference between the metal and the semiconductor is large, the potential barrier between the metal plug and the source-drain doped region is high, resulting in a large contact resistance between the metal plug and the source-drain doped region. In the prior art, a metal silicide is formed between a metal plug and a source-drain doped region to reduce contact resistance and improve the performance of a semiconductor structure.
However, the semiconductor structure formed in the prior art still has the problem that the contact resistance between the metal silicide and the source-drain doped region is large or the parasitic capacitance is large.
Disclosure of Invention
The invention provides a semiconductor structure and a forming method thereof, which can reduce the contact resistance between a metal silicide and a source-drain doped region and reduce the parasitic capacitance.
In order to solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: a substrate comprising adjacent device regions and isolation regions; a gate on the substrate, the gate extending from the device region to the isolation region; the top of the source-drain doping layer is higher than the surface of the substrate; the first dielectric layer is positioned on the substrate and covers the side wall of the grid electrode, a first groove is formed in the first dielectric layer and extends into the isolation region from the device region, and the bottom of the first groove is exposed out of the top of the source-drain doped layer and the surface of the side wall; the metallization is positioned on the surface of the source drain doped layer exposed at the bottom of the first groove; the second dielectric layer is positioned in the first groove of the isolation region, the second dielectric layer exposes the metallization on the top surface of the source-drain doped layer, the top of the second dielectric layer is higher than the bottom of the grid, and in the direction vertical to the side wall of the grid, the side walls on two sides of the second dielectric layer are respectively contacted with the side wall of the first groove; and the electric connection structure is positioned in the first groove and is electrically connected with the metallization on the top of the source-drain doping layer.
Optionally, the source-drain doping layer is made of silicon, germanium, silicon germanium or silicon carbide.
Optionally, the substrate includes: the source-drain doping layer is positioned in the fin part or on the surface of the fin part; the grid electrode covers the side wall and the top surface of the fin portion.
Optionally, the method further includes: the isolation structure is positioned on the isolation region substrate and covers the side wall of the fin part; the isolation region grid electrode is located on the isolation structure, and the second dielectric layer is located on the isolation region isolation structure.
Optionally, the source-drain doping layer is located in the substrate, an isolation region of the substrate has an isolation structure, the gate structure is located on the device region substrate and the isolation structure, and the second dielectric layer is located on the isolation region isolation structure.
Optionally, the isolation structure is exposed at the bottom of the first trench.
Optionally, the surface of the second dielectric layer of the isolation region is higher than or flush with the surface of the source-drain doped layer.
Optionally, the number of the device regions is multiple, and the isolation region is located between adjacent device regions; the electric connection structure is positioned on the second medium layer of the isolation region and the source-drain doping layers of the device regions.
Optionally, the first dielectric layer is made of silicon oxide, silicon nitride, silicon oxynitride or a low-k dielectric material; the second dielectric layer is made of silicon oxide, silicon nitride, silicon oxynitride or a low-k dielectric material.
Correspondingly, the technical scheme of the invention also provides a method for forming the semiconductor structure, which comprises the following steps: providing a substrate, the substrate comprising: adjacent device and isolation regions; forming a grid electrode, a source-drain doping layer and a first dielectric layer, wherein the grid electrode is positioned on the substrate and extends from the device region to the isolation region, the source-drain doping layer is positioned in the device region on two sides of the grid electrode, the substrate is exposed out of the surface of the source-drain doping layer, the first dielectric layer is positioned on the substrate and covers the side wall of the grid electrode, a first groove is formed in the first dielectric layer, the first groove extends from the first dielectric layer in the device region to the first dielectric layer in the isolation region, and the bottom of the first groove is exposed out of the top and the surface of the side wall of the source-drain doping layer; forming a metallization on the surface of the source drain doping layer exposed at the bottom of the first trench; forming a second dielectric layer in the first trench of the isolation region, wherein the second dielectric layer exposes the metallization on the top surface of the source-drain doped layer, the top of the second dielectric layer is higher than the bottom of the grid, and in the direction vertical to the side wall of the grid, the side walls on both sides of the second dielectric layer are respectively contacted with the side wall of the first trench; and after the second dielectric layer is formed, forming an electric connection structure in the first groove, wherein the electric connection structure is electrically connected with the metallization on the top of the source-drain doping layer.
Optionally, the first dielectric layer includes: the bottom dielectric layer is positioned on the substrate and exposes out of the top surface of the grid; the top dielectric layer is positioned on the bottom dielectric layer and the grid; the steps of forming the first dielectric layer, the gate and the source-drain doped layer include: forming a dummy gate on the substrate, the dummy gate extending from the device region to the isolation region; forming source and drain doped layers in substrate device regions on two sides of the pseudo gate, wherein the substrate is exposed out of the side walls of the source and drain doped layers; forming an initial bottom dielectric layer on the substrate and the source-drain doping layer, wherein the initial bottom dielectric layer covers the side wall of the pseudo gate; removing the pseudo grid and forming a grid opening in the initial bottom dielectric layer; forming a gate in the gate opening; forming an initial top dielectric layer on the grid and the initial bottom dielectric layer; after the grid electrode is formed, removing part of the initial top dielectric layer and part of the initial bottom dielectric layer through first imaging treatment, exposing the top and the side wall of the source-drain doping layer, enabling the initial top dielectric layer to form a top dielectric layer, enabling the initial bottom dielectric layer to form a bottom dielectric layer, and forming a first groove in the top dielectric layer and the bottom dielectric layer.
Optionally, the substrate isolation region has an isolation structure therein; the step of the first patterning process includes: forming a patterned first mask layer on the first initial dielectric layer, wherein the first mask layer is provided with a first opening, the first opening extends from the device region to the isolation region, and the first opening is positioned in the first mask layer on the source-drain doping layer; and etching the first initial dielectric layer by taking the first mask layer as a mask until the side wall of the source-drain doped layer is completely exposed.
Optionally, the step of forming the second dielectric layer includes: forming a second initial dielectric layer in the first groove, wherein the second initial dielectric layer completely fills the first groove; and etching the second initial dielectric layer through second patterning treatment, removing part of the second initial dielectric layer, exposing the top surface of the source-drain doping layer, and forming a second dielectric layer and a second groove in the second dielectric layer of the device region.
Optionally, the process for forming the second initial dielectric layer includes: a fluid chemical vapor deposition process, a plasma enhanced chemical vapor deposition process, or an atomic layer deposition process.
Optionally, the step of the second graphic processing includes: forming a patterned second mask layer on the second initial dielectric layer, wherein the device region second mask layer is provided with a second opening, the second opening extends from the device region to the isolation region, and the second opening is positioned in the second mask layer on the source-drain doping layer; and carrying out second etching on the second initial dielectric layer by taking the second mask layer as a mask until the metallization on the top of the source-drain doping layer is exposed.
Optionally, the second etching process includes a dry etching process.
Optionally, the first trench is only located in the second dielectric layer in the device region; or, the first trench extends from the device region to the isolation region, and the bottom of the isolation region is provided with the second dielectric layer.
Optionally, the number of the device regions is multiple, the number of the isolation regions is multiple, and the device regions and the isolation regions are alternately arranged; the second opening spans across a plurality of device regions and a plurality of isolation regions.
Optionally, the step of forming the metallization includes: forming metal layers on the side wall and the top surface of the source drain doping layer exposed at the bottom of the first groove; and annealing the metal layer, and reacting the metal layer with part of the source-drain doping layer to form the metallization.
Optionally, the metal layer is made of Ti, Co, Ni or Pt; the source-drain doped layer is made of silicon, germanium, silicon-germanium or silicon carbide.
Compared with the prior art, the technical scheme of the invention has the following advantages:
in the semiconductor structure provided by the technical scheme of the invention, the metalate is positioned on the side wall and the top surface of the source-drain doped layer, so that the contact area between the metalate and the source-drain doped layer is larger, and the contact resistance between the metalate and the source-drain doped layer can be reduced. Meanwhile, the electric connection structure is positioned in the first groove, a second dielectric layer is also arranged in the first groove of the isolation region, and the side walls of the two sides of the second dielectric layer are respectively contacted with the side walls of the first groove. The second dielectric layer occupies the space of a part of the first groove of the isolation region, so that the electric connection structure is only positioned in the first groove of the device region or is also positioned in the first groove of the partial isolation region. Therefore, the area of the projection pattern of the isolation region electric connection structure on the side wall surface of the grid electrode can be reduced by the second dielectric layer, and therefore parasitic capacitance formed by the electric connection structure, the grid electrode and the first dielectric layer between the electric connection structure and the grid electrode is reduced. In conclusion, the semiconductor structure can reduce the contact resistance between the metallization and the source-drain doping layer, and simultaneously reduce the parasitic capacitance, thereby improving the performance of the semiconductor structure.
Furthermore, the source-drain doping layer is located in the fin portion exposed by the isolation structure, the isolation structure is exposed at the bottom of the first groove, and the area of the side wall of the source-drain doping layer exposed by the first dielectric layer is large, so that the contact area between the metallization and the source-drain doping layer can be increased, the contact resistance between the metallization and the source-drain doping layer can be reduced, and the structural performance of the semiconductor can be improved.
In the method for forming the semiconductor structure provided by the technical scheme of the invention, the side wall and the top of the source-drain doping layer are exposed from the bottom of the first groove, so that the metalate can be positioned on the side wall and the top surface of the source-drain doping layer, and the contact resistance between the metalate and the drain doping layer can be reduced. And forming the electric connection structure after forming a second dielectric layer in the first groove. The second dielectric layer occupies a part of the first trench space of the isolation region, so that the electrical connection structure is only located in the first trench of the device region or is also located in the first trench of the isolation region. Therefore, the second dielectric layer can reduce the projection pattern area of the isolation region electric connection structure on the side wall surface of the grid, thereby reducing the parasitic capacitance formed by the electric connection structure, the grid and the first dielectric layer between the electric connection structure and the grid, and further improving the performance of the formed semiconductor structure.
Further, the first initial dielectric layer is subjected to first etching until the side wall of the source-drain doping layer is completely exposed, so that the contact area between the subsequently formed metal compound and the source-drain doping layer can be increased, the contact resistance between the metal compound and the source-drain doping layer can be reduced, and the performance of the formed semiconductor structure can be improved.
Furthermore, the surface of the second dielectric layer of the isolation region is higher than the surface of the source-drain doped layer, so that the space of the first groove occupied by the second dielectric layer is larger, the space of the first groove occupied by the electric connection structure is smaller, the area of the projection pattern of the electric connection structure on the side wall of the grid electrode is smaller, and the parasitic capacitance can be reduced.
Drawings
FIGS. 1-3 are schematic structural diagrams illustrating steps of a method for forming a semiconductor structure;
fig. 4 to 20 are schematic structural diagrams of steps of a method for forming a semiconductor structure according to an embodiment of the present invention.
Detailed Description
The semiconductor structure formed by the prior art has a plurality of problems, such as: the contact resistance between the metal silicide and the source-drain doped region is larger or the parasitic capacitance is larger.
Now, in combination with a method for forming a semiconductor structure, the reason why the contact resistance between a metal silicide of the semiconductor structure formed by the method and a source-drain doped region is large or the parasitic capacitance is large is analyzed:
fig. 1 to 3 are schematic structural diagrams of a semiconductor structure.
Referring to fig. 1 to 3, fig. 3 is a cross-sectional view taken along a cutting line a4-a4 ' in fig. 1, fig. 1 is a cross-sectional view taken along a cutting line A3-A3 ' in fig. 3, and fig. 2 is a cross-sectional view taken along a cutting line a2-a2 ' in fig. 3, wherein the semiconductor structure includes: a substrate 100, wherein the substrate 100 is provided with a fin part 101; an isolation structure 102 located on the substrate 100, wherein the isolation structure 102 covers a part of the sidewall of the fin 101, and the surface of the isolation structure 102 is lower than the top surface of the fin 101; a gate 111 crossing the fin 101, wherein the gate 111 covers a part of the surface of the isolation structure 102, and a part of the sidewall and the top surface of the fin 101; the doping layer 110 is positioned in the fin part 101 on two sides of the grid electrode 111; a dielectric layer 120 covering the gate 111, the doped layer 110 and the isolation structure 102; a trench in the dielectric layer 120, wherein the top and sidewalls of the doped layer 110 and the surface of the isolation structure 102 are exposed at the bottom of the trench; metal silicide 131 on the top and sidewall surfaces of the doped layer 110 exposed at the bottom of the trench; an electrical connection structure 130 located in the trench, the metal silicide 131 being located between the electrical connection structure 130 and the doped layer 110.
The depth of the trench is large, so that the dielectric layer 120 can expose the top and sidewall surfaces of the doped layer 110, and the metal silicide 110 is located on the top and sidewall surfaces of the doped layer 110, thereby increasing the contact area between the metal silicide 110 and the doped layer 110, and further reducing the contact resistance between the metal silicide 131 and the doped layer 110.
However, since the trench exposes the isolation structure 102, the electrical connection structure 130 is filled in the trench, so that the dimension of the electrical connection structure 130 on the isolation structure 102 in the direction perpendicular to the surface of the substrate 100 is larger, resulting in a larger projection area of the electrical connection structure 130 on the sidewall surface of the gate 111. The electrical connection structure 130, the gate 111, and the dielectric layer 120 between the electrical connection structure 130 and the gate 111 form a parasitic capacitor. The projected area of the electrical connection structure 130 on the sidewall surface of the gate 111 is large, which results in large parasitic capacitance, and thus easily affects the performance of the formed semiconductor structure.
In order to solve the technical problem, the invention provides a method for forming a semiconductor structure, which comprises the following steps: the first groove exposes the side wall and the top of the source-drain doped layer, so that the metallization can be positioned on the side wall and the top surface of the source-drain doped layer, and the contact resistance between the metallization and the drain doped layer can be reduced. In addition, the first groove is provided with a second dielectric layer. The second dielectric layer occupies a part of the first trench space of the isolation region. The second dielectric layer can reduce the projection pattern area of the isolation region electric connection structure on the surface of the side wall of the grid, so that the parasitic capacitance value of the capacitor formed by the electric connection structure, the grid and the first dielectric layer between the electric connection structure and the grid is reduced, and the performance of the formed semiconductor structure is improved.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 4 to 20 are schematic structural diagrams of steps of a method for forming a semiconductor structure according to an embodiment of the present invention.
Referring to fig. 4, a substrate is provided, which includes adjacent device regions a and isolation regions B.
In this embodiment, the substrate includes a base 200 and a fin 201 on the base 200. In other embodiments, the substrate may also be a planar substrate, such as a semiconductor substrate, e.g., a silicon substrate, a germanium substrate, a silicon-on-insulator, a germanium-on-insulator, or a silicon-germanium-on-insulator.
The number of the device regions A is single or multiple, the number of the isolation regions B is single or multiple, and the isolation regions B are positioned between the adjacent device regions A. In this embodiment, the number of the device regions a is two, the number of the isolation regions B is multiple, and the isolation regions B and the device regions a are alternately arranged.
Specifically, in this embodiment, the two device regions a are a first device region and a second device region, respectively.
The device regions A are used for forming MOS transistors, and the isolation regions B are used for realizing electric isolation between the device regions A.
Specifically, in this embodiment, the first device region is used to form a PMOS transistor. The second device region is used for forming an NMOS transistor. In other embodiments, the first device region is used to form NMOS transistors and the second device region is used to form PMOS transistors; or the first device area and the second device area are both used for forming NMOS transistors; the first device region and the second device region are both used for forming PMOS transistors.
In this embodiment, the substrate 200 and the fin 201 are made of silicon, silicon germanium, or germanium.
With continued reference to fig. 4, an isolation structure 202 is formed on the substrate 200, wherein the isolation structure 202 covers a portion of the sidewall of the fin 201, and the surface of the isolation structure 202 is lower than the top surface of the fin 201.
The isolation structure 202 is used for realizing electrical isolation between adjacent fins 201, and the isolation structure 202 is also used for realizing electrical isolation between a subsequently formed isolation region B gate and a substrate.
The isolation structure 202 is made of silicon oxide. In other embodiments, the material of the isolation structure may also be silicon nitride or silicon oxynitride.
In this embodiment, the process of forming the isolation structure 202 includes: chemical vapor deposition process. In other embodiments, the process of forming the isolation structure may also be a physical vapor deposition process or an atomic layer deposition process.
In other embodiments, the substrate is a planar substrate, and the isolation structure is located in the isolation region substrate.
And forming a grid electrode, a source-drain doping layer and a first dielectric layer subsequently, wherein the grid electrode is positioned on the substrate and extends from the device area A to the isolation area B, the source-drain doping layer is positioned in the device area A at two sides of the grid electrode, the substrate is exposed out of the surface of the source-drain doping layer, the first dielectric layer is positioned on the substrate, the first dielectric layer covers the side wall of the grid electrode 233, a first groove is formed in the first dielectric layer, the first groove extends from the first dielectric layer of the device area A to the first dielectric layer of the isolation area B, and the bottom of the first groove 215 is exposed out of the top and the surface of the side wall of the source-drain doping layer.
In this embodiment, the first dielectric layer includes: the bottom dielectric layer is positioned on the substrate and exposes out of the top surface of the grid; and the top dielectric layer is positioned on the bottom dielectric layer and the grid electrode.
In this embodiment, the semiconductor structure is formed by a gate last process. In other embodiments, the semiconductor structure may also be formed by a gate-front process. Specifically, the steps of forming the gate, the source-drain doping layer and the first dielectric layer are shown in fig. 5 to 12.
Referring to fig. 5 and 6, fig. 6 is a cross-sectional view taken along cutting line C1-C1' in fig. 5, wherein a dummy gate 230 is formed on the substrate, and the dummy gate 230 extends from the device region a to the isolation region B.
The dummy gate 230 is used to provide space for the subsequent formation of a gate.
In this embodiment, the dummy gate 230 is a long strip. The extension direction of the dummy gate 230 is the same as the arrangement direction of the device region a and the isolation region B.
In this embodiment, the dummy gate 230 crosses over the first device region, the second device region and the plurality of isolation regions B. The dummy gate 230 is located on a portion of the sidewall and top surface of the fin 201 and on a portion of the isolation structure 202 of the isolation region B.
The dummy gate 230 is made of silicon, germanium or silicon germanium.
The step of forming the dummy gate 230 includes: forming a dummy gate layer crossing the fin 201, the dummy gate layer extending from the device region a to an isolation region B; the dummy gate layer is patterned to form the dummy gate 230.
Before forming the dummy gate 230, further comprising: and forming a dummy gate dielectric layer 232 crossing the fin portion 201, wherein the dummy gate dielectric layer 232 covers part of the side wall and the top surface of the fin portion 201.
The dummy gate dielectric layer 232 is made of silicon oxide.
After the dummy gate 230 is formed, the method further includes: and forming a side wall 231 on the surface of the side wall of the dummy gate 230.
The side wall 231 is used for fixing the position of a source-drain doped layer formed subsequently, so that the source-drain doped layer is prevented from being too close to a transistor channel, and source-drain punch-through can be inhibited; in addition, the sidewall 231 may also protect the gate in the subsequent etching process of the first dielectric layer.
And forming a source-drain doped layer in the substrate device region a on both sides of the dummy gate 230, wherein the substrate exposes the sidewall of the source-drain doped layer.
In this embodiment, the source-drain doped layer is located in the substrate. The number of the device regions A is two, the number of the source-drain doping layers is multiple, and the source-drain doping layers comprise a first source-drain doping layer located in the first device region; and the second source-drain doped layer is positioned in the second device region.
Specifically, in this embodiment, the steps of forming the source-drain doping layer are as shown in fig. 7 to 9.
Referring to fig. 7, first source-drain doping layers 271 are formed in the first device region substrate at two sides of the dummy gate 230.
The first source-drain doped layer 271 has first doped ions therein.
The first source-drain doping layer 271 is used for forming a source region or a drain region of a PMOS transistor, and the first doping ions are P-type ions, such as boron ions or BF2 +Ions.
In this embodiment, the step of forming the first source-drain doping layer 271 includes: forming a first fin side wall 241 on the side wall of the fin 201 in the first device region; forming a first protective layer 281 covering the sidewalls and the top of the second device region fin 201; forming first grooves in the first device region fin 201 on two sides of the gate 233, wherein the first grooves are located between the first fin side walls 241; after the first protection layer 281 is formed, a first source drain doping layer 271 is formed in the first groove.
The first protection layer 281 is used for preventing a first source-drain doping layer 271 material from being formed on the surface of the second device region fin 201 in the process of forming the first source-drain doping layer 271; the first fin side wall 241 is configured to limit a dimension of the first source-drain doping layer 271 in a direction perpendicular to the side wall of the first device region fin 201, so as to inhibit the first source-drain doping layer 271 from contacting a subsequently formed second source-drain doping layer.
In this embodiment, the steps of forming the first protection layer 281 and the first fin sidewall 241 include: forming a first initial protection layer covering the side walls and the tops of the first device region fin 201 and the second device region fin 201; and removing the first initial protection layer on the top of the first device region fin 201, forming a first fin sidewall 241 on the sidewall of the first device region fin 201, and forming a first protection layer 281 on the sidewall and the top of the second device region fin 201.
The first initial protection layer is made of silicon nitride, silicon oxynitride or silicon oxide.
The process of forming the first initial protection layer is a furnace process, and the furnace process comprises a low temperature oxidation (HTO) process.
The process parameters for forming the first initial protection layer comprise: the reaction gas comprises silane (DCS) and NH3(ii) a The reaction temperature is 650-800 ℃.
The process of removing the first initial protection layer on the top of the fin 201 in the first device region includes an anisotropic dry etching process.
In this embodiment, after forming the first groove, the method further includes: and performing first side wall etching on the side wall of the first fin side wall 241, and increasing the size of the first groove along the side wall perpendicular to the fin 201 in the first device region.
The first sidewall etching is used for increasing the size of the first groove along the side wall perpendicular to the fin portion 201 of the first device region and increasing the size of a first source-drain doping layer formed subsequently, so that the stress provided by the first source-drain doping layer to a formed transistor channel is increased, and the performance of a formed semiconductor structure is improved.
In this embodiment, the first sidewall etching process includes an isotropic dry etching process. In other embodiments, the first sidewall etching process may also be a wet etching process.
In this embodiment, the first source-drain doping layer 271 is made of silicon germanium. The silicon germanium can provide compressive stress to the channel of the PMOS transistor being formed, thereby increasing the mobility rate of carriers in the channel of the PMOS transistor. In other embodiments, the material of the first source-drain doping layer may also be silicon. The first device region is used for forming an NMOS transistor, and the material of the first source-drain doped layer may also be silicon carbide.
Referring to fig. 8 and 9, fig. 9 is a cross-sectional view taken along cutting line B2-B2' in fig. 8, and a second source/drain doped layer 272 is formed in the second device region substrate at two sides of the dummy gate 230.
The second source-drain doped layer 272 has second doped ions therein.
The second source-drain doped layer 272 is used to form a source region or a drain region of the PMOS transistor, and the second doped ions are P-type ions, such as boron ions or BF2 +Ions.
In this embodiment, the step of forming the second source-drain doping layer 272 includes: forming second fin side walls 242 on the surfaces of the side walls of the fins 201 in the second device region; forming a second protection layer 282 covering the sidewalls and the top of the first device region fin 201; forming second grooves in the fin 201 in the second device region on two sides of the gate 233, wherein the second grooves are located between the second fin sidewalls 242; after the second passivation layer 282 is formed, a second source-drain doping layer 272 is formed in the second groove.
The second protection layer 282 is used for preventing a second source-drain doping layer 272 material from being formed on the surface of the first source-drain doping layer 271 in the process of forming the second source-drain doping layer 272; the second fin sidewall 242 is configured to limit a dimension of the second source-drain doping layer 272 in a direction perpendicular to the sidewall of the second device region fin 201, so as to inhibit the first source-drain doping layer 271 from contacting with a subsequently formed second source-drain doping layer.
In this embodiment, the steps of forming the second protection layer 282 and the second fin sidewall 242 include: forming a second initial protection layer covering the sidewalls and the tops of the second device region fin 201 and the first device region fin 201; and removing the second initial protection layer on the top of the fin 201 in the second device region, forming second fin side walls 242 on the side walls of the fin 201 in the second device region, and forming second protection layers 282 on the side walls and the top of the fin 201 in the second device region.
In this embodiment, after the first fin sidewall 241 and the first protection layer 281 are formed, the second fin sidewall 242 and the second protection layer 282 are formed. The second initial protection layer covers the first fin sidewall 241 and the first protection layer 281. In other embodiments, the first fin sidewall and the first protective layer may also be formed after the second fin sidewall and the second protective layer are formed.
In this embodiment, the first device region is used to form a PMOS transistor, and the second device region is used to form an NMOS transistor, and then the first doped ions are different from the second doped ions.
In this embodiment, after the first source-drain doping layer 271 is formed, a second source-drain doping layer 272 is formed. The second initial protection layer covers the surface of the first source-drain doping layer 271 and the surface of the first protection layer 281. In other embodiments, the first source-drain doping layer may be formed after the second source-drain doping layer is formed.
The second initial protection layer is made of silicon nitride, silicon oxynitride or silicon oxide.
The process of forming the second initial protection layer is a furnace tube process, and the furnace tube process comprises a low temperature oxidation (HTO) process.
The process parameters for forming the second initial protection layer comprise: the reaction gas comprises silane (DCS) and NH3(ii) a The reaction temperature is 650-800 ℃.
The process of removing the second initial protection layer on the top of the fin 201 in the second device region includes an anisotropic dry etching process.
In this embodiment, after forming the second groove, the method further includes: and performing second sidewall etching on the sidewalls of the second fin sidewall 242, and increasing the dimension of the second groove along the sidewall perpendicular to the sidewalls of the second device region fin 201.
The second sidewall etching is used for increasing the dimension of the second groove along the sidewall perpendicular to the fin 201 of the second device region and increasing the dimension of the second source-drain doping layer 272, so that the stress provided by the second source-drain doping layer 272 to the formed transistor channel is increased, and the performance of the formed semiconductor structure is improved.
In this embodiment, the second sidewall etching process includes an isotropic dry etching process. In other embodiments, the second sidewall etching process may also be a wet etching process.
In this embodiment, the second source-drain doping layer 272 is made of silicon carbide. Silicon carbide can provide tensile stress to the channel of the NMOS transistor formed, thereby increasing the mobility rate of carriers in the channel of the NMOS transistor. In other embodiments, the material of the second source-drain doping layer may also be silicon.
In other embodiments, the second device region is used to form a PMOS transistor, and the second source-drain doping layer is made of silicon germanium or silicon.
Referring to fig. 10 and 11, in fig. 10, the cross-sectional view of fig. 11 along the cutting line B3-B3' is shown, an initial bottom dielectric layer 210 is formed on the substrate and the source-drain doped layer, and the initial bottom dielectric layer 210 covers the sidewall of the dummy gate 230 and exposes the top surface of the dummy gate 230.
The initial bottom dielectric layer 210 is used for subsequent formation of a bottom dielectric layer.
In this embodiment, the initial bottom dielectric layer 210 is made of silicon oxide. In other embodiments, the material of the initial bottom dielectric layer is a low-k dielectric layer, and k is less than 3.9.
The step of forming the initial underlying dielectric layer 210 includes: forming an initial bottom dielectric film on the substrate, the source-drain doping layer and the dummy gate 230; and carrying out planarization treatment on the initial bottom dielectric film to expose the top surface of the dummy gate 230 to form an initial bottom dielectric layer 210.
In this embodiment, the process of forming the initial underlying dielectric film includes a fluid chemical vapor deposition process. The initial bottom dielectric film formed by the fluid chemical vapor deposition process has good filling performance, and can fully fill the gap between the first source-drain doping layer 271 and the second source-drain doping layer 272. In other embodiments, the process for forming the initial underlying dielectric film comprises a plasma enhanced chemical vapor deposition process.
The planarization treatment process comprises a chemical mechanical polishing process.
Referring to fig. 12, the dummy gate 230 (shown in fig. 11) is removed, and a gate opening is formed in the initial underlying dielectric layer 210; forming a gate 233 in the gate opening; an initial top dielectric layer 213 is formed over the gate 233 and the initial bottom dielectric layer 210.
The initial top dielectric layer 213 is used for subsequent top dielectric layer formation.
The process of removing the dummy gate 230 includes one or a combination of a dry etching process and a wet etching process.
The gate 233 is made of metal, for example: al, Cu, Ag, Au, Ni, Ti, W, WN or WSi.
Before forming the gate 233, the method further includes: and forming a gate dielectric layer 232 on the side wall and the bottom of the gate opening.
The gate dielectric layer 232 is used to electrically isolate the gate 233 from the substrate.
The material of the gate dielectric layer 232 includes a high-k (k is greater than 3.9) dielectric material, such as: HfO2、La2O3、HfSiON、HfAlO2、ZrO2、Al2O3Or HfSiO4。
The initial top dielectric layer 213 is made of silicon oxide or a low-K (K is less than 3.9) dielectric material, and the low-K dielectric material is a porous material. The low-k dielectric material comprises: carbon-doped silicon oxide, nitrogen-doped silicon carbide, fluorinated silica glass, polyimide porous materials or polyethylene porous materials.
In this embodiment, the process of forming the initial top dielectric layer 213 includes a chemical vapor deposition process.
Referring to fig. 13, after the gate 233 is formed, a portion of the initial top dielectric layer 213 (as shown in fig. 12) and a portion of the initial bottom dielectric layer 210 (as shown in fig. 12) are removed by a first patterning process, and the top and sidewalls of the source and drain doping layers are exposed, so that the initial top dielectric layer 213 forms a top dielectric layer 214, the initial bottom dielectric layer 210 forms a bottom dielectric layer 211, and a first trench 215 is formed in the top dielectric layer 214 and the bottom dielectric layer 211.
The bottom dielectric layer 211 is used for realizing electrical isolation between subsequently formed electrical connection structures; the top dielectric layer 214 is used to electrically isolate the gate 233 from external circuitry. The top dielectric layer 214 and the bottom dielectric layer 211 form a first dielectric layer; the first trench 215 is used to expose the top and the sidewall of the source-drain doped layer, so that a metallization can be formed on the sidewall and the top surface of the source-drain doped layer in the following process.
The step of the first patterning process includes: forming a patterned first mask layer on the first initial dielectric layer, wherein the first mask layer is provided with a first opening, the first opening extends from the device region A to the isolation region B, and the first opening is positioned in the first mask layer on the source-drain doping layer; and carrying out first etching on the first initial dielectric layer by taking the first mask layer as a mask until the side wall of the source-drain doped layer is completely exposed.
And performing first etching on the first initial dielectric layer until the side wall of the source-drain doped layer is completely exposed, so that the contact area between the subsequently formed metallization 250 and the source-drain doped layer can be increased, the contact resistance between the metallization 250 and the source-drain doped layer can be reduced, and the performance of the formed semiconductor structure can be improved.
Specifically, in this embodiment, the source-drain doped layer is located in the fin portion 201 exposed by the isolation structure 202. The first etching is performed until the isolation structure 202 is exposed, so that the first dielectric layer can completely expose the sidewalls of the source-drain doped layers.
In this embodiment, the first opening is a long strip, and the first opening spans across the plurality of device regions a and the isolation region B. The first trench 215 is a long stripe shape, and the first trench 215 penetrates through the first dielectric layers of the isolation regions B and the device region a.
The process for etching the first initial dielectric layer comprises the following steps: one or two of the dry etching process and the wet etching process are combined.
The first mask layer is made of photoresist.
Referring to fig. 14 and 15, fig. 15 is a cross-sectional view taken along a cutting line C3-C3 'in fig. 14, and fig. 14 is a cross-sectional view taken along a cutting line C5-C5' in fig. 15, after the first trench 215 is formed, the first protective layer 281, the first fin sidewall 241, the second protective layer 282, and the second fin sidewall 242 are removed.
The first protection layer 281, the first fin side wall 241, the second protection layer 282 and the second fin side wall 242 are removed to expose the source-drain doping layer.
In this embodiment, the process of removing the first protection layer 281, the first fin sidewall 241, the second protection layer 282, and the second fin sidewall 242 includes one or two of a dry etching process and a wet etching process.
Referring to fig. 16, a metallization 250 is formed on the surface of the source-drain doped layer exposed at the bottom of the first trench 215.
The metallization 250 is used for reducing the contact resistance between the subsequently formed electrical connection structure and the source-drain doping layer.
The first trench 215 exposes the sidewall and the top of the source-drain doped layer, so that the metallization 250 can be located on the sidewall and the top surface of the source-drain doped layer, and the contact resistance between the metallization 250 and the source-drain doped layer can be reduced.
In this embodiment, the step of forming the metallization 250 includes: forming a metal layer on the bottom and sidewall surfaces of the first trench 215; and annealing the metal layer, and reacting the metal layer with part of the source-drain doping layer to form the metallization 250.
The annealing process is used to react the metal layer with a portion of the source drain doping layer to form the metallization 250.
The metal layer is made of Ti, Co, Ni or Pt.
After the annealing treatment, the method further comprises the following steps: and removing the metal layer on the surface of the first dielectric layer.
And removing the metal layer on the surface of the first dielectric layer can prevent the metal layer from influencing the isolation performance of the first dielectric layer and the subsequently formed second dielectric layer.
A second dielectric layer is subsequently formed in the first trench 215 (as shown in fig. 16) of the isolation region B, the second dielectric layer exposes the metallization 250 on the top surface of the source-drain doping layer, the top of the second dielectric layer is higher than the bottom of the gate 233, and two ends of the second dielectric layer 221 are respectively in contact with the side wall of the first trench 215.
In this embodiment, the second dielectric layer 221 has a second trench therein, and the metallization 250 on the top of the fin 201 is exposed at the bottom of the second trench. Specifically, the steps of forming the second dielectric layer and the second trench are shown in fig. 17 and fig. 19.
Referring to fig. 17, a second initial dielectric layer 220 is formed in the first trench 215 (as shown in fig. 16), and the second initial dielectric layer 220 completely fills the first trench 215.
The second initial dielectric layer 220 is used for subsequent formation of a second dielectric layer.
In this embodiment, the second initial dielectric layer 220 is made of silicon oxide. In other embodiments, the material of the second initial dielectric layer may also be a low-k (k less than 3.9) dielectric material. The low-k dielectric material comprises: carbon-doped silicon oxide, nitrogen-doped silicon carbide, fluorinated silica glass, polyimide porous materials or polyethylene porous materials.
The process for forming the second initial dielectric layer 220 includes: a fluid chemical vapor deposition process. The second initial dielectric layer 220 formed by the fluid chemical vapor deposition process has good gap filling capability, and can fully fill the first trench 215, thereby increasing the isolation performance of the subsequently formed second dielectric layer. In other embodiments, the process for forming the second initial dielectric layer includes a plasma enhanced chemical vapor deposition process or an atomic layer deposition process.
When the material of the second initial dielectric layer is a low-k dielectric material, a spin coating process may also be used to form the second initial dielectric layer.
Referring to fig. 18, the second initial dielectric layer 220 is etched through a second patterning process to remove a portion of the second initial dielectric layer 220 and expose the metallization 250 on the top surface of the source-drain doping layer, so as to form a second dielectric layer 221 and a second trench 222 located in the second dielectric layer 221.
The second trench 222 is used for subsequently accommodating an electrical connection structure, and the bottom of the second trench 222 has a second dielectric layer 221, so that the second dielectric layer 221 occupies a part of the space of the first trench 215 (as shown in fig. 18) of the isolation region B, so that the electrical connection structure formed subsequently is only located in the first trench 215 of the device region a or is also located in the first trench 215 of the isolation region B. Therefore, the second dielectric layer 221 can reduce the projection pattern area of the electrical connection structure of the isolation region B on the sidewall surface of the gate 233, thereby reducing the parasitic capacitance of the capacitor formed by the electrical connection structure 260, the gate 233, and the first dielectric layer 211 between the electrical connection structure 260 and the gate 233, and further improving the performance of the formed semiconductor structure.
The step of the second patterning process includes: forming a patterned second mask layer on the second initial dielectric layer 220, wherein the second mask layer in the device region a has a second opening therein, the second opening extends from the device region a to the isolation region B, and the second opening is located in the second mask layer on the source-drain doping layer; and performing second etching on the second initial dielectric layer 220 by using the second mask layer as a mask until the metallization 250 at the top of the source-drain doping layer is exposed.
In this embodiment, the first source-drain doping layer 271 needs to be electrically connected to the second source-drain doping layer 272 through a subsequently formed electrical connection structure. Thus, the second opening spans the isolation region B and the plurality of device regions a, and the second trench 222 spans the isolation region B and the plurality of device regions a. Specifically, the second opening extends from the first device region to the second device region, and the second trench 222 extends from the first device region to the second device region.
In this embodiment, the second trench extends from the device region a to the isolation region B, and the bottom of the second trench 222 of the isolation region B has a second dielectric layer 221. In other embodiments, the second opening may be located only in the device region, and the second trench may be located only in the device region.
In this embodiment, the second etching is stopped until the metallization 250 on the top of the source-drain doping layer is exposed. Since the top surface of the source-drain doped layer is higher than the surface of the substrate 200, after the second etching, the isolation structure 202 of the isolation region B further has a second dielectric layer 221.
In this embodiment, the second etching process includes a dry etching process. The dry etching process has good linewidth control, and can accurately control the position and size of the second trench 222.
In other embodiments, the step of forming the second dielectric layer includes: and forming a second dielectric layer in the first groove of the isolation region by a fluid chemical vapor deposition process, wherein the surface of the second dielectric layer is higher than the bottom surface of the grid, and the second dielectric layer exposes the metallization on the top of the source-drain doped layer.
In this embodiment, the surface of the second dielectric layer 221 in the isolation region B is flush with the surface of the source-drain doped layer.
In other embodiments, the surface of the second dielectric layer of the isolation region is higher than the surface of the source-drain doped layer, so that the space of the first trench occupied by the second dielectric layer is larger, the space occupied by the electrical connection structure is smaller, the area of a projection pattern of the electrical connection structure on the side wall of the gate is smaller, and the parasitic capacitance can be reduced.
Referring to fig. 19 and 20, fig. 20 is a cross-sectional view taken along cutting line B4-B4' in fig. 19, after the second dielectric layer 221 is formed, an electrical connection structure 260 is formed in the first trench 215 (as shown in fig. 16), and the electrical connection structure 260 is electrically connected to the metallization 250 on the top of the source-drain doping layer.
The electrical connection structure 260 is used for electrically connecting the source-drain doped layer with an external circuit.
It should be noted that, due to the second dielectric layer 221 in the first trench 215 (as shown in fig. 16), the electrical connection structure 260 is only located in the first trench 215 of the device region a or the partial isolation region B. Therefore, the second dielectric layer 221 can reduce the projection pattern area of the isolation region B electrical connection structure 260 on the sidewall surface of the gate 233, thereby reducing the parasitic capacitance of the capacitor formed by the electrical connection structure 260, the gate 233, and the first dielectric layer 211 between the electrical connection structure 260 and the gate 233, and further improving the performance of the formed semiconductor structure.
In this embodiment, the second dielectric layer 221 has a second trench 222 therein (as shown in fig. 18), and the electrical connection structure 260 is located in the second trench 222.
The material of the electrical connection structure 260 is tungsten or copper.
The process of forming the electrical connection structure 260 includes an electroplating process.
Before forming the electrical connection structure 260, the forming method further includes: a barrier layer is formed at the bottom and sidewall surfaces of the second trench 222.
The barrier layer is used for preventing atoms in the material of the electrical connection structure 260 from diffusing into the first dielectric layer and the second dielectric layer 221 to affect the isolation performance of the first dielectric layer and the second dielectric layer 221, so that the isolation performance of the first dielectric layer and the second dielectric layer 221 is improved.
The barrier layer is made of titanium nitride or tantalum nitride.
With continuing reference to fig. 19 and 20, embodiments of the present invention also provide a semiconductor structure, comprising: a substrate, the substrate comprising: adjacent device region A and isolation region B; a gate 233 on the substrate, the gate 233 extending from the device region a to the isolation region B; the source-drain doping layers are positioned in the device region A on two sides of the grid 233, and the tops of the source-drain doping layers are higher than the surface of the substrate; the first dielectric layer is positioned on the substrate, covers the side wall of the grid 233, is provided with a first groove, extends from the device region A to the first dielectric layer of the isolation region B, and exposes the top and the side wall surface of the source-drain doped layer at the bottom of the first groove; the metallization 250 is positioned on the surface of the source drain doped layer exposed at the bottom of the first groove; the second dielectric layer 221 is positioned in the trench of the isolation region B, the metallization 250 on the top surface of the source-drain doping layer is exposed out of the second dielectric layer 221, the top of the second dielectric layer 221 is higher than the bottom of the gate 233, and in the direction perpendicular to the side wall of the gate, the side walls on the two sides of the second dielectric layer are respectively contacted with the side wall of the first trench; and the electric connection structure 260 is positioned in the first groove, and the electric connection structure 260 is electrically connected with the metallization 250 at the top of the source-drain doping layer.
The source-drain doped layer is made of silicon, germanium, silicon-germanium or silicon carbide.
In this embodiment, the substrate includes: the device region A comprises a substrate 200 and a fin portion 201 located on the substrate 200 of the device region A, wherein the source-drain doping layer is located in the fin portion 201 or on the surface of the fin portion 201; the gate 233 covers a portion of the sidewalls and top surface of the fin 201 and a portion of the surface of the isolation region B substrate 200.
The semiconductor structure further includes: an isolation structure 202 located on the isolation region B substrate 200, wherein the isolation structure 202 covers a portion of the sidewall of the fin 201; the isolation region B gate 233 is located on the isolation structure 202, and the second dielectric layer 221 is located on the isolation region B isolation structure 202.
In this embodiment, the source-drain doping layer is located in the substrate, the top of the source-drain doping layer is higher than the surface of the substrate, the isolation region B of the substrate has an isolation structure 202 therein, the gate 233 structure 202 is located on the substrate of the device region a and the isolation structure 202, and the second dielectric layer 221 is located on the isolation structure 202 of the isolation region B.
In this embodiment, the source-drain doped layer is located in the fin portion 201 exposed by the isolation structure 202, and the isolation structure 202 is exposed at the bottom of the first trench.
In this embodiment, the surface of the second dielectric layer 221 in the isolation region B is higher than or flush with the surface of the source-drain doped layer.
In this embodiment, the number of the device regions a is multiple, and the isolation region B is located between adjacent device regions a; the electrical connection structure 260 is located on the second dielectric layer 221 in the isolation region B and the source-drain doped layers in the plurality of device regions a. In other embodiments, the number of the device regions is single, and the number of the isolation regions is single.
The first dielectric layer includes: a bottom dielectric layer on the substrate, wherein the bottom dielectric layer covers the side wall of the gate 233 and exposes the top of the gate 233; and a top dielectric layer 214 located on the bottom dielectric layer and the gate 233.
The first dielectric layer is made of silicon oxide, silicon nitride, silicon oxynitride or a low-k dielectric material; the second dielectric layer 221 is made of silicon oxide, silicon nitride, silicon oxynitride, or a low-k dielectric material.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (20)
1. A semiconductor structure, comprising:
a substrate comprising adjacent device regions and isolation regions;
a gate on the substrate, the gate extending from the device region to the isolation region;
the top of the source-drain doping layer is higher than the surface of the substrate;
the first dielectric layer is positioned on the substrate and covers the side wall of the grid electrode, a first groove is formed in the first dielectric layer and extends into the isolation region from the device region, and the bottom of the first groove is exposed out of the top of the source-drain doped layer and the surface of the side wall;
the metallization is positioned on the surface of the source drain doped layer exposed at the bottom of the first groove;
the second dielectric layer is positioned in the first groove of the isolation region, the second dielectric layer exposes the metallization on the top surface of the source-drain doped layer, the top of the second dielectric layer is higher than the bottom of the grid, and in the direction vertical to the side wall of the grid, the side walls on two sides of the second dielectric layer are respectively contacted with the side wall of the first groove;
and the electric connection structure is positioned in the first groove and is electrically connected with the metallization on the top of the source-drain doping layer.
2. The semiconductor structure of claim 1, wherein the source-drain doped layer is made of silicon, germanium, silicon-germanium or silicon carbide.
3. The semiconductor structure of claim 1, wherein the substrate comprises: the source-drain doping layer is positioned in the fin part or on the surface of the fin part; the grid electrode covers the side wall and the top surface of the fin portion.
4. The semiconductor structure of claim 3, further comprising: the isolation structure is positioned on the isolation region substrate and covers the side wall of the fin part; the isolation region grid electrode is located on the isolation structure, and the second dielectric layer is located on the isolation region isolation structure.
5. The semiconductor structure of claim 1, wherein the source-drain doped layer is located in the substrate, an isolation region of the substrate has an isolation structure therein, the gate structure is located on the device region substrate and the isolation structure, and the second dielectric layer is located on the isolation region isolation structure.
6. The semiconductor structure of claim 3 or 5, wherein the isolation structure is exposed at the bottom of the first trench.
7. The semiconductor structure of claim 1, wherein the isolation region second dielectric layer surface is higher than or flush with the source drain doped layer surface.
8. The semiconductor structure of claim 1, wherein there are a plurality of said device regions, said isolation region being located between adjacent device regions; the electric connection structure is positioned on the second medium layer of the isolation region and the source-drain doping layers of the device regions.
9. The semiconductor structure of claim 1, wherein the first dielectric layer is made of silicon oxide, silicon nitride, silicon oxynitride, or a low-k dielectric material; the second dielectric layer is made of silicon oxide, silicon nitride, silicon oxynitride or a low-k dielectric material.
10. A method of forming a semiconductor structure, comprising:
providing a substrate, the substrate comprising: adjacent device and isolation regions;
forming a grid electrode, a source-drain doping layer and a first dielectric layer, wherein the grid electrode is positioned on the substrate and extends from the device region to the isolation region, the source-drain doping layer is positioned in the device region on two sides of the grid electrode, the substrate is exposed out of the surface of the source-drain doping layer, the first dielectric layer is positioned on the substrate and covers the side wall of the grid electrode, a first groove is formed in the first dielectric layer, the first groove extends from the first dielectric layer in the device region to the first dielectric layer in the isolation region, and the bottom of the first groove is exposed out of the top and the surface of the side wall of the source-drain doping layer;
forming a metallization on the surface of the source drain doping layer exposed at the bottom of the first trench;
forming a second dielectric layer in the first trench of the isolation region, wherein the second dielectric layer exposes the metallization on the top surface of the source-drain doped layer, the top of the second dielectric layer is higher than the bottom of the grid, and in the direction vertical to the side wall of the grid, the side walls on both sides of the second dielectric layer are respectively contacted with the side wall of the first trench;
and after the second dielectric layer is formed, forming an electric connection structure in the first groove, wherein the electric connection structure is electrically connected with the metallization on the top of the source-drain doping layer.
11. The method of forming a semiconductor structure of claim 10, wherein the first dielectric layer comprises: the bottom dielectric layer is positioned on the substrate and exposes out of the top surface of the grid; the top dielectric layer is positioned on the bottom dielectric layer and the grid;
the steps of forming the first dielectric layer, the gate and the source-drain doped layer include: forming a dummy gate on the substrate, the dummy gate extending from the device region to the isolation region; forming source and drain doped layers in substrate device regions on two sides of the pseudo gate, wherein the substrate is exposed out of the side walls of the source and drain doped layers; forming an initial bottom dielectric layer on the substrate and the source-drain doping layer, wherein the initial bottom dielectric layer covers the side wall of the pseudo gate; removing the pseudo grid and forming a grid opening in the initial bottom dielectric layer; forming a gate in the gate opening; forming an initial top dielectric layer on the grid and the initial bottom dielectric layer; after the grid electrode is formed, removing part of the initial top dielectric layer and part of the initial bottom dielectric layer through first imaging treatment, exposing the top and the side wall of the source-drain doping layer, enabling the initial top dielectric layer to form a top dielectric layer, enabling the initial bottom dielectric layer to form a bottom dielectric layer, and forming a first groove in the top dielectric layer and the bottom dielectric layer.
12. The method of forming a semiconductor structure of claim 11, wherein the substrate isolation region has an isolation structure therein;
the step of the first patterning process includes: forming a patterned first mask layer on the first initial dielectric layer, wherein the first mask layer is provided with a first opening, the first opening extends from the device region to the isolation region, and the first opening is positioned in the first mask layer on the source-drain doped layer; and etching the first initial dielectric layer by taking the first mask layer as a mask until the side wall of the source-drain doped layer is completely exposed.
13. The method of forming a semiconductor structure of claim 10, wherein forming the second dielectric layer comprises: forming a second initial dielectric layer in the first groove, wherein the second initial dielectric layer completely fills the first groove; and etching the second initial dielectric layer through second patterning treatment, removing part of the second initial dielectric layer, exposing the top surface of the source-drain doping layer, and forming a second dielectric layer and a second groove in the second dielectric layer of the device region.
14. The method of forming a semiconductor structure of claim 13, wherein forming the second initial dielectric layer comprises: a fluid chemical vapor deposition process, a plasma enhanced chemical vapor deposition process, or an atomic layer deposition process.
15. The method of forming a semiconductor structure of claim 13, wherein the second patterning process comprises: forming a patterned second mask layer on the second initial dielectric layer, wherein the device region second mask layer is provided with a second opening, the second opening extends from the device region to the isolation region, and the second opening is positioned in the second mask layer on the source-drain doping layer; and carrying out second etching on the second initial dielectric layer by taking the second mask layer as a mask until the metallization on the top of the source-drain doping layer is exposed.
16. The method of forming a semiconductor structure of claim 15, wherein the second etching process comprises a dry etching process.
17. The method of forming a semiconductor structure of claim 15, wherein the first trench is located only in the device region second dielectric layer; or, the first trench extends from the device region to the isolation region, and the bottom of the isolation region is provided with the second dielectric layer.
18. The method of forming a semiconductor structure of claim 15, wherein the number of the device regions is plural, the number of the isolation regions is plural, and the device regions and the isolation regions are alternately arranged; the second opening spans across a plurality of device regions and a plurality of isolation regions.
19. The method of forming a semiconductor structure of claim 10, wherein forming the metallization comprises: forming metal layers on the side wall and the top surface of the source drain doping layer exposed at the bottom of the first groove; and annealing the metal layer, and reacting the metal layer with part of the source-drain doping layer to form the metallization.
20. The method of claim 19, wherein the metal layer is made of Ti, Co, Ni, or Pt; the source-drain doped layer is made of silicon, germanium, silicon-germanium or silicon carbide.
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