CN109727976A - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN109727976A CN109727976A CN201711034035.7A CN201711034035A CN109727976A CN 109727976 A CN109727976 A CN 109727976A CN 201711034035 A CN201711034035 A CN 201711034035A CN 109727976 A CN109727976 A CN 109727976A
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Abstract
A kind of semiconductor structure and forming method thereof, wherein, the forming method includes: the first medium layer on substrate, the first medium layer covers gate lateral wall, there is first groove in the first medium layer, the first groove extends in the isolated area first medium layer from the device region, and the first groove bottom-exposed goes out at the top of the source and drain doping layer and sidewall surfaces；The metal compound of the source and drain doping layer surface gone out positioned at the first groove bottom-exposed；Second dielectric layer in the isolated area groove, the second dielectric layer expose the metal compound of the source and drain doping layer top surface.The second dielectric layer can reduce isolated area electric connection structure in the projecting figure area on the gate lateral wall surface, to the parasitic capacitance value that the first medium layer reduced between electric connection structure, grid and electric connection structure and grid is formed, and then improve the performance of formed semiconductor structure.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors more particularly to a kind of semiconductor structure and forming method thereof.
Background technique
With being constantly progressive for semiconductor technology, the characteristic size of semiconductor devices is gradually become smaller.The diminution of critical size
Mean to arrange greater number of transistor on chip, while more stringent requirements are proposed to semiconductor technology.
Since metal has good electric conductivity, in semiconductor technology, source and drain doping is realized often through metal plug
Area is electrically connected with external circuit.However, belonging to plug and source and drain since the fermi level between metal and semiconductor differs larger
Potential barrier between doped region is higher, causes the contact resistance belonged between plug and source and drain doping area larger.The prior art by
Belong to and form metal silicide between plug and source and drain doping area to reduce contact resistance, improves the performance of semiconductor structure.
However, the semiconductor structure that the prior art is formed still has the contact between metal silicide and source and drain doping area
The problem that resistance is larger or parasitic capacitance is larger.
Summary of the invention
Problems solved by the invention is to provide a kind of semiconductor structure and forming method thereof, can reduce metal silicide with
Contact resistance between source and drain doping area, while reducing parasitic capacitance.
To solve the above problems, technical solution of the present invention provides a kind of forming method of semiconductor structure, comprising: substrate,
The substrate includes adjacent device region and isolated area；Grid on the substrate, the grid prolong from the device region
Extend to the isolated area；Positioned at the source and drain doping layer of the device region of the grid two sides, institute is higher than at the top of the source and drain doping layer
State substrate surface；First medium layer on the substrate, the first medium layer covering gate lateral wall, described first
There is first groove, the first groove extends in the isolated area from the device region, the first groove in dielectric layer
Bottom-exposed goes out at the top of the source and drain doping layer and sidewall surfaces；The source and drain doping layer gone out positioned at the first groove bottom-exposed
The metal compound on surface；Second dielectric layer in the isolated area first groove, the second dielectric layer expose described
The metal compound of source and drain doping layer top surface, the second dielectric layer top are higher than the gate bottom, and perpendicular to institute
It states on gate lateral wall direction, second dielectric layer two sides side wall is contacted with the first groove side wall respectively；Positioned at described
Electric connection structure in one groove, the electric connection structure are electrically connected with the metal compound at the top of the source and drain doping layer.
Optionally, the material of the source and drain doping layer is silicon, germanium, SiGe or silicon carbide.
Optionally, the substrate includes: substrate and the fin in the device region substrate, source and drain doping layer position
In the fin or the fin portion surface；The grid covers the fin partial sidewall and top surface.
Optionally, further includes: the isolation structure in the isolated area substrate, the isolation structure cover the fin
Partial sidewall；The isolated area grid is located on the isolation structure, and the second dielectric layer is located at the isolated area isolation junction
On structure.
Optionally, the source and drain doping layer is located in the substrate, has isolation structure, institute in the isolated area of the substrate
It states gate structure to be located on the device region substrate and isolation structure, the second dielectric layer is located at the isolated area isolation structure
On.
Optionally, the first groove bottom-exposed goes out the isolation structure.
Optionally, the isolated area second medium layer surface is higher than or is flush to the source and drain doping layer surface.
Optionally, the number of the device region is multiple, and the isolated area is between adjacent devices area；The electrical connection
Structure is located in isolated area second dielectric layer and on multiple device region source and drain doping layers.
Optionally, the material of the first medium layer is silica, silicon nitride, silicon oxynitride or low k dielectric materials；It is described
The material of second dielectric layer is silica, silicon nitride, silicon oxynitride or low k dielectric materials.
Correspondingly, technical solution of the present invention also provides a kind of forming method of semiconductor structure, comprising: provide substrate, institute
Stating substrate includes: adjacent device region and isolated area；Grid, source and drain doping layer and first medium layer, the grid is formed to be located at
On the substrate, and the isolated area is extended to from the device region, the source and drain doping layer is located at the device of the grid two sides
Part area, the substrate expose the source and drain doping layer surface, and the first medium layer is located on the substrate, and described first
Dielectric layer covers the gate lateral wall, has first groove in the first medium layer, and the first groove is from the device region
First medium layer extends in the isolated area first medium layer, and the first groove bottom-exposed goes out source and drain doping layer top
Portion and sidewall surfaces；Metal compound is formed in the source and drain doping layer surface that the first groove bottom-exposed goes out；In the isolation
Second dielectric layer is formed in area's first groove, the second dielectric layer exposes the metallization of the source and drain doping layer top surface
Object, the second dielectric layer top are higher than the gate bottom, and on perpendicular to the gate lateral wall direction, described second is situated between
Matter layer two sides side wall is contacted with the first groove side wall respectively；It is formed after the second dielectric layer, in the first groove
Middle formation electric connection structure, the electric connection structure are electrically connected with the metal compound at the top of the source and drain doping layer.
Optionally, the first medium layer includes: the underlying dielectric layer on the substrate, and the underlying dielectric layer is sudden and violent
Expose the gate top surface；Top layer dielectric layer in the underlying dielectric layer and the grid；Form described first
The step of dielectric layer, grid and source and drain doping layer includes: to form dummy grid over the substrate, and the dummy grid is from the device
Area extends to the isolated area；Source and drain doping floor is formed in the substrate devices area of the dummy grid two sides, the substrate exposes
The source and drain doping layer side wall；Initial underlying dielectric layer is formed on the substrate and source and drain doping layer, the initial bottom is situated between
Matter layer covers the dummy grid side wall；The dummy grid is removed, forms gate openings in the initial underlying dielectric layer；Institute
It states and forms grid in gate openings；Initial top layer dielectric layer is formed on the grid and initial underlying dielectric layer；Described in formation
After grid, the part initial top layer dielectric layer and the initial underlying dielectric layer in part are removed by the first graphical treatment, and
The source and drain doping layer top and side wall are exposed, initial top layer dielectric layer is made to form top layer dielectric layer, initial underlying dielectric layer
It forms underlying dielectric layer and forms the first groove being located in the top layer dielectric layer and underlying dielectric layer.
Optionally, there is isolation structure in the substrate isolated area；The step of first graphical treatment includes: in institute
It states and forms patterned first mask layer on the first initial medium layer, there is the first opening in first mask layer, described the
One opening extends to isolated area from the device region, and first opening is located at the first mask layer on the source and drain doping layer
In；The first initial medium layer is performed etching using first mask layer as exposure mask, until completely revealing the source and drain
Doped layer side wall.
Optionally, the step of forming the second dielectric layer includes: that the second initial medium is formed in the first groove
Layer, the second initial medium layer are filled up completely the first groove；It is handled by second graphical to described second initial Jie
Matter layer performs etching, and removes the second initial medium of part layer, and expose the source and drain doping layer top surface, forms second and is situated between
Matter layer and the second groove in the device region second dielectric layer.
Optionally, the technique for forming the second initial medium layer includes: fluid chemistry gas-phase deposition, plasma
Enhance chemical vapor deposition process or atom layer deposition process.
Optionally, the step of second graphical is handled includes: to be formed graphically on the second initial medium layer
The second mask layer, there is the second opening, second opening extends from the device region in second mask layer of device region
To isolated area, second opening is located in the second mask layer on the source and drain doping layer；It is to cover with second mask layer
Film carries out the second etching to the second initial medium layer, until exposing the metal compound at the top of the source and drain doping layer.
Optionally, the technique of second etching includes dry etch process.
Optionally, the first groove is only located in the device region second dielectric layer；Alternatively, the first groove is from institute
It states device region and extends to the isolated area, the isolated area bottom has the second dielectric layer.
Optionally, the number of the device region is multiple, and the number of the isolated area is multiple, device region and isolated area friendship
For arrangement；Second opening is across multiple device regions and multiple isolated areas.
Optionally, the step of forming the metal compound includes: the source and drain doping gone out in the first groove bottom-exposed
Layer side wall and top surface form metal layer；The metal layer is made annealing treatment, the metal layer and part source and drain doping
Layer reaction forms the metal compound.
Optionally, the material of the metal layer is Ti, Co, Ni or Pt；The material of the source and drain doping layer is silicon, germanium, silicon
Germanium or silicon carbide.
Compared with prior art, technical solution of the present invention has the advantage that
Technical solution of the present invention provide semiconductor structure in, the metallization level in the source and drain doping layer side wall with
Top surface keeps the contact area between metal compound and source and drain doping layer larger, mixes so as to reduce metal compound with leakage
Contact resistance between diamicton.Meanwhile the electric connection structure is located in the first groove, in the isolated area first groove
Also there is second dielectric layer, and second dielectric layer two sides side wall is contacted with the first groove side wall respectively.Described second
Dielectric layer occupies the space of a part of isolated area first groove, so that it is only located at electric connection structure in device region first groove,
Or it is also located in the isolated area first groove of part.Therefore, the second dielectric layer can reduce isolated area electric connection structure and exist
The area of the projecting figure on the gate lateral wall surface, to reduce electric connection structure, grid and electric connection structure and grid
Between first medium layer formed parasitic capacitance.To sum up, the semiconductor structure can reduce the metal compound and source
While leaking contact resistance between doped layer, the parasitic capacitance is reduced, so as to improve semiconductor structure performance.
Further, the source and drain doping layer is located in the fin that the isolation structure exposes, and the first groove bottom
Portion exposes the isolation structure, then the sidewall area for the source and drain doping layer that the first medium layer exposes is larger, so as to
Enough increase the contact area of metal compound and source and drain doping layer, and then can reduce connecing between metal compound and source and drain doping layer
Electric shock resistance, improves semiconductor structure performance.
In the forming method for the semiconductor structure that technical solution of the present invention provides, the first groove bottom-exposed goes out described
Source and drain doping layer side wall and top, then the level that can make to metallize in the source and drain doping layer side wall and top surface, so as to
It enough reduces metal compound and leaks the contact resistance between doped layer.It is formed after second dielectric layer in the first groove, shape
At the electric connection structure.The second dielectric layer occupies a part of isolated area first groove space, to make electric connection structure
It is only located in device region first groove, or is also located in the isolated area first groove of part.Therefore, the second dielectric layer can
Reduce isolated area electric connection structure the gate lateral wall surface projecting figure area, thus reduce electric connection structure, grid,
And the parasitic capacitance value that the first medium layer between electric connection structure and grid is formed, and then improve formed semiconductor structure
Performance.
Further, the first etching is carried out to the first initial medium layer, until completely revealing the source and drain doping layer
Side wall can increase the contact area for the metal compound and source and drain doping layer being subsequently formed, so as to reduce metal compound with
Contact resistance between source and drain doping layer improves the performance of formed semiconductor structure.
Further, the isolated area second medium layer surface is higher than the source and drain doping layer surface, can make described second
The space for the first groove that dielectric layer occupies is larger, so that the space for the first groove for occupying the electric connection structure is smaller,
To keep electric connection structure smaller in the area of the projecting figure of the gate lateral wall, so as to reduce parasitic capacitance.
Detailed description of the invention
Fig. 1 to Fig. 3 is a kind of structural schematic diagram of each step of forming method of semiconductor structure；
Fig. 4 to Figure 20 is the structural schematic diagram of each step of one embodiment of forming method of semiconductor structure of the present invention.
Specific embodiment
There are problems for the semiconductor structure that the prior art is formed, such as: between metal silicide and source and drain doping area
Contact resistance it is larger or parasitic capacitance is larger.
Now in conjunction with a kind of forming method of semiconductor structure, the semiconductor structure metallic silicon that the forming method is formed is analyzed
The reason that contact resistance between compound and source and drain doping area is larger or parasitic capacitance is larger:
Fig. 1 to Fig. 3 is a kind of structural schematic diagram of semiconductor structure.
Fig. 1 to Fig. 3 is please referred to, Fig. 3 is sectional view of the Fig. 1 along cutting line A4-A4 ', and Fig. 1 is Fig. 3 along cutting line A3-A3 '
Sectional view, Fig. 2 is sectional view of the Fig. 3 along cutting line A2-A2 ', and the semiconductor structure includes: substrate 100, the substrate
There is fin 101 on 100；Isolation structure 102 on the substrate 100, the isolation structure 102 cover the fin
101 partial sidewalls, 102 surface of isolation structure are lower than 101 top surface of fin；Across the grid of the fin 101
111,111 covering part isolation structure of grid, 102 surface and 101 partial sidewall of the fin and top surface；It is located at
Doped layer 110 in the 111 two sides fin 101 of grid；Cover the grid 111, doped layer 110 and isolation structure 102
Dielectric layer 120；Groove in the dielectric layer 120, the channel bottom expose 110 top of doped layer and side
102 surface of wall and the isolation structure；Metal positioned at doped layer 110 top and sidewall surfaces that channel bottom exposes
Silicide 131；The electric connection structure 130 being located in the groove, the metal silicide 131 are located at the electric connection structure
Between 130 and doped layer 110.
Wherein, since the depth of the groove is larger, so that the dielectric layer 120 is exposed the doped layer 110 and push up
Portion and sidewall surfaces increase so that the metal silicide 110 is located at 110 top of doped layer and sidewall surfaces
Contact area between metal silicide 110 and doped layer 110 thereby reduces between metal silicide 131 and doped layer 110
Contact resistance.
However, the electric connection structure 130 is filled in the ditch since the groove exposes the isolation structure 102
In slot, so that the electric connection structure 130 on the isolation structure 102 is along perpendicular to the size in 100 surface direction of substrate
It is larger, it is larger in the projected area of 111 sidewall surfaces of grid so as to cause electric connection structure 130.The electric connection structure 130,
Dielectric layer 120 between grid 111 and electric connection structure 130 and grid 111 constitutes parasitic capacitance.Electric connection structure 130 exists
The projected area of 111 sidewall surfaces of grid is larger, causes the parasitic capacitance larger, to be easy to influence formed semiconductor junction
The performance of structure.
To solve the technical problem, the present invention provides a kind of forming methods of semiconductor structure, comprising: first groove
The source and drain doping layer side wall and top are exposed, then the level that can make to metallize is in the source and drain doping layer side wall and top table
Face, so as to reduce metal compound and leak the contact resistance between doped layer.In addition, having second to be situated between in the first groove
Matter layer.The second dielectric layer occupies a part of isolated area first groove space.The second dielectric layer can reduce isolated area
Electric connection structure the gate lateral wall surface projecting figure area, thus reduce electric connection structure, grid and electrical connection
The parasitic capacitance value for the capacitor that first medium layer between structure and grid is formed, and then improve formed semiconductor structure
Performance.
To make the above purposes, features and advantages of the invention more obvious and understandable, with reference to the accompanying drawing to the present invention
Specific embodiment be described in detail.
Fig. 4 to Figure 20 is the structural schematic diagram of each step of one embodiment of forming method of semiconductor structure of the present invention.
Referring to FIG. 4, providing substrate, the substrate includes adjacent device region A and isolated area B.
In the present embodiment, the substrate includes substrate 200 and the fin 201 in the substrate 200.In other implementations
In example, the substrate can also be in planar substrate, such as silicon substrate, germanium substrate, silicon-Germanium substrate, silicon-on-insulator, insulator
The semiconductor substrates such as germanium or sige-on-insulator.
The number of the device region A be it is single or multiple, the number of the isolated area B is single or multiple, the isolation
Area B is located between adjacent devices area A.In the present embodiment, the number of the device region A is two, and the number of the isolated area B is
Multiple, the isolated area B and device region A are alternately arranged.
Specifically, two device region A are respectively the first device region and the second device region in the present embodiment.
The device region A is used to form MOS transistor, and the isolated area B is for realizing the electric isolution between device region A.
Specifically, first device region is used to form PMOS transistor in the present embodiment.Second device region is used for
Form NMOS transistor.In other embodiments, first device region is used to form NMOS transistor, second device region
It is used to form PMOS transistor；Alternatively, first device region and the second device region are used to form NMOS transistor；Described
One device region and the second device region are used to form PMOS transistor.
In the present embodiment, the material of the substrate 200 and fin 201 is silicon, SiGe or germanium.
With continued reference to Fig. 4, isolation structure 202 is formed in the substrate 200, the isolation structure 202 covers the fin
201 partial sidewall of portion, 202 surface of isolation structure are lower than 201 top surface of fin.
The isolation structure 202 is also used to for realizing the electric isolution between adjacent fin 201, the isolation structure 202
Realize the electric isolution between the isolated area B grid being subsequently formed and substrate.
The material of the isolation structure 202 is silica.In other embodiments, the material of the isolation structure can be with
For silicon nitride or silicon oxynitride.
In the present embodiment, the technique for forming the isolation structure 202 includes: chemical vapor deposition process.In other implementations
In example, the technique for forming the isolation structure can also be physical gas-phase deposition or atom layer deposition process.
In other embodiments, the substrate is planar substrate, then the isolation structure is located in the isolated area substrate.
It is subsequently formed grid, source and drain doping layer and first medium layer, the grid is located on the substrate, and from the device
Part area A extends to the isolated area B, and the source and drain doping layer is located at the device region A of the grid two sides, and the substrate exposes
The source and drain doping layer surface, the first medium layer are located on the substrate, and the first medium layer covers the grid
233 side walls, have first groove in the first medium layer, and the first groove extends from the device region A first medium layer
To in the isolated area B first medium layer, 215 bottom-exposed of first groove goes out at the top of the source and drain doping layer and side wall table
Face.
In the present embodiment, the first medium layer includes: the underlying dielectric layer on the substrate, the underlying dielectric
Layer exposes the gate top surface；Top layer dielectric layer in the underlying dielectric layer and the grid.
In the present embodiment, the semiconductor structure is formed by rear grid technique.It in other embodiments, can also be by preceding
Grid technique forms the semiconductor structure.Specifically, the step of forming grid, source and drain doping layer and first medium layer such as Fig. 5 are extremely
Shown in Figure 12.
Fig. 5 and Fig. 6 are please referred to, Fig. 6 is sectional view of the Fig. 5 along cutting line C1-C1 ', forms dummy grid over the substrate
230, the dummy grid 230 extends to the isolated area B from the device region A.
The dummy grid 230 is used to provide space to be subsequently formed grid.
In the present embodiment, the dummy grid 230 is long strip type.The extending direction of the dummy grid 230 and the device region A
It is identical with the orientation of isolated area B.
In the present embodiment, the dummy grid 230 is across first device region, the second device region and multiple isolated area B.
The dummy grid 230 is located at 201 partial sidewall of fin and top surface and the isolated area part B isolation structure 202
On.
The material of the dummy grid 230 is silicon, germanium or SiGe.
The step of forming dummy grid 230 includes: the dummy gate layer for being developed across the fin 201, the dummy grid
Layer extends to isolated area B from the device region A；The dummy gate layer is patterned, the dummy grid 230 is formed.
It is formed before the dummy grid 230, further includes: it is developed across the pseudo- gate dielectric layer 232 of the fin 201, it is described
Pseudo- gate dielectric layer 232 covers 201 partial sidewall of fin and top surface.
The material of the puppet gate dielectric layer 232 is silica.
It is formed after the dummy grid 230, further includes: form side wall 231 in 230 sidewall surfaces of dummy grid.
The side wall 231 is used to prevent source and drain doping layer apart from crystal due to the position for the source and drain doping layer being subsequently formed
Pipe trench road is excessively close, so as to inhibit Punchthrough；In addition, the side wall 231 can also be in subsequent etching first medium layer
Grid is protected in the process.
The subsequent substrate devices area A in 230 two sides of dummy grid forms source and drain doping floor, and the substrate exposes described
Source and drain doping layer side wall.
In the present embodiment, the source and drain doping layer is located in the substrate.The number of the device region A is two, described
The number of source and drain doping layer is multiple, includes the first source and drain doping positioned at first device region in multiple source and drain doping layers
Layer；Positioned at the second source and drain doping layer of the second device region.
Specifically, in the present embodiment, the step of forming the source and drain doping layer, is as shown in Figure 7 to 9.
Referring to FIG. 7, forming the first source and drain doping layer 271 in the first device region substrate of 230 two sides of dummy grid.
There are the first Doped ions in the first source and drain doping layer 271.
The first source and drain doping layer 271 is used to form source region or the drain region of PMOS transistor, then described first adulterate from
Son is P-type ion, such as boron ion or BF2 +Ion.
In the present embodiment, formed the first source and drain doping layer 271 the step of include: in the first device region fin
201 side walls form the first fin side wall 241；Form the first protection for covering 201 side wall of the second device region fin and top
Layer 281；The first groove is formed in the first device region fin 201 of 233 two sides of grid, first groove is located at first
Between fin side wall 241；It is formed after first protective layer 281, forms the first source and drain doping layer in first groove
271。
First protective layer 281 is used for during forming the first source and drain doping layer 271, is prevented described the
Two device region fins, 201 surface forms 271 material of the first source and drain doping layer；The first fin side wall 241 is described for limiting
First source and drain doping layer 271 is perpendicular to the size in 201 sidewall direction of the first device region fin, to inhibit the first source
Leakage doped layer 271 is contacted with the second source and drain doping layer being subsequently formed.
In the present embodiment, forms the first protective layer 281 and the step of the first fin side wall 241 includes: to form covering first
First initial protective layers of device region fin 201 and 201 side wall of the second device region fin and top；Remove first device region
First initial protective layers at 201 top of fin form the first fin side wall 241 in 201 side wall of the first device region fin, and in institute
It states and forms the first protective layer 281 on 201 side wall of the second device region fin and top.
The material of first initial protective layers is silicon nitride, silicon oxynitride or silica.
The technique for forming first initial protective layers is furnace process, and the furnace process includes low-temperature oxidation (HTO)
Technique.
It includes silane (DCS) and NH that the technological parameter for forming first initial protective layers, which includes: reaction gas,3；Reaction
Temperature is 650 DEG C~800 DEG C.
The technique for removing first initial protective layers at 201 top of the first device region fin includes that anisotropic dry is carved
Etching technique.
It in the present embodiment, is formed after first groove, further includes: 241 side wall of the first fin side wall is carried out
First side wall etching increases by first groove along the size perpendicular to 201 side wall of the first device region fin.
First side wall etching for increasing by first groove along the size perpendicular to 201 side wall of the first device region fin,
The size for increasing the first source and drain doping layer being subsequently formed, to increase the first source and drain doping layer to formed crystal pipe trench
The stress that road provides, and then improve the performance of formed semiconductor structure.
In the present embodiment, the technique of the first side wall etching includes isotropic dry etch technique.In other implementations
In example, the technique of the first side wall etching can also be wet-etching technology.
In the present embodiment, the material of the first source and drain doping layer 271 is SiGe.SiGe can be to be formed PMOS crystal
Pipe trench road provides compression, to increase the migration rate of carrier in PMOS transistor channel.In other embodiments, described
The material of first source and drain doping layer can also be silicon.First device region is used to form NMOS transistor, then first source
The material for leaking doped layer can also be silicon carbide.
Fig. 8 and Fig. 9 are please referred to, Fig. 9 is sectional view of the Fig. 8 along cutting line B2-B2 ', the of 230 two sides of dummy grid
The second source and drain doping layer 272 is formed in two device region substrates.
There are the second Doped ions in the second source and drain doping layer 272.
The second source and drain doping layer 272 is used to form source region or the drain region of PMOS transistor, then described second adulterate from
Son is P-type ion, such as boron ion or BF2 +Ion.
In the present embodiment, formed the second source and drain doping layer 272 the step of include: in the second device region fin
201 sidewall surfaces form the second fin side wall 242；It is formed and covers the second of 201 side wall of the first device region fin and top
Protective layer 282；The second groove is formed in the second device region fin 201 of 233 two sides of grid, second groove is located at
Between second fin side wall 242；It is formed after second protective layer 282, forms the second source and drain in second groove and mix
Diamicton 272.
Second protective layer 282 is used for during forming the second source and drain doping layer 272, is prevented described the
One source and drain doping layer, 271 surface forms 272 material of the second source and drain doping layer；The second fin side wall 242 is described for limiting
Second source and drain doping layer 272 is perpendicular to the size in 201 sidewall direction of the second device region fin, to inhibit the first source
Leakage doped layer 271 is contacted with the second source and drain doping layer being subsequently formed.
In the present embodiment, forms the second protective layer 282 and the step of the second fin side wall 242 includes: to form covering second
Second initial protective layers of device region fin 201 and 201 side wall of the first device region fin and top；Remove second device region
Second initial protective layers at 201 top of fin form the second fin side wall 242 in 201 side wall of the second device region fin, and in institute
It states 201 side wall of the second device region fin and the second protective layer 282 is formed on top.
It in the present embodiment, is formed after the first fin side wall 241 and the first protective layer 281, forms second fin
Portion's side wall 242 and the second protective layer 282.Second initial protective layers cover the first fin side wall 241 and the first protection
Layer 281.In other embodiments, described the can also be formed after forming the second fin side wall and the second protective layer
One fin side wall and the first protective layer.
In the present embodiment, first device region is used to form PMOS transistor, and second device region is used to form
NMOS transistor, then first Doped ions and the second Doped ions are not identical.
It in the present embodiment, is formed after the first source and drain doping layer 271, forms the second source and drain doping layer 272.Described
Two initial protective layers cover 271 surface of the first source and drain doping layer and 281 surface of the first protective layer.In other realities
It applies in example, the first source and drain doping layer can also be formed after forming the second source and drain doping layer.
The material of second initial protective layers is silicon nitride, silicon oxynitride or silica.
The technique for forming second initial protective layers is furnace process, and the furnace process includes low-temperature oxidation (HTO)
Technique.
It includes silane (DCS) and NH that the technological parameter for forming second initial protective layers, which includes: reaction gas,3；Reaction
Temperature is 650 DEG C~800 DEG C.
The technique for removing second initial protective layers at 201 top of the second device region fin includes that anisotropic dry is carved
Etching technique.
It in the present embodiment, is formed after second groove, further includes: 242 side wall of the second fin side wall is carried out
The erosion of second side stela increases by second groove along the size perpendicular to 201 side wall of the second device region fin.
The erosion of second side stela for increasing by second groove along the size perpendicular to 201 side wall of the second device region fin,
Increase the size of the second source and drain doping layer 272, is mentioned to increase described second source and drain doping layer, 272 pairs of formed transistor channel
The stress of confession, so as to improve the performance of formed semiconductor structure.
In the present embodiment, the technique of second side stela erosion includes isotropic dry etch technique.In other implementations
In example, the technique of second side stela erosion can also be wet-etching technology.
In the present embodiment, the material of the second source and drain doping layer 272 is silicon carbide.Silicon carbide can be to be formed NMOS
Transistor channel provides tensile stress, to increase the migration rate of carrier in NMOS transistor channel.In other embodiments,
The material of the second source and drain doping layer can also be silicon.
In other embodiments, second device region is used to form PMOS transistor, then the second source and drain doping layer
Material be SiGe or silicon.
Figure 10 and Figure 11 are please referred to, Figure 10 is sectional view of the Figure 11 along cutting line B3-B3 ', is mixed in the substrate and source and drain
Initial underlying dielectric layer 210 is formed on diamicton, the initial underlying dielectric layer 210 covers 230 side wall of dummy grid, and exposure
230 top surface of dummy grid out.
The initial underlying dielectric layer 210 is for being subsequently formed underlying dielectric layer.
In the present embodiment, the material of the initial underlying dielectric layer 210 is silica.In other embodiments, described first
The material of beginning underlying dielectric layer is low-k dielectric layer, and k is less than 3.9.
The step of forming initial underlying dielectric layer 210 includes: in the substrate, source and drain doping layer and dummy grid 230
It is upper to form initial bottom dielectric film；Planarization process is carried out to initial bottom dielectric film, exposes the 230 top table of dummy grid
Face forms initial underlying dielectric layer 210.
In the present embodiment, the technique for forming the initial bottom dielectric film includes fluid chemistry gas-phase deposition.Fluid
The filling capacity for the initial bottom dielectric film that chemical vapor deposition process is formed is good, can be sufficient filling with the first source and drain doping layer
271 and the second gap between source and drain doping layer 272.In other embodiments, the technique of the initial bottom dielectric film is formed
Including plasma enhanced chemical vapor deposition technique.
The technique of the planarization process includes chemical mechanical milling tech.
Figure 12 is please referred to, the dummy grid 230 (as shown in figure 11) is removed, the shape in the initial underlying dielectric layer 210
At gate openings；Grid 233 is formed in the gate openings；It is formed on the grid 233 and initial underlying dielectric layer 210
Initial top layer dielectric layer 213.
The initial top layer dielectric layer 213 is for being subsequently formed top layer dielectric layer.
The technique for removing the dummy grid 230 includes one or both of dry etch process or wet-etching technology group
It closes.
The material of the grid 233 is metal, such as: Al, Cu, Ag, Au, Ni, Ti, W, WN or WSi.
It is formed before the grid 233, further includes: form gate dielectric layer 232 in the gate openings side wall and bottom.
The gate dielectric layer 232 is for realizing the electric isolution between grid 233 and substrate.
The material of the gate dielectric layer 232 includes high k (k is greater than 3.9) dielectric material, such as: HfO2、La2O3、HfSiON、
HfAlO2、ZrO2、Al2O3Or HfSiO4。
The material of the initial top layer dielectric layer 213 is silica or low k (k is less than 3.9) dielectric material, and the low K is situated between
Material is porous material.The low k dielectric materials include: the silica of carbon doping, the silicon carbide of N doping, fluorine silica glass,
Polyimide porous material or polyethylene porous material.
In the present embodiment, the technique for forming the initial top layer dielectric layer 213 includes chemical vapor deposition process.
Figure 13 is please referred to, is formed after the grid 233, the part initial top layer is removed by the first graphical treatment
The initial underlying dielectric layer 210 (as shown in figure 12) of dielectric layer 213 (as shown in figure 12) and part, and expose the source and drain doping
Layer top and side wall make initial top layer dielectric layer 213 form top layer dielectric layer 214, initial underlying dielectric layer 210 forms bottom and is situated between
Matter layer 211 simultaneously forms the first groove 215 being located in the top layer dielectric layer 214 and underlying dielectric layer 211.
The underlying dielectric layer 211 is for realizing the electric isolution between the electric connection structure being subsequently formed；The top layer is situated between
Matter layer 214 for realizing grid 233 and external circuit electric isolution.The top layer dielectric layer 214 and underlying dielectric layer 211 are constituted
First medium layer；The first groove 215 is for being exposed the top of the source and drain doping layer and side wall, to make subsequent
Metal compound can be formed in the source and drain doping layer side wall and top surface.
The step of first graphical treatment includes: to form patterned first on the first initial medium layer to cover
Film layer has the first opening in first mask layer, and first opening extends to isolated area B from the device region A, described
First opening is located in the first mask layer on the source and drain doping layer；It is exposure mask at the beginning of described first using first mask layer
Beginning dielectric layer carries out the first etching, until completely revealing the source and drain doping layer side wall.
First etching is carried out to the first initial medium layer, until completely revealing the source and drain doping layer side wall, energy
Increase the contact area for the metal compound 250 and source and drain doping layer being subsequently formed, enough so as to reduce metal compound 250 and source
The contact resistance between doped layer is leaked, formed semiconductor structure performance is improved.
Specifically, the source and drain doping layer is located in the fin 201 that the isolation structure 202 exposes in the present embodiment.
First etching is described so as to completely reveal the first medium layer up to exposing the isolation structure 202
Source and drain doping layer side wall.
In the present embodiment, first opening is long strip type, and first opening is across multiple device region A and isolated area B.
The first groove 215 is long strip type, and the first groove 215 runs through the first medium of multiple isolated area B and device region A
Layer.
The technique performed etching to the first initial medium layer includes: in dry etch process and wet-etching technology
One or two combination.
The material of first mask layer is photoresist.
Figure 14 and Figure 15 are please referred to, Figure 15 is sectional view of the Figure 14 along cutting line C3-C3 ', and Figure 14 is Figure 15 along cutting line
The sectional view of C5-C5 ' is formed after the first groove 215, and first protective layer 281, the first fin side wall are removed
241, second protective layer 282 and the second fin side wall 242.
Remove first protective layer 281, the first fin side wall 241, the second protective layer 282 and the second fin side wall 242
For the source and drain doping layer to be exposed.
In the present embodiment, first protective layer 281, the first fin side wall 241, the second protective layer 282 and second are removed
The technique of fin side wall 242 includes the combination of one or both of dry etch process or wet-etching technology.
Figure 16 is please referred to, forms metal compound in the source and drain doping layer surface that 215 bottom-exposed of first groove goes out
250。
The metal compound 250 is for reducing the contact electricity between the electric connection structure being subsequently formed and source and drain doping layer
Resistance.
The first groove 215 exposes the source and drain doping layer side wall and top, then metal compound 250 can be made to be located at
The source and drain doping layer side wall and top surface, so as to reduce the electricity of the contact between metal compound 250 and source and drain doping layer
Resistance.
In the present embodiment, the step of forming metal compound 250 includes: in 215 bottom and side wall of first groove
Forming metal layer on surface；The metal layer is made annealing treatment, the metal layer reacts to form institute with part source and drain doping layer
State metal compound 250.
The annealing is for making metal layer react to form the metal compound 250 with part source and drain doping layer.
The material of the metal layer is Ti, Co, Ni or Pt.
After the annealing, further includes: remove the metal layer of the first medium layer surface.
The metal layer for removing the first medium layer surface can prevent metal layer to first medium layer and be subsequently formed
The influence of second dielectric layer isolation performance.
It is subsequent that second dielectric layer, the second medium are formed in the isolated area B first groove 215 (as shown in figure 16)
Layer exposes the metal compound 250 of the source and drain doping layer top surface, is higher than the grid 233 at the top of the second dielectric layer
Bottom, and 221 both ends of the second dielectric layer are contacted with 215 side wall of first groove respectively.
In the present embodiment, there is second groove in the second dielectric layer 221, the second groove bottom-exposed goes out described
The metal compound 250 at 201 top of fin.Specifically, the step of forming the second dielectric layer and second groove such as Figure 17 and figure
Shown in 19.
Figure 17 is please referred to, forms the second initial medium layer 220 in the first groove 215 (as shown in figure 16), it is described
Second initial medium layer 220 is filled up completely the first groove 215.
The second initial medium layer 220 is for being subsequently formed second dielectric layer.
In the present embodiment, the material of the second initial medium layer 220 is silica.In other embodiments, described
The material of two initial medium layers can also be low k (k is less than 3.9) dielectric material.The low k dielectric materials include: what carbon adulterated
Silica, the silicon carbide of N doping, fluorine silica glass, polyimide porous material or polyethylene porous material.
The technique for forming the second initial medium layer 220 includes: fluid chemistry gas-phase deposition.Fluid chemistry gas phase
The clearance filling capability for the second initial medium layer 220 that depositing operation is formed is good, can be sufficient filling with the first groove 215,
So as to increase the isolation performance for the second dielectric layer being subsequently formed.In other embodiments, described second initial Jie is formed
The technique of matter layer includes plasma enhanced chemical vapor deposition technique or atom layer deposition process.
When the material of the second initial medium layer is low k dielectric materials, going back for the second initial medium layer is formed
It can be spin coating proceeding.
Figure 18 is please referred to, is handled by second graphical and the second initial medium layer 220 is performed etching, removes part
Second initial medium layer 220, and the metal compound 250 of the source and drain doping layer top surface is exposed, form second dielectric layer
221 and the second groove 222 in the second dielectric layer 221.
The second groove 222 is used for subsequent receiving electric connection structure, and 222 bottom of second groove has second medium
Layer 221, then the second dielectric layer 221 occupies a part of isolated area B first groove 215 (as shown in figure 18) space, to make
The electric connection structure being subsequently formed is only located in device region A first groove 215, or is also located at part isolated area B first groove
In 215.Therefore, the second dielectric layer 221 can reduce isolated area B electric connection structure in 233 sidewall surfaces of grid
Projecting figure area, to reduce by between electric connection structure 260, grid 233 and electric connection structure 260 and grid 233
The parasitic capacitance value for the capacitor that one dielectric layer 211 is formed, and then improve formed semiconductor structure performance.
The step of second graphical processing includes: that patterned the is formed on the second initial medium layer 220
Two mask layers, have the second opening in second mask layer of device region A, and second opening is extended to from the device region A
Isolated area B, second opening are located in the second mask layer on the source and drain doping layer；It is to cover with second mask layer
Film carries out the second etching to the second initial medium layer 220, until exposing the metal compound at the top of the source and drain doping layer
250。
In the present embodiment, the first source and drain doping layer 271 needs electric connection structure and the second source by being subsequently formed
Doped layer 272 is leaked to be electrically connected.Therefore, second opening is across isolated area B and multiple device region A, then the second groove 222
Across isolated area B and multiple device region A.Specifically, second opening extends to second device from first device region
Part area, then the second groove 222 extends to second device region from first device region.
In the present embodiment, the second groove extends to isolated area B, the isolated area B second groove from the device region A
222 bottoms have second dielectric layer 221.In other embodiments, second opening can be only located at the device region, described
Second groove is only located at the device region.
In the present embodiment, described second, which is etched to the metal compound 250 exposed at the top of the source and drain doping layer, stops.By
Be higher than 200 surface of substrate in the source and drain doping layer top surface, then after the second etching, the isolated area B isolation junction
Also there is second dielectric layer 221 on structure 202.
In the present embodiment, the technique of second etching includes dry etch process.Dry etch process has good
Line width control, can accurately control the positions and dimensions of second groove 222.
In other embodiments, the step of forming the second dielectric layer includes: by fluid chemistry gas-phase deposition
Second dielectric layer is formed in the first groove of the isolated area, the second medium layer surface is higher than the gate bottom table
Face, and the second dielectric layer exposes the metal compound at the top of the source and drain doping layer.
In the present embodiment, 221 surface of isolated area B second dielectric layer is flush to the source and drain doping layer surface.
In other embodiments, the isolated area second medium layer surface is higher than the source and drain doping layer surface, can make
The space for the first groove that the second dielectric layer occupies is larger, so that the space for occupying the electric connection structure is smaller, from
And keep electric connection structure smaller in the area of the projecting figure of the gate lateral wall, so as to reduce parasitic capacitance.
Figure 19 and Figure 20 are please referred to, Figure 20 is sectional view of the Figure 19 along cutting line B4-B4 ', forms the second dielectric layer
After 221, form electric connection structure 260 in the first groove 215 (as shown in figure 16), the electric connection structure 260 with
Metal compound 250 at the top of the source and drain doping layer is electrically connected.
The electric connection structure 260 is electrically connected for realizing source and drain doping layer and external circuit.
It should be noted that due to having second dielectric layer 221 in the first groove 215 (as shown in figure 16), it is described
Electric connection structure 260 is only located in the first groove 215 of device region A or part isolated area B.Therefore, the second dielectric layer 221
Isolated area B electric connection structure 260 can be reduced in the projecting figure area of 233 sidewall surfaces of grid, be electrically connected to reduce
The capacitor that first medium layer 211 between binding structure 260, grid 233 and electric connection structure 260 and grid 233 is formed
Parasitic capacitance value, and then improve formed semiconductor structure performance.
In the present embodiment, there is second groove 222 (as shown in figure 18) in the second dielectric layer 221, then it is described to be electrically connected
Binding structure 260 is located in the second groove 222.
The material of the electric connection structure 260 is tungsten or copper.
The technique for forming the electric connection structure 260 includes electroplating technology.
Formed before the electric connection structure 260, the forming method further include: in 222 bottom of second groove and
Sidewall surfaces form barrier layer.
The barrier layer is used to stop the atom in 260 material of electric connection structure to the first medium layer and second medium
The isolation performance of first medium layer and second dielectric layer 221 is spread and influenced in layer 221, so as to improve first medium layer and second
The isolation performance of dielectric layer 221.
The material on the barrier layer is titanium nitride or tantalum nitride.
9 and Figure 20 are continued to refer to figure 1, the embodiment of the present invention also provides a kind of semiconductor structure, comprising: substrate, the lining
Bottom includes: adjacent device region A and isolated area B；Grid 233 on the substrate, the grid 233 is from the device region
A extends to the isolated area B；Positioned at the source and drain doping layer of the device region A of 233 two sides of grid, source and drain doping layer top
Portion is higher than the substrate surface；First medium layer on the substrate, the first medium layer cover 233 side of grid
Wall, has first groove in the first medium layer, and the first groove extends to the isolated area B the from the device region A
In one dielectric layer, the first groove bottom-exposed goes out at the top of the source and drain doping layer and sidewall surfaces；Positioned at first ditch
The metal compound 250 for the source and drain doping layer surface that trench bottom exposes；Second dielectric layer in the isolated area B groove
221, the second dielectric layer 221 exposes the metal compound 250 of the source and drain doping layer top surface, the second dielectric layer
221 tops are higher than 233 bottom of grid, and on perpendicular to the gate lateral wall direction, second dielectric layer two sides side
Wall is contacted with the first groove side wall respectively；Electric connection structure 260 in the first groove, the electric connection structure
260 are electrically connected with the metal compound 250 at the top of the source and drain doping layer.
The material of the source and drain doping layer is silicon, germanium, SiGe or silicon carbide.
In the present embodiment, the substrate includes: substrate 200 and the fin 201 in the device region A substrate 200, institute
Source and drain doping layer is stated to be located in the fin 201 or 201 surface of the fin；The grid 233 covers 201 part of fin
Side wall and top surface and 200 surface of part isolated area B substrate.
The semiconductor structure further include: the isolation structure 202 in the isolated area B substrate 200, the isolation junction
Structure 202 covers 201 partial sidewall of fin；The isolated area B grid 233 is located on the isolation structure 202, and described second
Dielectric layer 221 is located on the isolated area B isolation structure 202.
In the present embodiment, the source and drain doping layer is located in the substrate, and is higher than at the top of the source and drain doping layer described
Substrate surface, has isolation structure 202 in the isolated area B of the substrate, and 233 structure 202 of grid is located at the device region A
On substrate and isolation structure 202, the second dielectric layer 221 is located on the isolated area B isolation structure 202.
In the present embodiment, the source and drain doping layer is located in the fin 201 that the isolation structure 202 exposes, and described
One channel bottom exposes the isolation structure 202.
In the present embodiment, 221 surface of isolated area B second dielectric layer is higher than or is flush to the source and drain doping layer table
Face.
In the present embodiment, the number of the device region A be it is multiple, the isolated area B is located between adjacent devices area A；Institute
Electric connection structure 260 is stated to be located on isolated area B second dielectric layer 221 and multiple device region A source and drain doping layers.In other implementations
Example in, the number of the device region be it is single, the number of the isolated area is single.
The first medium layer includes: the underlying dielectric layer on the substrate, described in the underlying dielectric layer covering
233 side wall of grid, and expose 233 top of grid；Top layer in the underlying dielectric layer and the grid 233 is situated between
Matter layer 214.
The material of the first medium layer is silica, silicon nitride, silicon oxynitride or low k dielectric materials；Described second is situated between
The material of matter layer 221 is silica, silicon nitride, silicon oxynitride or low k dielectric materials.
Although present disclosure is as above, present invention is not limited to this.Anyone skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (20)
1. a kind of semiconductor structure characterized by comprising
Substrate, the substrate include adjacent device region and isolated area；
Grid on the substrate, the grid extend to the isolated area from the device region；
Positioned at the source and drain doping layer of the device region of the grid two sides, the substrate surface is higher than at the top of the source and drain doping layer；
First medium layer on the substrate, the first medium layer cover the gate lateral wall, the first medium layer
In there is first groove, the first groove extends in the isolated area from the device region, and the first groove bottom is sudden and violent
Expose the source and drain doping layer top and sidewall surfaces；
The metal compound of the source and drain doping layer surface gone out positioned at the first groove bottom-exposed；
Second dielectric layer in the isolated area first groove, the second dielectric layer expose source and drain doping layer top
The metal compound on portion surface, the second dielectric layer top are higher than the gate bottom, and perpendicular to the gate lateral wall side
Upwards, second dielectric layer two sides side wall is contacted with the first groove side wall respectively；
Metallization at the top of electric connection structure in the first groove, the electric connection structure and the source and drain doping layer
Object electrical connection.
2. semiconductor structure as described in claim 1, which is characterized in that the material of the source and drain doping layer is silicon, germanium, SiGe
Or silicon carbide.
3. semiconductor structure as described in claim 1, which is characterized in that the substrate include: substrate and be located at the device
Fin in area's substrate, the source and drain doping layer is located in the fin or the fin portion surface；The grid covers the fin
Portion's partial sidewall and top surface.
4. semiconductor structure as claimed in claim 3, which is characterized in that further include: in the isolated area substrate every
From structure, the isolation structure covers the fin partial sidewall；The isolated area grid is located on the isolation structure, described
Second dielectric layer is located on the isolated area isolation structure.
5. semiconductor structure as described in claim 1, which is characterized in that the source and drain doping layer is located in the substrate, institute
Stating has isolation structure in the isolated area of substrate, the gate structure is located on the device region substrate and isolation structure, described
Second dielectric layer is located on the isolated area isolation structure.
6. semiconductor structure as claimed in claim 3 or 5, which is characterized in that the first groove bottom-exposed go out it is described every
From structure.
7. semiconductor structure as described in claim 1, which is characterized in that the isolated area second medium layer surface is higher than or together
It puts down in the source and drain doping layer surface.
8. semiconductor structure as described in claim 1, which is characterized in that the number of the device region is multiple, the isolation
Area is between adjacent devices area；The electric connection structure is located in isolated area second dielectric layer and multiple device region source and drain are mixed
On diamicton.
9. semiconductor structure as described in claim 1, which is characterized in that the material of the first medium layer is silica, nitrogen
SiClx, silicon oxynitride or low k dielectric materials；The material of the second dielectric layer is silica, silicon nitride, silicon oxynitride or low k
Dielectric material.
10. a kind of forming method of semiconductor structure characterized by comprising
Substrate is provided, the substrate includes: adjacent device region and isolated area；
It forms grid, source and drain doping layer and first medium layer, the grid to be located on the substrate, and extends from the device region
To the isolated area, the source and drain doping layer is located at the device region of the grid two sides, and the substrate exposes the source and drain and mixes
Diamicton surface, the first medium layer are located on the substrate, and the first medium layer covers the gate lateral wall, and described the
There is first groove, the first groove extends to the isolated area first from the device region first medium layer in one dielectric layer
In dielectric layer, the first groove bottom-exposed goes out at the top of the source and drain doping layer and sidewall surfaces；
Metal compound is formed in the source and drain doping layer surface that the first groove bottom-exposed goes out；
Second dielectric layer is formed in the isolated area first groove, the second dielectric layer exposes source and drain doping layer top
The metal compound on portion surface, the second dielectric layer top are higher than the gate bottom, and perpendicular to the gate lateral wall side
Upwards, second dielectric layer two sides side wall is contacted with the first groove side wall respectively；
It is formed after the second dielectric layer, forms electric connection structure, the electric connection structure and institute in the first groove
State the metal compound electrical connection at the top of source and drain doping layer.
11. the forming method of semiconductor structure as claimed in claim 10, which is characterized in that the first medium layer includes:
Underlying dielectric layer on the substrate, the underlying dielectric layer expose the gate top surface；Positioned at the bottom
Top layer dielectric layer on dielectric layer and the grid；
The step of forming the first medium layer, grid and source and drain doping layer includes: to form dummy grid over the substrate, described
Dummy grid extends to the isolated area from the device region；Source and drain doping is formed in the substrate devices area of the dummy grid two sides
Layer, the substrate expose the source and drain doping layer side wall；Initial underlying dielectric is formed on the substrate and source and drain doping layer
Layer, the initial underlying dielectric layer cover the dummy grid side wall；The dummy grid is removed, in the initial underlying dielectric layer
Form gate openings；Grid is formed in the gate openings；Initial top is formed on the grid and initial underlying dielectric layer
Layer dielectric layer；It is formed after the grid, the part initial top layer dielectric layer and part is removed by the first graphical treatment
Initial underlying dielectric layer, and the source and drain doping layer top and side wall are exposed, so that initial top layer dielectric layer is formed top layer medium
Layer, initial underlying dielectric layer form underlying dielectric layer and form first be located in the top layer dielectric layer and underlying dielectric layer
Groove.
12. the forming method of semiconductor structure as claimed in claim 11, which is characterized in that have in the substrate isolated area
Isolation structure；
The step of first graphical treatment includes: that patterned first exposure mask is formed on the first initial medium layer
Layer, has the first opening in first mask layer, and first opening extends to isolated area from the device region, and described first
Opening is located in the first mask layer on the source and drain doping layer；
The first initial medium layer is performed etching using first mask layer as exposure mask, until completely revealing the source and drain
Doped layer side wall.
13. the forming method of semiconductor structure as claimed in claim 10, which is characterized in that form the second dielectric layer
Step includes: that the second initial medium layer is formed in the first groove, and the second initial medium layer is filled up completely described
One groove；It is handled by second graphical and the second initial medium layer is performed etching, remove the second initial medium of part layer,
And expose the source and drain doping layer top surface, formed second dielectric layer and in the device region second dielectric layer the
Two grooves.
14. the forming method of semiconductor structure as claimed in claim 13, which is characterized in that form second initial medium
The technique of layer includes: fluid chemistry gas-phase deposition, plasma enhanced chemical vapor deposition technique or atomic layer deposition work
Skill.
15. the forming method of semiconductor structure as claimed in claim 13, which is characterized in that the second graphical processing
Step includes: that patterned second mask layer is formed on the second initial medium layer, in second mask layer of device region
With the second opening, second opening extends to isolated area from the device region, and second opening is located at the source and drain and mixes
In the second mask layer on diamicton；Using second mask layer as exposure mask, the second etching is carried out to the second initial medium layer,
Until exposing the metal compound at the top of the source and drain doping layer.
16. the forming method of semiconductor structure as claimed in claim 15, which is characterized in that the technique packet of second etching
Include dry etch process.
17. the forming method of semiconductor structure as claimed in claim 15, which is characterized in that the first groove is only located at institute
It states in device region second dielectric layer；Alternatively, the first groove extends to the isolated area, the isolated area from the device region
Bottom has the second dielectric layer.
18. the forming method of semiconductor structure as claimed in claim 15, which is characterized in that the number of the device region is more
It is a, the number of the isolated area be it is multiple, device region and isolated area are alternately arranged；Second opening across multiple device regions and
Multiple isolated areas.
19. the forming method of semiconductor structure as claimed in claim 10, which is characterized in that form the step of the metal compound
It suddenly include: the source and drain doping layer side wall and top surface formation metal layer gone out in the first groove bottom-exposed；To the gold
Belong to layer to be made annealing treatment, the metal layer reacts to form the metal compound with part source and drain doping layer.
20. the forming method of semiconductor structure as claimed in claim 19, which is characterized in that the material of the metal layer is
Ti, Co, Ni or Pt；The material of the source and drain doping layer is silicon, germanium, SiGe or silicon carbide.
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