CN109285888B - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

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Publication number
CN109285888B
CN109285888B CN201710596408.3A CN201710596408A CN109285888B CN 109285888 B CN109285888 B CN 109285888B CN 201710596408 A CN201710596408 A CN 201710596408A CN 109285888 B CN109285888 B CN 109285888B
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fin
forming
substrate
source
dummy
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CN109285888A (en
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周飞
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/6681—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET using dummy structures having essentially the same shape as the semiconductor body, e.g. to provide stability
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A semiconductor structure and a method of forming the same, wherein the method comprises: providing a substrate, wherein the substrate comprises a second area and first areas respectively positioned at two sides of the second area, the first areas are connected with the second area, the substrate is provided with a fin part structure extending from the second area to the first areas at two sides, and the fin part structure comprises at least one fin part; forming pseudo fin parts on the first region substrate on two sides of the fin part structure, wherein the pseudo fin parts and the fin parts are arranged in parallel along the extending direction vertical to the fin parts; forming a grid structure crossing the fin part structure on the second region substrate; forming source and drain doped regions in the fin part structure and the dummy fin part on two sides of the grid structure, wherein the source and drain doped regions in the fin part structure are connected with the source and drain doped regions in the dummy fin part; forming a dielectric layer covering the side wall of the grid structure on the substrate and the source drain doped region; and forming a contact hole in the dielectric layer, wherein the bottom of the contact hole is exposed out of the top surface of the source-drain doped region. The contact resistance of the device formed by the method is small.

Description

Semiconductor structure and forming method thereof
Technical Field
The present invention relates to the field of semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.
Background
With the continuous development of semiconductor technology, the size of semiconductor devices is continuously decreasing. As the size of semiconductor devices is reduced, the contact resistance of MOS transistors has an increasing impact on the performance of MOS transistors and the entire semiconductor chip.
In order to improve the performance of the semiconductor chip, it is necessary to reduce the contact resistance of the MOS transistor. In the contact resistance of the MOS transistor, the contact resistance between the source electrode and the drain electrode is large due to the small areas of the source electrode and the drain electrode, so that the performance of the MOS transistor is greatly influenced, and the running speed of a semiconductor device is greatly reduced.
Disclosure of Invention
The invention provides a method for forming a semiconductor structure to improve the performance of a semiconductor device.
To solve the above technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein the substrate comprises a second area and first areas respectively positioned at two sides of the second area, the first areas are connected with the second area, the substrate is provided with a fin part structure extending from the second area to the first areas at two sides, and the fin part structure comprises at least one fin part; forming pseudo fin parts on the first region substrate on two sides of the fin part structure, wherein the pseudo fin parts and the fin parts are arranged in parallel along the extending direction vertical to the fin parts; forming a gate structure crossing the fin structure on the second region substrate; forming source and drain doped regions in the fin part structure and the dummy fin part on two sides of the grid structure respectively, wherein the source and drain doped regions in the fin part structure are connected with the source and drain doped regions in the dummy fin part; forming a dielectric layer covering the side wall of the grid structure on the substrate and the source drain doping region; and forming a contact hole in the dielectric layer, wherein the bottom of the contact hole is exposed out of the top surface of the source-drain doped region.
Optionally, the forming of the dummy fin portion includes: forming initial pseudo fin portions on the substrate on two sides of the fin portion structure, wherein the initial pseudo fin portions and the fin portions are arranged in parallel along the extending direction perpendicular to the fin portions; and removing the initial pseudo fin part on the second region substrate, and forming the pseudo fin part on the first region substrate.
Optionally, the process of removing the initial dummy fin portion on the second region substrate includes: anisotropic dry etching process; the parameters of the anisotropic dry etching process comprise: the flow rate of the oxygen is 50 standard ml/min-300 standard ml/min, CH3The flow rate of F is 100-500 standard ml/min, the flow rate of helium is 30-200 standard ml/min, the temperature is 25-80 ℃, and the time is 5-100 seconds.
Optionally, the minimum distance from the dummy fin portion to the fin portion structure along the extending direction perpendicular to the fin portion is 25 nm to 100 nm.
Optionally, along a direction perpendicular to the extending direction of the fin portion, the dimension of the dummy fin portion is: 5 to 15 nanometers.
Optionally, in a direction perpendicular to the extending direction of the fin portion, the dimension of the fin portion is: 5 to 15 nanometers.
Optionally, the number of the fin portions is: 1 to 40.
Optionally, when the number of the fin portions is greater than 1, more than two fin portions are arranged in parallel along a direction perpendicular to the extending direction of the fin portions; the distance between adjacent fins is: 20 to 50 nanometers.
Optionally, the forming step of the source-drain doped region includes: forming openings in the dummy fin portion and the fin portion structure on two sides of the gate structure respectively; forming an epitaxial layer in the opening; doping ions into the epitaxial layer to form a source-drain doped region.
Optionally, in a direction perpendicular to the extending direction of the fin portion, the size of the opening is: 80 to 1000 nanometers.
Optionally, the step of forming the opening includes: forming a pattern layer on the substrate, wherein the top surface of the pattern layer is exposed out of the top surfaces of the dummy fin portion and the fin portion structure; etching the pseudo fin part and the fin part structure by taking the pattern layer as a mask to form the opening; the process for etching the pseudo fin portion and the fin portion structure comprises the following steps: an anisotropic dry etching process; the parameters of the anisotropic dry etching process comprise: CH (CH)4The flow rate of (1) is 8-500 standard ml/min, CHF3The flow rate of the gas is 30-200 standard ml/min, the radio frequency power is 100-1300W, the bias voltage is 80-500V, the pressure of the chamber is 10-2000 mTorr, and the time is 4-500 seconds.
Optionally, after forming the contact hole, the method further includes: forming a metal silicide layer at the bottom of the contact hole; and forming a conductive plug on the metal silicide layer.
Optionally, the material of the metal silicide layer includes: a silicon-titanium compound; the conductive plug is made of metal, and the metal comprises: tungsten.
Optionally, the substrate further includes an isolation layer, and a top surface of the isolation layer is lower than a top surface of the fin and covers a portion of the sidewall of the fin.
The present invention also provides a semiconductor structure comprising: the substrate comprises a second area and first areas respectively positioned at two sides of the second area, the first areas are connected with the second area, the substrate is provided with a fin portion structure extending from the second area to the first areas at two sides, and the fin portion structure comprises at least one fin portion; the dummy fin parts are positioned on the first region substrate on two sides of the fin part structure and are arranged in parallel with the fin parts along the extending direction vertical to the fin parts; a gate structure located on the second region substrate and crossing the fin structure; the source drain doped region is positioned in the fin part structure and connected with the source drain doped region in the pseudo fin part; the dielectric layer is positioned on the substrate and the source-drain doped region and covers the side wall of the grid structure; and the contact hole is positioned in the medium layer, and the bottom of the contact hole is exposed out of the top surface of the source-drain doped region.
Optionally, the size of the contact hole is 80 nm to 1000 nm in the extending direction perpendicular to the fin portion.
Optionally, in a direction perpendicular to the extending direction of the fin portion, the minimum distance from the dummy fin portion to the fin portion structure is: 25-100 nm; along the extending direction perpendicular to the fin portion, the dimension of the dummy fin portion is: 5 to 15 nanometers.
Optionally, the number of the fin portions is: 1 to 40.
Optionally, when the number of the fin portions is greater than 1, more than two fin portions are arranged in parallel along a direction perpendicular to the extending direction of the fin portions; the distance between adjacent fins is: 20 to 50 nanometers.
Optionally, the method further includes: a metal silicide layer at the bottom of the contact hole; a plug located on the metal silicide layer; the material of the metal silicide layer comprises: a silicon-titanium compound; the material of the conductive plug is metal, and the metal comprises: tungsten.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
in the method for forming the semiconductor structure, provided by the technical scheme of the invention, the dummy fin parts are formed on the first region substrate on two sides of the fin part structure, and the dummy fin parts and the fin parts are arranged in parallel along the extending direction vertical to the fin parts, so that the source and drain doped regions are formed in the fin part structure and the source and drain doped regions are formed in the dummy fin parts, and the size of the source and drain doped regions is larger than that of the source and drain doped regions formed in the fin part structure along the extending direction vertical to the fin parts. And forming the contact hole in the dielectric layer subsequently, wherein the bottom of the contact hole is exposed out of the top surface of the source-drain doped region, so that the contact hole has a larger dimension in the extending direction perpendicular to the fin portion, the contact area between a conductive plug formed in the contact hole subsequently and the source-drain doped region is larger, and the reduction of the contact resistance between the conductive plug and the source-drain doped region is facilitated.
Drawings
FIGS. 1-3 are schematic structural diagrams illustrating steps of a method for forming a semiconductor structure;
fig. 4 to 21 are schematic structural diagrams of steps of a method for forming a semiconductor structure according to an embodiment of the present invention.
Detailed Description
As described in the background, the performance of the semiconductor device is poor.
Fig. 1 to fig. 3 are schematic structural diagrams of a method for forming a semiconductor structure.
Referring to fig. 1 and fig. 2, wherein fig. 1 is a schematic cross-sectional view taken along line AA1 of fig. 2, and fig. 2 is a schematic cross-sectional view taken along line BB1 of fig. 1, a substrate 100 is provided, the substrate 100 has a fin structure 101 thereon, and the fin structure 101 includes at least one fin 110; forming a gate structure 102 crossing the fin structure 101; forming source-drain doped regions 103 in the fin portions 110 on two sides of the gate structure 102; forming a dielectric layer 104 covering the side wall of the gate structure 102 on the substrate 100 and the source-drain doped region 103; forming a contact hole (not shown) in the dielectric layer 104, wherein the contact hole exposes the top surface of the source/drain doped region 103; conductive plugs 105 are formed within the contact holes.
In the above method, the fin structure 101 includes at least one fin 110. When the fin structure 101 includes: when there are two or more fins 110, the two or more fins 110 are arranged in parallel along a direction perpendicular to the extending direction of the fins 110.
However, as the integration of semiconductor devices increases, the dimension of the fin 110 in a direction perpendicular to the extending direction of the fin 110 is decreasing. Moreover, if the fin structure 101 includes: when there are two or more fins 110, the distance between adjacent fins 110 is also continuously decreased, so that the dimension of the source/drain doped region 103 along the direction parallel to the surface of the substrate 100 and perpendicular to the extending direction of the fins 110 is also continuously decreased. The contact hole is formed in the dielectric layer 104, and the bottom of the contact hole is exposed out of the top surface of the source/drain doped region 103, so that the dimension of the contact hole in the extending direction parallel to the surface of the substrate 100 and perpendicular to the fin 110 is continuously reduced, the contact area between the conductive plug 105 formed in the contact hole and the source/drain doped region 103 is smaller, and the contact resistance between the conductive plug 105 and the source/drain doped region 103 is larger.
The method for reducing the contact resistance of the conductive plug 105 and the source-drain impurity region 103 comprises the following steps: the contact area of the conductive plug 105 and the source-drain doped region 103 is increased. Specifically, the dimension of the contact hole along the direction parallel to the surface of the substrate 100 and perpendicular to the extending direction of the fin 110 is increased, specifically referring to fig. 3, fig. 1 is a schematic cross-sectional view taken along line CC1 of fig. 3, and fig. 3 is a schematic cross-sectional view taken along line BB1 of fig. 1.
Due to the improvement of the integration level of the semiconductor device, the side walls of the source and drain doped regions 103 formed in the adjacent fins 110 are connected, so that the side wall of the fin 110 located in the middle of the fin structure 101 is not exposed due to the blocking of the source and drain doped regions 103 when a contact hole is formed in the dielectric layer 104 in the following step. The sidewall of the fin 110 located at the outermost side of the fin structure 101 is exposed due to the blocking of the source/drain-free doped region 103. Before forming the conductive plug 105 in the contact hole subsequently, the method further includes: and forming a metal silicide layer in the contact hole. The exposed sidewalls of the outermost fins 110 of the fin structure 101 are also metallized during the formation of the metal silicide layer, so that the metallized fins 110 are also biased during the subsequent biasing of the plug 105. Since the source-drain doped region 103 and the well region in the substrate 100 have opposite conductivity types, the PN junction between the source-drain doped region 103 and the well region is easily conducted or broken down under the influence of the bias voltage, so that leakage is easily generated at the exposed sidewall of the fin portion 110, which is not favorable for improving the performance of the semiconductor device.
To solve the above technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: the substrate comprises a second area and first areas respectively positioned at two sides of the second area, and the fin part structure is arranged on the substrate; forming pseudo fin parts on the first region substrate on two sides of the fin part structure, wherein the pseudo fin parts and the fin parts are arranged in parallel along the extending direction vertical to the fin parts; and forming the source drain doped region in the fin part structure and the dummy fin part on two sides of the grid electrode structure. The method can reduce the contact resistance between the source-drain doped region and the subsequently formed conductive plug.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 4 to 21 are schematic structural diagrams of steps of a method for forming a semiconductor structure according to an embodiment of the present invention.
Referring to fig. 4 and 5, fig. 5 is a top view of fig. 4, fig. 4 is a schematic cross-sectional view taken along line DD1 of fig. 5, providing a substrate 200, where the substrate 200 includes a second region B and first regions a respectively located at two sides of the second region B, the first regions a are connected to the second region B, the substrate 200 has a fin structure 230 extending from the second region B to the first regions a at two sides, and the fin structure 230 includes at least one fin 201.
The steps of forming the substrate 200 and the fin structure 230 include: providing an initial substrate; the initial substrate is patterned to form a base 200 and a fin structure 230 on the base 200.
In this embodiment, the material of the initial substrate is silicon germanium. In other embodiments, the initial substrate may also be a semiconductor substrate such as a germanium substrate, a silicon-on-insulator or a germanium-on-insulator.
The number of fins 101 in the fin structure 230 may be set according to actual process requirements. In this embodiment, the number of the fin portions 201 is: 1-40, more than two of the fin portions 201 are arranged along a direction perpendicular to the extending direction of the fin portions 201. In other embodiments, the number of fins may be greater than 40.
In the present embodiment, taking the fin structure 230 as an example and including two fins 201, the two fins 201 are arranged in parallel along a direction perpendicular to the extending direction of the fins 201. The extending direction of the fin 201 is the long side direction (X direction) of the fin 201.
The spacing between adjacent fins 201 is: 20 to 50 nanometers.
In a direction perpendicular to the extending direction (Y direction) of the fin 201, the dimensions of the fin 201 are: 5 to 15 nanometers.
The dimension of fin structure 230 in a direction perpendicular to the extension direction (Y-direction) of fin 201 is determined by the dimension of the fin, the pitch between adjacent fins, and the number of fins.
In a direction perpendicular to the extending direction (Y direction) of the fin 201, the size of the fin structure 230, the size of the subsequently formed dummy fin, and the minimum distance between the dummy fin and the fin structure 230 determine the size of the subsequently formed source/drain doped region.
In this embodiment, after the substrate 200 and the fin structure 230 are formed, initial dummy fin portions 202 are formed on the substrate 200 at two sides of the fin structure 230, and the initial dummy fin portions 202 and the fin portions 201 are arranged in parallel along a direction (Y direction) perpendicular to the extending direction of the fin portions 201. Specifically, the arrangement direction of the fin portion 201 and the initial dummy fin portion 202 is a connection line direction (Y direction) between the center of the fin portion 201 and the center of the initial dummy fin portion 202.
The initial dummy fin portion 202 extends from the second region B substrate 200 to the first region a substrates 200 at both sides.
The material of the initial dummy fin 202 includes: silicon.
The initial dummy fin portions 202 on the first region a substrate 200 are used for subsequent dummy fin portions.
In a direction perpendicular to the extending direction (Y direction) of the fin 201, the dimension of the initial dummy fin 202 is: 5 to 15 nanometers.
The initial dummy fin portions 202 and the fin portions 201 are arranged in parallel along a direction (Y direction) perpendicular to the extending direction of the fin portions 201. In a direction perpendicular to the extending direction (Y direction) of the fin 201, the minimum distance b from the initial dummy fin 202 to the fin structure 230 is: 25 to 100 nanometers. The minimum distance b from the initial dummy fin 202 to the fin structure 230 refers to: a distance from a sidewall of the initial dummy fin 202 near the fin structure 230 to a sidewall of the fin structure 230 near the initial dummy fin 202 in a direction perpendicular to an extension direction (Y direction) of the fin 201.
The minimum distance b from the initial dummy fin 202 to the fin structure 230 in a direction perpendicular to the extension direction (Y direction) of the fin 201 determines the minimum distance b from a subsequently formed dummy fin to the fin structure 230.
In other embodiments, the base, fin structure and initial dummy fin are formed simultaneously. The forming steps of the substrate, the fin structure and the initial dummy fin include: providing an initial substrate; and patterning the initial substrate to form the substrate, and a fin portion structure and an initial pseudo fin portion which are located on the substrate.
Referring to fig. 6 and 7, fig. 6 is a top view of fig. 7, fig. 7 is a schematic cross-sectional view of fig. 6 taken along line EE1, the initial dummy fin portion 202 on the substrate 200 in the second region B is removed, the dummy fin portion 204 is formed on the substrate 200 in the first region a, and the dummy fin portion 204 and the fin portion 201 are arranged in parallel along a direction (Y direction) perpendicular to the extending direction of the fin portion 201.
The process of removing the initial dummy fin 202 on the second region B substrate 200 includes: an anisotropic dry etching process; the parameters of the anisotropic dry etching process comprise: the flow rate of oxygen is 50 standard ml/min-300 standard ml/min, CH3F flow rate of 100Quasi-ml/min-500 standard ml/min, helium flow of 30 standard ml/min-200 standard ml/min, temperature of 25-80 deg.c and time of 5-100 sec.
The dimension of the dummy fin portion 204 in the direction perpendicular to the extending direction (Y direction) of the fin portion 201 is determined by the dimension of the initial dummy fin portion 202, and therefore the dimension of the dummy fin portion 204 in the direction perpendicular to the extending direction (Y direction) of the fin portion 201 is: 5 to 15 nanometers.
The dimensions of the dummy fins 204 in a direction perpendicular to the extension direction (Y-direction) of the fins 201 are chosen in the sense that: if the dimension of the dummy fin portion 204 in the direction perpendicular to the extending direction of the fin portion 201 is smaller than 5 nm, the dimension of the subsequently formed contact hole is smaller, which is not beneficial to increasing the contact area between the conductive plug and the source drain doped region which are subsequently formed in the contact hole, so that the contact resistance between the conductive plug and the source drain doped region is larger; if the dimension of the dummy fin 204 in the direction perpendicular to the extending direction of the fin 201 is greater than 15 nm, it is not favorable to improve the integration of the semiconductor device.
The dummy fin portion 204 and the fin portion 201 are arranged in parallel along a direction (Y direction) perpendicular to the extending direction of the fin portion 201. The minimum distance b from the dummy fin 204 to the fin structure 230 in the direction perpendicular to the extension direction of the fin 201 (Y direction) is determined by the minimum distance b from the initial dummy fin 202 to the fin structure 230, and therefore the minimum distance b from the dummy fin 204 to the fin structure 230 in the direction perpendicular to the extension direction of the fin 201 (Y direction) is: 25 to 100 nanometers.
The minimum distance b from the dummy fin 204 to the fin structure 230 in a direction perpendicular to the extension direction (Y-direction) of the fin 201 is: 25 nm to 100 nm, the minimum distance b from the dummy fin 204 to the fin structure 230 in the direction perpendicular to the extension direction of the fin 201 is selected to be: if the minimum distance b from the dummy fin portion 204 to the fin portion structure 230 along the extending direction (Y direction) perpendicular to the fin portion 201 is less than 25 nm, the size of the contact hole formed subsequently is small, which is not beneficial to increasing the contact area between the conductive plug formed subsequently in the contact hole and the source/drain doped region, and the contact resistance between the conductive plug and the source/drain doped region is large; if the minimum distance b from the dummy fin 204 to the fin structure 230 along the direction perpendicular to the extending direction (Y direction) of the fin 201 is greater than 100 nm, it is not favorable to improve the integration level of the semiconductor device.
Referring to fig. 8, an oxide layer 206 is formed on the substrate 200 and on the sidewalls and top surfaces of the fin structure 230 and the dummy fins 204.
Fig. 8 is a schematic cross-sectional view of the structure in the cross-sectional direction of fig. 7.
The material of the oxide layer 206 includes: silicon oxide.
The formation process of the oxide layer 206 includes: chemical vapor deposition process.
The oxide layer 206 protects the surface of the substrate 200, and the sidewalls and top surfaces of the fin structure 230 and the dummy fins 204 when a layer of isolation material is subsequently formed.
Referring to fig. 9, an isolation material layer 207 is formed on the oxide layer 206, and a top surface of the isolation material layer 207 exposes the fin structure 230 and the oxide layer 206 on the top surface of the dummy fin 204.
The isolation material layer 207 is used for the subsequent formation of isolation layers.
In this embodiment, the material of the isolation material layer 207 is silicon oxide. In other embodiments, the material of the isolation material layer comprises: silicon oxynitride.
The step of forming the isolation material layer 207 includes: forming a barrier material film on the oxide layer 206; the film of isolation material is planarized until the oxide layer 206 on the top surfaces of the fin structures 230 and the dummy fins 204 is exposed, forming a layer of isolation material 207.
The forming process of the isolating material film comprises the following steps: a fluid chemical vapor deposition process.
The isolation material film formed by the fluid chemical vapor deposition process has a strong filling capability for the fin structure 230 and the gap between the fin structure 230 and the dummy fin 204, and the formed isolation material layer 207 has a good performance for isolating different devices of the semiconductor.
In the process of forming the isolation material film, the oxide layer 206 can protect the surface of the substrate 200, and the sidewalls and the top surfaces of the fin structure 230 and the dummy fin 204, so that the surface of the substrate 200, and the sidewalls and the top surfaces of the fin structure 230 and the dummy fin 204 are less damaged, which is beneficial to improving the performance of the semiconductor device.
The process of planarizing the film of isolation material includes: and (5) carrying out a chemical mechanical polishing process.
Referring to fig. 10 and 11, fig. 11 is a cross-sectional view taken along line FF1 of fig. 10, in which a portion of the isolation material layer 207 is removed to form an isolation layer 208, a top surface of the isolation layer 208 is lower than top surfaces of the fin structure 230 and the dummy fin 204, and covers a portion of sidewalls of the fin structure 230 and the dummy fin 204.
The formation process of the isolation layer 208 includes: wet etching process; the parameters of the wet etching process comprise: the etching agent comprises hydrofluoric acid solution, and the mass percentage concentration of the etching agent is 0.1-1%.
During the formation of the isolation layer 208, the oxide layer 206 on the sidewalls and the top surface of the fin structure 230 and the dummy fin 204 is also removed, exposing the sidewalls and the top surface of the fin structure 230 and the dummy fin 204.
After the isolation layer 208 is formed, a gate structure crossing the fin structure 230 is formed on the second region B substrate 200. The gate structure includes: the gate structure comprises a gate dielectric layer and a gate electrode layer positioned on the gate dielectric layer. In this embodiment, the gate dielectric layer is made of a high-K dielectric material, the dielectric constant of the high-K dielectric material is greater than 3.9, and the gate layer is made of a metal. The gate structure is formed by a gate last process, specifically referring to fig. 12 to 18. In other embodiments, the material of the gate dielectric layer includes: silicon oxide, the material of the gate layer comprises: silicon.
Referring to fig. 12 and 13, fig. 12 is a cross-sectional view taken along line GG1 in fig. 13, and fig. 13 is a top view of fig. 12. after forming the isolation layer 208, a dummy gate structure 209 crossing the fin structure 230 is formed on the substrate in the second region B.
The dummy gate structure 209 includes: a dummy gate dielectric layer (not shown) on a portion of the sidewalls and top surface of the fin structure 230, and a dummy gate layer (not shown) on the dummy gate dielectric layer.
The material of the pseudo gate dielectric layer comprises: silicon oxide. The material of the dummy gate layer comprises: silicon.
Source and drain doped regions are formed in the fin structure 230, the first dummy fin 204 and the second dummy fin 205 on two sides of the dummy gate structure 209.
Referring to fig. 14 and 15, fig. 14 is a schematic cross-sectional view taken along line HH1 of fig. 15, and source/drain doped regions 210 are formed in the dummy fin 204 and the fin structure 230 on both sides of the dummy gate structure 209.
The forming step of the source-drain doped region 210 includes: forming openings in the dummy fin portion 204 and the fin portion structure 230 on two sides of the dummy gate structure 209; forming an epitaxial layer in the opening; doping ions into the epitaxial layer to form a source/drain doped region 210.
The forming of the opening includes: forming a pattern layer on the substrate 200, wherein the top surface of the pattern layer exposes the top surfaces of the dummy fin 204 and the fin structure 230; and etching the dummy fin portion 204 and the fin portion structure 230 by using the pattern layer as a mask to form the opening.
The patterned material comprises: silicon nitride.
The process for etching the dummy fin 204 and the fin structure 230 includes: anisotropic dry etching process; the parameters of the anisotropic dry etching process comprise: CH (CH)4The flow rate of (1) is 8-500 standard ml/min, CHF3The flow rate of the gas is 30-200 standard ml/min, the radio frequency power is 100-1300W, the bias voltage is 80-500V, the pressure of the chamber is 10-2000 mTorr, and the time is 4-500 seconds.
The dimension of the opening along the extending direction (Y direction) parallel to the surface of the substrate 200 and perpendicular to the fin 201 is: 80 nm to 1000 nm, the dimensions of the opening in a direction perpendicular to the extension direction (Y direction) of the fin 201 being chosen in the sense that: if the dimension of the opening in the extending direction (Y direction) parallel to the surface of the substrate 200 and perpendicular to the fin 201 is less than 80 nm, the dimension of the formed source/drain doped region 210 in the extending direction (Y direction) perpendicular to the fin 201 is smaller, so that the dimension of a contact hole formed in a dielectric layer on the source/drain doped region 210 in the extending direction (Y direction) perpendicular to the fin 201 is smaller, the contact area between a conductive plug in the contact hole and the source/drain doped region 210 is smaller, and the contact resistance between the conductive plug and the source/drain doped region 210 is larger; if the dimension of the opening along the extending direction (Y direction) parallel to the surface of the substrate 200 and perpendicular to the fin 201 is greater than 1000 nm, it is not favorable to improve the integration of the semiconductor device.
The material and the doping ions of the epitaxial layer are both related to the type of the transistor, and if the transistor is a PMOS transistor, the material of the epitaxial layer is as follows: silicon germanium or silicon, the doping ions being: p-type ions, such as: boron ions. If the transistor is an NMOS transistor, the epitaxial layer is made of silicon carbide or silicon, and the doping ions are: n-type ions, such as: phosphorus ions, arsenic ions.
Referring to fig. 16, a first dielectric layer 211 is formed on the substrate 200, the isolation layer 208, the source-drain doped region 210, and the sidewall of the dummy gate structure 209, and a top surface of the first dielectric layer 211 exposes a top surface of the dummy gate structure 209.
Fig. 16 is a schematic cross-sectional structure diagram of a subsequent step based on fig. 14.
Before forming the first dielectric layer 211, the method further includes: a stop layer (not shown) is formed on the substrate 200, the isolation layer 208, the source-drain doped region 210, and the sidewall of the gate structure 209.
The stop layer is used as an etching stop layer when a contact hole is formed on the source-drain doped region 210 in the following step. The material of the stop layer comprises: silicon nitride, the forming process of the stop layer comprises the following steps: chemical vapor deposition processes.
The forming step of the first dielectric layer 211 includes: forming a first dielectric film on the substrate 200, the isolation layer 208, the source-drain doped region 210, and the sidewall and the top surface of the dummy gate structure 209, and planarizing the first dielectric film until the top surface of the dummy gate structure 209 is exposed to form a first dielectric layer 211.
The first dielectric film comprises the following materials: silicon oxide, and accordingly, the material of the first dielectric layer 211 includes: silicon oxide.
The forming process of the first dielectric film comprises the following steps: chemical vapor deposition process.
The process for flattening the first dielectric film comprises the following steps: and (5) carrying out a chemical mechanical polishing process.
Referring to fig. 17, the dummy gate structure 209 is removed (as shown in fig. 16), and a dummy gate opening 212 is formed in the first dielectric layer 211.
The step of removing the dummy gate structure 209 includes: removing the dummy gate layer; and removing the dummy gate dielectric layer after removing the dummy gate layer.
The process for removing the dummy gate layer comprises the following steps: and (3) an anisotropic dry etching process. The process for removing the pseudo gate dielectric layer comprises the following steps: and (3) an anisotropic dry etching process.
A gate structure is subsequently formed within the dummy gate opening 212.
Referring to fig. 18, a gate structure 213 is formed in the first opening 212.
The forming step of the gate structure 213 includes: forming a gate dielectric layer (not shown) on the sidewall and the bottom of the first opening 212; and forming a gate electrode layer on the gate dielectric layer.
The gate dielectric layer is made of a high-K dielectric material, the high-K dielectric material refers to a material having a dielectric constant K greater than 3.9, and in this embodiment, the high-K dielectric material is: HfO2. In other embodiments, the high-K dielectric material comprises: la2O3、HfSiON、HfAlO2、ZrO2、Al2O3Or HfSiO4. The forming process of the gate dielectric layer comprises the following steps: and (5) an atomic layer deposition process.
The gate layer is made of a metal, and in this embodiment, the metal is tungsten. In other embodiments, the metals include: al, Cu, Ag, Au, Ni, Ti, W, WN or WSi.
Referring to fig. 19, a second dielectric layer 214 is formed on the first dielectric layer 211 and the gate structure 213.
The material of the second dielectric layer 214 includes: silicon oxide, and the forming process of the second dielectric layer 214 includes: chemical vapor deposition process.
The dielectric layer includes: a first dielectric layer 211 and a second dielectric layer 214 on the first dielectric layer 211.
Referring to fig. 20 and 21, fig. 20 is a schematic cross-sectional view taken along line JJ1 of fig. 21, wherein a contact hole (not shown) is formed in the first dielectric layer 211 and the second dielectric layer 214 on the source/drain doped region 210, and the bottom of the contact hole exposes the surface of the source/drain doped region 210; conductive plugs 215 are formed within the contact holes.
The bottom of the contact hole exposes the surface of the source-drain doped region 210, and the source-drain doped region 210 is not only located in the fin structure 230, but also located in the dummy fin 204, so that the dimension of the contact hole in the extending direction (Y direction) perpendicular to the fin 201 is larger, the dimension of the conductive plug 215 formed in the contact hole in the extending direction (Y direction) of the fin 201 is larger, the contact area between the conductive plug 215 and the source-drain doped region 210 is larger, and the reduction of the contact resistance of the semiconductor device is facilitated.
After the contact hole is formed, before the conductive plug 215 is formed, the method further includes: a metal silicide layer (not shown) is formed on the surface of the source/drain doped region 210 at the bottom of the contact hole.
The forming step of the metal silicide layer comprises the following steps: forming a metal material layer in the contact hole; annealing the metal material layer to form the metal silicide layer; and after the annealing process, removing the residual metal material layer.
The material of the metal silicide layer comprises: silicon titanium.
The metal silicide layer is used for reducing the contact resistance between the subsequently formed conductive plug 215 and the source-drain doped region 210, and is beneficial to improving the electrical performance of the transistor.
The forming step of the conductive plug 215 includes: forming a material layer on the second dielectric layer 214 and in the contact hole; the material layer is planarized until the top surface of the second dielectric layer 214 is exposed, forming the conductive plug 215 within the contact hole.
The material of the material layer is metal, and the metal comprises: tungsten. Correspondingly, the material of the conductive plug is metal, and the metal comprises tungsten.
Accordingly, the present invention also provides a semiconductor structure formed by the above method, with continued reference to fig. 20 and 21, including:
a substrate 200, wherein the substrate 200 includes a second region B (see fig. 15) and first regions a (see fig. 15) respectively located at two sides of the second region B, the first regions a are connected to the second region B, a fin structure 230 extending from the first regions a to the second regions B is provided on the substrate 200, and the fin structure 230 includes at least a fin 201;
dummy fin portions 204 on the first region a substrate 200 at two sides of the fin structure 230 in a direction perpendicular to the extending direction of the fin portion 201;
a gate structure 213 overlying the fin structure 230 in the second region B substrate 200;
the fin structure 230 and the source-drain doped region 210 in the dummy fin 204 are positioned at two sides of the gate structure 213;
the dielectric layers are positioned on the substrate 200, the source-drain doped region 210, the side wall of the gate structure 213 and the top surface;
and the contact hole is positioned in the medium layer, and the bottom of the contact hole is exposed out of the top surface of the source drain doped region 210.
The number of the fin portions 201 is: 1 to 40. When the number of the fin portions 201 is greater than 1, more than two fin portions 201 are arranged in parallel along the extending direction perpendicular to the fin portions 201; the spacing between adjacent fins 201 is: 20 to 50 nanometers.
The size of the contact hole is 80-1000 nm along the extending direction parallel to the surface of the substrate 200 and perpendicular to the fin 201.
Along a direction perpendicular to the extending direction of the fin 201, the dimensions of the dummy fin 204 are: 5 to 15 nanometers.
The dummy fin portion 204 and the fin portion 201 are arranged in parallel along a direction perpendicular to the extending direction of the fin portion 201; along a direction perpendicular to the extension of the fin 201, the minimum distance from the dummy fin 204 to the fin structure 230 is: 25 to 100 nanometers.
Further comprising: a metal silicide layer at the bottom of the contact hole; a conductive plug 215 on the metal silicide layer. The material of the metal silicide layer comprises: a silicon-titanium compound; the material of the conductive plug 215 is metal, and the metal includes: tungsten.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (20)

1. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein the substrate comprises a second area and first areas respectively positioned at two sides of the second area, the first areas are connected with the second area, the substrate is provided with a fin part structure extending from the second area to the first areas at two sides, and the fin part structure comprises at least one fin part;
forming pseudo fin portions on the first region substrate on two sides of the fin portion structure, wherein the pseudo fin portions and the fin portions are arranged in parallel along the extending direction perpendicular to the fin portions;
forming a grid structure crossing the fin part structure on the second region substrate;
forming source and drain doped regions in the fin portion structure and the dummy fin portion on two sides of the gate structure respectively, wherein the source and drain doped regions in the fin portion structure are connected with the source and drain doped regions in the dummy fin portion;
forming a dielectric layer covering the side wall of the grid structure on the substrate and the source-drain doped region;
and forming a contact hole in the dielectric layer, wherein the bottom of the contact hole exposes the top surface and the side wall of the source-drain doped region.
2. The method of forming a semiconductor structure of claim 1, wherein the forming of the dummy fin comprises: forming initial pseudo fin portions on the substrate on two sides of the fin portion structure, wherein the initial pseudo fin portions are arranged in parallel with the fin portions along the extending direction perpendicular to the fin portions; and removing the initial pseudo fin part on the second region substrate, and forming the pseudo fin part on the first region substrate.
3. The method of claim 2, wherein the removing the initial dummy fin on the second region substrate comprises: an anisotropic dry etching process; the parameters of the anisotropic dry etching process comprise: the flow rate of the oxygen is 50 standard ml/min-300 standard ml/min, CH3The flow rate of F is 100-500 standard ml/min, the flow rate of helium is 30-200 standard ml/min, the temperature is 25-80 ℃, and the time is 5-100 seconds.
4. The method of claim 1, wherein a minimum distance from the dummy fin to the fin structure in a direction perpendicular to an extension direction of the fin is: 25 to 100 nanometers.
5. The method of claim 1, wherein the dummy fin has a dimension in a direction perpendicular to an extension direction of the fin that is: 5 to 15 nanometers.
6. The method as claimed in claim 1, wherein the fin has a dimension of 5 nm to 15 nm in a direction perpendicular to an extension direction of the fin.
7. The method of forming a semiconductor structure of claim 1, wherein the number of fins is: 1 to 40.
8. The method of claim 1, wherein when the number of the fin portions is greater than 1, more than two fin portions are arranged in parallel along a direction perpendicular to an extending direction of the fin portions; the distance between adjacent fins is: 20 to 50 nanometers.
9. The method for forming the semiconductor structure according to claim 1, wherein the step of forming the source and drain doped regions comprises: forming openings in the pseudo fin parts and the fin part structures on two sides of the grid electrode structure respectively; forming an epitaxial layer in the opening; doping ions into the epitaxial layer to form a source-drain doped region.
10. The method as claimed in claim 9, wherein the opening has a dimension of 80 nm to 1000 nm in a direction perpendicular to the extending direction of the fin.
11. The method of forming a semiconductor structure of claim 9, wherein the step of forming the opening comprises: forming a pattern layer on the substrate, wherein the top surface of the pattern layer is exposed out of the top surfaces of the pseudo fin portion and the fin portion structure; etching the pseudo fin part and the fin part structure by taking the pattern layer as a mask to form the opening; the process for etching the pseudo fin portion and the fin portion structure comprises the following steps: an anisotropic dry etching process; the parameters of the anisotropic dry etching process comprise: CH (CH)4The flow rate of (1) is 8-500 standard ml/min, CHF3The flow rate of the gas is 30-200 standard ml/min, the radio frequency power is 100-1300W, the bias voltage is 80-500V, the pressure of the chamber is 10-2000 mTorr, and the time is 4-500 seconds.
12. The method of forming a semiconductor structure of claim 1, further comprising, after forming the contact hole: forming a metal silicide layer at the bottom of the contact hole; and forming a conductive plug on the metal silicide layer.
13. The method of forming a semiconductor structure of claim 12, wherein the material of the metal silicide layer comprises: a silicon-titanium compound; the conductive plug is made of metal, and the metal comprises: tungsten.
14. The method of claim 1, further comprising providing an isolation layer on the substrate, wherein a top surface of the isolation layer is lower than a top surface of the fin and covers a portion of the sidewall of the fin.
15. A semiconductor structure, comprising:
the substrate comprises a second area and first areas respectively positioned at two sides of the second area, the first areas are connected with the second area, the substrate is provided with a fin portion structure extending from the second area to the first areas at two sides, and the fin portion structure comprises at least one fin portion;
the dummy fin parts are positioned on the first region substrate on two sides of the fin part structure and are arranged in parallel with the fin parts along the extending direction vertical to the fin parts;
a gate structure located on the second region substrate and crossing the fin structure;
the source drain doped region is positioned in the fin part structure and connected with the source drain doped region in the pseudo fin part;
the dielectric layer is positioned on the substrate and the source-drain doped region and covers the side wall of the grid structure;
and the contact hole is positioned in the medium layer, and the bottom of the contact hole is exposed out of the top surface and the side wall of the source-drain doped region.
16. The semiconductor structure of claim 15, wherein the contact hole has a dimension of 80 nm to 1000 nm in a direction perpendicular to the extension direction of the fin.
17. The semiconductor structure of claim 15, wherein a minimum distance from the dummy fin to the fin structure in a direction perpendicular to an extension direction of the fin is: 25-100 nm; along the extending direction perpendicular to the fin portion, the dimension of the dummy fin portion is: 5 to 15 nanometers.
18. The semiconductor structure of claim 15, wherein the number of fins is: 1 to 40.
19. The semiconductor structure of claim 15, wherein when the number of the fin portions is greater than 1, more than two fin portions are arranged in parallel along a direction perpendicular to an extending direction of the fin portions; the distance between adjacent fins is: 20 to 50 nanometers.
20. The semiconductor structure of claim 15, further comprising: a metal silicide layer at the bottom of the contact hole; a plug located on the metal silicide layer; the material of the metal silicide layer comprises: a silicon-titanium compound; the conductive plug is made of metal, and the metal comprises: tungsten.
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