CN109285888A - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN109285888A CN109285888A CN201710596408.3A CN201710596408A CN109285888A CN 109285888 A CN109285888 A CN 109285888A CN 201710596408 A CN201710596408 A CN 201710596408A CN 109285888 A CN109285888 A CN 109285888A
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- 238000000034 method Methods 0.000 title claims abstract description 71
- 239000004065 semiconductor Substances 0.000 title claims abstract description 53
- 239000000758 substrate Substances 0.000 claims abstract description 98
- 239000000463 material Substances 0.000 claims description 57
- 229910052751 metal Inorganic materials 0.000 claims description 38
- 239000002184 metal Substances 0.000 claims description 38
- 229910021332 silicide Inorganic materials 0.000 claims description 21
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 21
- 230000015572 biosynthetic process Effects 0.000 claims description 14
- 238000000926 separation method Methods 0.000 claims description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 9
- 229910052710 silicon Inorganic materials 0.000 claims description 9
- 239000010703 silicon Substances 0.000 claims description 9
- 229910052721 tungsten Inorganic materials 0.000 claims description 9
- 150000002500 ions Chemical class 0.000 claims description 8
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 8
- 239000010937 tungsten Substances 0.000 claims description 8
- UGACIEPFGXRWCH-UHFFFAOYSA-N [Si].[Ti] Chemical compound [Si].[Ti] UGACIEPFGXRWCH-UHFFFAOYSA-N 0.000 claims description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 4
- 239000001301 oxygen Substances 0.000 claims description 4
- 229910052760 oxygen Inorganic materials 0.000 claims description 4
- 239000001307 helium Substances 0.000 claims description 3
- 229910052734 helium Inorganic materials 0.000 claims description 3
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 claims description 3
- 238000002955 isolation Methods 0.000 claims description 3
- 150000001875 compounds Chemical class 0.000 claims 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 12
- 125000006850 spacer group Chemical group 0.000 description 8
- 238000010586 diagram Methods 0.000 description 7
- 239000003989 dielectric material Substances 0.000 description 6
- 239000000377 silicon dioxide Substances 0.000 description 6
- 238000005530 etching Methods 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 229910052737 gold Inorganic materials 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 2
- -1 boron ion Chemical class 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 239000012530 fluid Substances 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical group [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000003701 mechanical milling Methods 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- VIKNJXKGJWUCNN-XGXHKTLJSA-N norethisterone Chemical compound O=C1CC[C@@H]2[C@H]3CC[C@](C)([C@](CC4)(O)C#C)[C@@H]4[C@@H]3CCC2=C1 VIKNJXKGJWUCNN-XGXHKTLJSA-N 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 description 1
- 240000007594 Oryza sativa Species 0.000 description 1
- 235000007164 Oryza sativa Nutrition 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 1
- 238000000231 atomic layer deposition Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 229910052593 corundum Inorganic materials 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
- 229910000167 hafnon Inorganic materials 0.000 description 1
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum oxide Inorganic materials [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- KTUFCUMIWABKDW-UHFFFAOYSA-N oxo(oxolanthaniooxy)lanthanum Chemical compound O=[La]O[La]=O KTUFCUMIWABKDW-UHFFFAOYSA-N 0.000 description 1
- 125000006239 protecting group Chemical group 0.000 description 1
- 235000009566 rice Nutrition 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical group [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000010944 silver (metal) Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910001845 yogo sapphire Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/6681—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET using dummy structures having essentially the same shape as the semiconductor body, e.g. to provide stability
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
A kind of semiconductor structure and forming method thereof, wherein method includes: offer substrate, substrate includes the secondth area and the firstth area for being located at the second area two sides, firstth area is connect with the secondth area, there is the fin structure that the firstth area of two sides is extended to by the secondth area, the fin structure includes at least one fin in substrate；Pseudo- fin is formed in first area's substrate of the fin structure two sides, the puppet fin is with fin along perpendicular to arranged in parallel on the extending direction of fin；The gate structure of fin structure is developed across in second area's substrate；Source and drain doping area is formed in the fin structure of gate structure two sides and pseudo- fin, the source and drain doping area in fin structure is connected with the source and drain doping area being located in pseudo- fin；The dielectric layer for covering the gate structure sidewall is formed in substrate and source and drain doping area；Contact hole is formed in dielectric layer, the bottom-exposed of contact hole goes out the top surface in source and drain doping area.The contact resistance for the device that the method is formed is small.
Description
Technical field
The present invention relates to field of semiconductor manufacture more particularly to a kind of semiconductor structure and forming method thereof.
Background technique
With the continuous development of semiconductor technology, the size of semiconductor devices constantly reduces.With the ruler of semiconductor devices
Very little diminution, the contact resistance of MOS transistor influence the performance of MOS transistor and entire semiconductor chip increasing.
In order to improve the performance of semiconductor chip, need to reduce the contact resistance of MOS transistor.And MOS transistor connects
In electric shock resistance, since the area of source electrode, drain electrode is smaller, the contact resistance between conductive plunger is larger, to MOS transistor
Performance is affected, so that the speed of service of semiconductor devices is greatly reduced.
Summary of the invention
The technical problem to be solved by the present invention is to provide a kind of forming methods of semiconductor structure, to improve semiconductor devices
Performance.
In order to solve the above technical problems, the embodiment of the present invention provides a kind of forming method of semiconductor structure, comprising: mention
For substrate, the substrate includes the secondth area and the firstth area for being located at the second area two sides, and firstth area and the secondth area connect
It connects, there is the fin structure for extending to the firstth area of two sides by the secondth area, the fin structure includes at least one in the substrate
Fin；Pseudo- fin is formed in first area's substrate of the fin structure two sides, the puppet fin and fin are along perpendicular to fin
Extending direction on it is arranged in parallel；The gate structure of fin structure is developed across in secondth area substrate；In the grid
It is respectively formed source and drain doping area in the fin structure of structure two sides and pseudo- fin, the source and drain doping in fin structure
Area is connected with the source and drain doping area being located in pseudo- fin；It is formed in the substrate and source and drain doping area and covers the grid
The dielectric layer of pole structure side wall；Contact hole is formed in the dielectric layer, the bottom-exposed of the contact hole goes out source and drain doping area
Top surface.
Optionally, the forming step of the pseudo- fin includes: that initial puppet is formed in the substrate of the fin structure two sides
Fin, the initial pseudo- fin is with fin along perpendicular to arranged in parallel on the extending direction of fin；It removes in second area's substrate
Initial puppet fin forms the pseudo- fin in firstth area substrate.
Optionally, the technique for removing the initial pseudo- fin in second area's substrate includes: anisotropic dry etch process；
The parameter of the anisotropic dry etch process includes: that the flow of oxygen is 50 standard milliliters/minute~~300 standards milli
Liter/min, CH3The flow of F is 100 standard milliliters/minute~500 standard milliliters/minute, and the flow of helium is 30 standards milli
Liter/min~200 standard milliliters/minute, temperature is 25 degrees Celsius~80 degrees Celsius, and the time is 5 seconds~100 seconds.
Optionally, along perpendicular on the extending direction of fin, the minimum range of pseudo- fin to fin structure for 25 nanometers~
100 nanometers.
Optionally, along perpendicular on the extending direction of fin, the size of pseudo- fin are as follows: 5 nanometers~15 nanometers.
Optionally, along perpendicular on the extending direction of fin, the size of fin are as follows: 5 nanometers~15 nanometers.
Optionally, the number of the fin are as follows: 1~40.
Optionally, when the number of the fin is greater than 1, more than two fins are along the extending direction perpendicular to fin
It is upper arranged in parallel；Spacing between adjacent fin are as follows: 20 nanometers~50 nanometers.
Optionally, the forming step in the source and drain doping area include: respectively the gate structure two sides pseudo- fin and
Opening is formed in fin structure；Epitaxial layer is formed in the opening；Doped ions are mixed in the epitaxial layer, form source
Leak doped region.
Optionally, along perpendicular on the extending direction of fin, the size of the opening are as follows: 80 nanometers~1000 nanometers.
Optionally, the forming step of the opening includes: to form graph layer on the substrate, the top of the graph layer
Portion surface exposes the top surface of pseudo- fin and fin structure；Using the graph layer as exposure mask, the pseudo- fin and fin are etched
Portion's structure forms the opening；The technique for etching the pseudo- fin and fin structure includes: anisotropic dry etch process；
The parameter of the anisotropic dry etch process includes: CH4Flow be 8 standard milliliters/minute~500 standard milliliters/point
Clock, CHF3Flow be 30 standard milliliters/minute~200 standard milliliters/minute, radio-frequency power be 100 watts~1300 watts, partially
Setting voltage is 80 volts~500 volts, and chamber pressure is 10 millitorrs~2000 millitorrs, and the time is 4 seconds~500 seconds.
Optionally, it is formed after the contact hole, further includes: form metal silicide layer in the contact hole bottom；?
Conductive plunger is formed on the metal silicide layer.
Optionally, the material of the metal silicide layer includes: silicon-titanium compound；The material of the conductive plunger is gold
Belong to, metal includes: tungsten.
Optionally, also there is separation layer, the top surface of the separation layer is lower than the top table of fin in the substrate
Face, and cover the partial sidewall of fin.
The present invention also provides a kind of semiconductor structures, comprising: substrate, the substrate include the secondth area and be located at the
Firstth area in two areas two sides, firstth area are connect with the secondth area, are had in the substrate and are extended to two sides first by the secondth area
The fin structure in area, the fin structure include at least one fin；In first area's substrate of the fin structure two sides
Pseudo- fin, the puppet fin is along perpendicular to arranged in parallel with fin on the extending direction of fin；It is horizontal in second area's substrate
Gate structure across fin structure；Source and drain doping area in the fin structure and pseudo- fin of the gate structure two sides, position
It is connected in the source and drain doping area in fin structure with the source and drain doping area being located in pseudo- fin；Positioned at the substrate
With the dielectric layer in source and drain doping area, the side wall of the dielectric layer covering gate structure；Contact in the dielectric layer
Hole, the bottom-exposed of the contact hole go out the top surface in source and drain doping area.
Optionally, along perpendicular on the extending direction of fin, the size of the contact hole is 80 nanometers~1000 nanometers.
Optionally, along perpendicular on the extending direction of fin, the minimum range of pseudo- fin to fin structure are as follows: 25 nanometers
~100 nanometers；Along perpendicular on the extending direction of fin, the size of pseudo- fin are as follows: 5 nanometers~15 nanometers.
Optionally, the number of the fin are as follows: 1~40.
Optionally, when the number of the fin is greater than 1, more than two fins are along the extending direction perpendicular to fin
It is upper arranged in parallel；Spacing between adjacent fin are as follows: 20 nanometers~50 nanometers.
Optionally, further includes: the metal silicide layer positioned at contact hole bottom；Plug on metal silicide layer；
The material of the metal silicide layer includes: silicon-titanium compound；The material of the conductive plunger is metal, and metal includes: tungsten.
Compared with prior art, the technical solution of the embodiment of the present invention has the advantages that
In the forming method for the semiconductor structure that technical solution of the present invention provides, the first of the fin structure two sides
Pseudo- fin, the puppet fin and fin edge are formed in area's substrate perpendicular to arranged in parallel on the extending direction of fin, so that subsequent
The source and drain doping area is not only formed in fin structure, the source and drain doping area is also formed in pseudo- fin, so that along vertical
In on the extending direction of fin, the size in the source and drain doping area in fin structure compared with only forming the source and drain doping area
Size is big.Subsequent that the contact hole is formed in dielectric layer, the bottom-exposed of the contact hole goes out the top in the source and drain doping area
Portion surface, therefore, the contact hole edge are larger perpendicular to the size on the extending direction of fin, so that subsequent in contact hole
The conductive plunger of formation and the contact area in source and drain doping area are larger, advantageously reduce connecing for conductive plunger and source and drain doping area
Electric shock resistance.
Detailed description of the invention
Fig. 1 to Fig. 3 is a kind of structural schematic diagram of each step of forming method of semiconductor structure；
Fig. 4 to Figure 21 is the structural schematic diagram of each step of one embodiment of forming method of semiconductor structure of the present invention.
Specific embodiment
As described in background, the performance of the semiconductor devices is poor.
Fig. 1 to Fig. 3 is a kind of structural schematic diagram of the forming method of semiconductor structure.
Fig. 1 and Fig. 2 are please referred to, described Fig. 1 is diagrammatic cross-section of the Fig. 2 along AA1 line, and Fig. 2 is section of the Fig. 1 along BB1 line
Schematic diagram provides substrate 100, has fin structure 101 in the substrate 100, and the fin structure 101 includes at least one
Fin 110；It is developed across the gate structure 102 of the fin structure 101；Fin 110 in 102 two sides of gate structure
Interior formation source and drain doping area 103；It is formed in the substrate 100 and source and drain doping area 103 and covers 102 side of gate structure
The dielectric layer 104 of wall；Contact hole (not marking in figure) is formed in the dielectric layer 104, the contact holes exposing goes out source and drain and mixes
The top surface in miscellaneous area 103；Conductive plunger 105 is formed in the contact hole.
In the above method, the fin structure 101 includes at least one fin 110.When the fin structure 101 includes:
When two or more fin 110, two or more fin 110 is along perpendicular to 110 extending direction of fin
It is upper arranged in parallel.
However, the fin 110 is on perpendicular to 110 extending direction of fin with the raising of semiconductor devices integrated level
Size constantly reduce.If also, the fin structure 101 is when including: two or more fin 110, adjacent fins
Spacing between portion 110 also constantly reduces, so that the source and drain doping area 103 is along being parallel to 100 surface of substrate and perpendicular to fin
Size on the extending direction in portion 110 also constantly reduces.It is subsequent that the contact hole, the contact hole are formed in dielectric layer 104
Bottom-exposed goes out the top surface in source and drain doping area 103, and therefore, the contact hole is along being parallel to 100 surface of substrate and vertical
Constantly reduce in the size on the extending direction of fin 110, so that the subsequent conductive plunger 105 formed in contact hole and source
The contact area for leaking doped region 103 is smaller, so that conductive plunger 105 and the contact resistance in source and drain doping area 103 are larger.
A kind of method for the contact resistance reducing conductive plunger 105 and the miscellaneous area 103 of source and drain includes: to increase conductive plunger 105
With the contact area in source and drain doping area 103.Specifically, increasing the contact hole edge is parallel to 100 surface of substrate and perpendicular to fin
Size on 110 extending direction of portion, specific referring to FIG. 3, Fig. 1 is diagrammatic cross-section of the Fig. 3 along CC1 line, Fig. 3 is the edge Fig. 1
The diagrammatic cross-section of BB1 line.
Due to the raising of semiconductor devices integrated level, so that the source and drain doping area 103 formed in adjacent fin 110
Side wall is connected, so that subsequent 110 side of fin in dielectric layer 104 when formation contact hole, among fin structure 101
Wall is because the blocking by source and drain doping area 103 is without being exposed.And it is located at the side of the outermost fin 110 of fin structure 101
Wall is exposed because of the blocking of without source-drain doped region 103.It is subsequent to be formed before conductive plunger 105 in contact hole, also wrap
It includes: forming metal silicide layer in the contact hole.When forming the metal silicide layer, the fin structure 101 is most
The side wall that outside fin 110 is exposed also is metallized, so that it is subsequent in biasing on plug 105, it is metallized
Fin 110 is also added the bias.Due to the well region conduction type in source and drain doping area 103 and substrate 100 on the contrary, then source and drain
The PN junction of doped region 103 and well region is easy to be connected or puncture under the influence of the bias, thus easily in 110 quilt of fin
Exposed side-walls are leaked electricity, and are unfavorable for improving the performance of semiconductor devices.
In order to solve the above technical problems, technical solution of the present invention provides a kind of forming method of semiconductor structure, comprising:
The substrate includes the secondth area and the firstth area for being located at the second area two sides, has the fin structure in substrate；In fin
Pseudo- fin is formed in first area's substrate of structure two sides, the puppet fin and fin are put down along perpendicular on the extending direction of fin
Row arrangement；The source and drain doping area is formed in the fin structure of the gate structure two sides and pseudo- fin.The method can
Reduce the contact resistance in source and drain doping area with the conductive plunger being subsequently formed.
It is understandable to enable above-mentioned purpose of the invention, feature and beneficial effect to become apparent, with reference to the accompanying drawing to this
The specific embodiment of invention is described in detail.
Fig. 4 to Figure 21 is the structural schematic diagram of each step of one embodiment of forming method of semiconductor structure of the present invention.
Fig. 4 and Fig. 5 are please referred to, Fig. 5 is the top view of Fig. 4, and Fig. 4 is diagrammatic cross-section of the Fig. 5 along DD1 line, provides substrate
200, the substrate 200 includes the second area B and the first area A for being located at the second area two sides B, the firstth area A and the secondth area
B connection has the fin structure 230 that the firstth area of two sides A is extended to by the second area B, the fin structure in the substrate 200
230 include at least one fin 201.
The forming step of the substrate 200 and fin structure 230 includes: offer initial substrate；The graphical initial lining
Bottom forms substrate 200 and the fin structure 230 in substrate 200.
In the present embodiment, the material of the initial substrate is SiGe.In other embodiments, the initial substrate is also
It can be the semiconductor substrates such as germanium substrate, silicon substrate, silicon-on-insulator or germanium on insulator.
The number of fin 101 can be set according to actual process demand in the fin structure 230.In the present embodiment, institute
State the number of fin 201 are as follows: 1~40, more than two fins 201 are along the side extended perpendicular to the fin 201
It is arranged upwards.In other embodiments, the number of the fin can be greater than 40.
In the present embodiment, it is illustrated so that the fin structure 230 includes two fins 201 as an example, two fins
Portion 201 is arranged in parallel along the extending direction perpendicular to fin 201.The extending direction of the fin 201 is the fin 201
Longitudinal direction (X-direction).
The spacing of adjacent fin 201 are as follows: 20 nanometers~50 nanometers.
Along perpendicular on the extending direction (Y-direction) of fin 201, the size of the fin 201 are as follows: 5 nanometers~15 receive
Rice.
Along perpendicular on the extending direction (Y-direction) of fin 201, the size of fin structure 230 be by fin size,
The spacing of adjacent fin and the number of fin determine.
Along perpendicular on the extending direction (Y-direction) of fin 201, the size of fin structure 230, the pseudo- fin being subsequently formed
The size in the source and drain doping area that the size in portion and pseudo- fin determine to be subsequently formed to the minimum range between fin structure 230.
In the present embodiment, it is formed after the substrate 200 and fin structure 230, in 230 two sides of fin structure
Substrate 200 on form initial pseudo- fin 202, the initial pseudo- fin 202 and fin 201 are along the extension perpendicular to fin 201
It is arranged in parallel on direction (Y-direction).Specifically, the orientation of the fin 201 and the initial pseudo- fin 202 is fin
The line direction (Y-direction) at 202 center of 201 centers and the initial pseudo- fin.
The initial pseudo- fin 202 extends to the firstth area of two sides A substrate 200 by second area's B substrate 200.
The material of the initial pseudo- fin 202 includes: silicon.
The initial pseudo- fin 202 in the firstth area A substrate 200 is for being subsequently formed pseudo- fin.
Along perpendicular on the extending direction (Y-direction) of fin 201, the size of the initial pseudo- fin 202 are as follows: 5 nanometers~
15 nanometers.
Initial pseudo- fin 202 and fin 201 parallel along the extending direction (Y-direction) perpendicular to fin 201
Column.Along perpendicular on the extending direction (Y-direction) of fin 201, the initial pseudo- fin 202 arrives the most narrow spacing of fin structure 230
From b are as follows: 25 nanometers~100 nanometers.The minimum range b of initial pseudo- fin 202 to the fin structure 230 is referred to: along vertical
In on the extending direction (Y-direction) of fin 201, the side wall in the initial pseudo- fin 202 close to fin structure 230 is described in
Close to the distance of the side wall of initial pseudo- fin 202 in fin structure 230.
Along perpendicular on the extending direction (Y-direction) of fin 201, the initial pseudo- fin 202 arrives fin structure 230
Minimum range b determines the pseudo- fin being subsequently formed to the minimum range b of fin structure 230.
In other embodiments, the substrate, fin structure and initial pseudo- fin are formed simultaneously.The substrate, fin knot
The forming step of structure and initial pseudo- fin includes: offer initial substrate；The graphical initial substrate forms substrate and is located at
Fin structure and initial pseudo- fin in substrate.
Please refer to Fig. 6 and Fig. 7, Fig. 6 is the top view of Fig. 7, and Fig. 7 is diagrammatic cross-section of the Fig. 6 along EE1 line, described in removal
Initial pseudo- fin 202 in second area's B substrate 200 forms the pseudo- fin 204 in the firstth area A substrate 200, described
Pseudo- fin 204 and fin 201 are arranged in parallel along the extending direction (Y-direction) perpendicular to fin 201.
The technique for removing the initial pseudo- fin 202 in the secondth area B substrate 200 includes: anisotropic dry etching work
Skill；The parameter of the anisotropic dry etch process includes: that the flow of oxygen is 50 standard milliliters/minute~~300 standards
Ml/min, CH3The flow of F is 100 standard milliliters/minute~500 standard milliliters/minute, and the flow of helium is 30 standards
Ml/min~200 standard milliliters/minute, temperature are 25 degrees Celsius~80 degrees Celsius, and the time is 5 seconds~100 seconds.
Along perpendicular on the extending direction (Y-direction) of fin 201, the size of the puppet fin 204 is by initial pseudo- fin
What 202 size determined, therefore, size of the puppet fin 204 on the extending direction (Y-direction) perpendicular to fin 201
Are as follows: 5 nanometers~15 nanometers.
The meaning of size of the pseudo- fin 204 on the extending direction (Y-direction) perpendicular to fin 201 is selected to be:
If size of the puppet fin 204 on the extending direction perpendicular to fin 201 is less than 5 nanometers, so that the contact being subsequently formed
The size in hole is smaller, is unfavorable for improving the subsequent contact surface between the conductive plunger formed in contact hole and source and drain doping area
Product, so that conductive plunger and the contact resistance in source and drain doping area are larger；If the puppet fin 204 is along prolonging perpendicular to fin 201
The size stretched on direction is greater than 15 nanometers, is unfavorable for improving the integrated level of semiconductor devices.
The puppet fin 204 and fin 201 are arranged in parallel along the extending direction (Y-direction) perpendicular to fin 201.Edge
Perpendicular on the extending direction (Y-direction) of fin 201, the minimum range b of puppet fin 204 to the fin structure 230 is by first
Pseudo- fin 202 begin to the minimum range b decision of fin structure 230, therefore, the puppet fin 204 is along perpendicular to fin 201
The minimum range b of fin structure 230 is arrived on extending direction (Y-direction) are as follows: 25 nanometers~100 nanometers.
The puppet fin 204 arrives the most narrow spacing of fin structure 230 along the extending direction (Y-direction) perpendicular to fin 201
From b are as follows: 25 nanometers~100 nanometers, the pseudo- fin 204 is selected to arrive fin structure along the extending direction perpendicular to fin 201
The meaning of 230 minimum range b is: if the puppet fin 204 arrives along the extending direction (Y-direction) perpendicular to fin 201
The minimum range b of fin structure 230 is less than 25 nanometers, so that the size for the contact hole being subsequently formed is smaller, after being unfavorable for raising
Continue the contact area between the conductive plunger formed in contact hole and source and drain doping area, so that conductive plunger and source and drain doping
The contact resistance in area is larger；If the puppet fin 204 arrives fin structure along the extending direction (Y-direction) perpendicular to fin 201
230 minimum range b is greater than 100 nanometers, is unfavorable for improving the integrated level of semiconductor devices.
Referring to FIG. 8, in the substrate 200 and the side wall and top surface of fin structure 230 and pseudo- fin 204
Form oxide layer 206.
It should be noted that Fig. 8 is the schematic diagram of the section structure based on Fig. 7 profile direction.
The material of the oxide layer 206 includes: silica.
The formation process of the oxide layer 206 includes: chemical vapor deposition process.
When the oxide layer 206 is used to be subsequently formed spacer material layer, 200 surface of protecting group bottom and fin structure
230 and pseudo- fin 204 side wall and top surface.
Referring to FIG. 9, forming spacer material layer 207, the top of the spacer material layer 207 in the oxide layer 206
Surface exposes the oxide layer 206 of 204 top surface of fin structure 230 and pseudo- fin.
The spacer material layer 207 is for being subsequently formed separation layer.
In the present embodiment, the material of the spacer material layer 207 is silica.In other embodiments, the isolation
The material of material layer includes: silicon oxynitride.
The forming step of the spacer material layer 207 includes: the formation isolated material film in the oxide layer 206；It is flat
Change the isolated material film, until expose the oxide layer 206 of fin structure 230 and pseudo- 204 top surface of fin, formed every
From material layer 207.
The formation process of the isolated material film includes: fluid chemistry gas-phase deposition.
The isolated material film formed using fluid chemistry gas-phase deposition is to fin structure 230 and fin structure
The filling capacity in the gap between 230 and pseudo- fin 204 is stronger, is formed by 207 isolation of semiconductor difference device of spacer material layer
The performance of part is good.
During forming isolated material film, the oxide layer 206 can protect 200 surface of substrate and fin
The side wall and top surface of portion's structure 230 and pseudo- fin 204, so that 200 surface of the substrate and fin structure 230 and puppet
The damage that the side wall and top surface of fin 204 are subject to is smaller, is conducive to the performance for improving semiconductor devices.
The technique for planarizing the isolated material film includes: chemical mechanical milling tech.
Figure 10 and 11 are please referred to, Figure 11 is diagrammatic cross-section of the Figure 10 along FF1 line, part spacer material layer 207 is removed,
Separation layer 208 is formed, the top surface of the separation layer 208 is lower than the top surface of fin structure 230 and pseudo- fin 204, and
Cover the partial sidewall of fin structure 230 and pseudo- fin 204.
The formation process of separation layer 208 includes: wet-etching technology；The parameter of the wet-etching technology includes: etching
Agent includes hydrofluoric acid solution, and the mass percent concentration of etching agent is 0.1%~1%.
During forming separation layer 208, the oxygen of fin structure 230 and pseudo- fin 204 partial sidewall and top surface
Change layer 206 to be also removed, exposes fin structure 230 and pseudo- 204 partial sidewall of fin and top surface.
It is formed after the separation layer 208, the grid knot of fin structure 230 is developed across in second area's B substrate 200
Structure.The gate structure includes: gate dielectric layer and the grid layer on gate dielectric layer.In the present embodiment, the grid are situated between
The material of matter layer is high K dielectric material, and the dielectric constant of the high K dielectric material is greater than 3.9, and the material of the grid layer is
Metal.The gate structure is formed by rear grid technique, specifically please refers to Figure 12 to Figure 18.In other embodiments, the grid
The material of dielectric layer includes: silica, and the material of the grid layer includes: silicon.
Figure 12 and Figure 13 are please referred to, Figure 12 is Figure 13 along the diagrammatic cross-section of GG1 line, and Figure 13 is the top view of Figure 12, shape
After separation layer 208, the pseudo- grid structure 209 of fin structure 230 is developed across in second area's B substrate.
Dummy gate structure 209 includes: the pseudo- gate dielectric layer (figure positioned at 230 partial sidewall of fin structure and top surface
In do not mark) and dummy gate layer (not marked in figure) on pseudo- gate dielectric layer.
The material of the puppet gate dielectric layer includes: silica.The material of the dummy gate layer includes: silicon.
Shape in the pseudo- fin 204 of the subsequent fin structure 230, first in pseudo- 209 two sides of grid structure and the second pseudo- fin 205
At source and drain doping area.
Figure 14 and Figure 15 are please referred to, Figure 14 is diagrammatic cross-section of the Figure 15 along HH1 line, the puppet in pseudo- 209 two sides of grid structure
Source and drain doping area 210 is formed in fin 204 and fin structure 230.
The forming step in the source and drain doping area 210 includes: the pseudo- fin 204 and fin in 209 two sides of dummy gate structure
Opening is formed in portion's structure 230；Epitaxial layer is formed in the opening；Doped ions are mixed in the epitaxial layer, form source
Leak doped region 210.
The forming step of the opening includes: that graph layer is formed in the substrate 200, the top table of the graph layer
Face exposes the top surface of pseudo- fin 204 and fin structure 230；Using the graph layer as exposure mask, the pseudo- fin is etched
204 and fin structure 230, form the opening.
The patterned material includes: silicon nitride.
The technique for etching the pseudo- fin 204 and fin structure 230 includes: anisotropic dry etch process；It is described each
The parameter of anisotropy dry etch process includes: CH4Flow be 8 standard milliliters/minute~500 standard milliliters/minute, CHF3
Flow be 30 standard milliliters/minute~200 standard milliliters/minute, radio-frequency power is 100 watts~1300 watts, and bias voltage is
80 volts~500 volts, chamber pressure is 10 millitorrs~2000 millitorrs, and the time is 4 seconds~500 seconds.
The opening edge is parallel to 200 surface of substrate and perpendicular to the size in the extending direction of fin 201 (Y-direction)
Are as follows: 80 nanometers~1000 nanometers, select the opening along the meaning perpendicular to the size on the extending direction (Y-direction) of fin 201
Justice is: if opening edge is parallel to 200 surface of substrate and perpendicular to the size in the extending direction of fin 201 (Y-direction)
Less than 80 nanometers, so that being formed by size of the source and drain doping area 210 on the extending direction (Y-direction) perpendicular to fin 201
It is smaller, so that the contact hole formed in the subsequent dielectric layer in source and drain doping area 210 is along the extension side perpendicular to fin 201
Size in (Y-direction) is smaller, so that the contact surface of subsequent conductive plunger and source and drain doping area 210 in contact hole
Product is smaller, so that conductive plunger and the contact resistance in source and drain doping area 210 are larger；If the opening edge is parallel to substrate
200 surfaces and perpendicular to the size on the extending direction of fin 201 (direction Y) be greater than 1000 nanometers, be unfavorable for improve semiconductor
The integrated level of device.
The material and Doped ions of the epitaxial layer are related to the type of transistor, if the transistor is PMOS brilliant
When body pipe, the material of the epitaxial layer are as follows: SiGe or silicon, the Doped ions are as follows: P-type ion, such as: boron ion.If described
When transistor is NMOS transistor, the material of the epitaxial layer is silicon carbide or silicon, the Doped ions are as follows: N-type ion,
Such as: phosphonium ion, arsenic ion.
Figure 16 is please referred to, in the substrate 200, separation layer 208 and source and drain doping area 210 and pseudo- grid structure 209
Side wall form first medium layer 211, the top surface of the first medium layer 211 exposes the top table of pseudo- grid structure 209
Face.
It should be noted that Figure 16 is the schematic diagram of the section structure of the subsequent step on the basis of Figure 14.
Formed before the first medium layer 211, further includes: in the substrate 200, on separation layer 208, source and drain mixes
In miscellaneous area 210 and the side wall of gate structure 209 forms stop-layer (not marking in figure).
The stop-layer for it is subsequent in source and drain doping area 210 formed contact hole when as etching stop layer.It is described to stop
Only the material of layer includes: silicon nitride, and the formation process of the stop-layer includes: chemical vapor deposition process.
The forming step of the first medium floor 211 includes: in the substrate 200, separation layer 208, source and drain doping area
210 and the side wall and top surface of pseudo- grid structure 209 form first medium film, planarize the first medium film, until
The top surface of pseudo- grid structure 209 is exposed, first medium layer 211 is formed.
The material of the first medium film includes: silica, correspondingly, the material of first medium layer 211 includes: oxidation
Silicon.
The formation process of the first medium film includes: chemical vapor deposition process.
The technique for planarizing the first medium film includes: chemical mechanical milling tech.
Figure 17 is please referred to, removes dummy gate structure 209 (as shown in figure 16), is formed in the first medium layer 211
Pseudo- grid opening 212.
The step of removing dummy gate structure 209 includes: removal dummy gate layer；After removing dummy gate layer, pseudo- grid are removed
Dielectric layer.
The technique for removing dummy gate layer includes: anisotropic dry etch process.Remove the technique packet of pseudo- gate dielectric layer
It includes: anisotropic dry etch process.
It is subsequent to form gate structure in the pseudo- grid opening 212.
Figure 18 is please referred to, forms gate structure 213 in first opening 212.
The forming step of the gate structure 213 includes: to form grid in the side wall of first opening 212 and bottom to be situated between
Matter layer (does not mark) in figure；Grid layer is formed on the gate dielectric layer.
The material of the gate dielectric layer is high K dielectric material, and the high K dielectric material refers to that dielectric constant K is greater than
3.9 material, in the present embodiment, the high K dielectric material are as follows: HfO2.In other embodiments, the high K dielectric material
It include: La2O3、HfSiON、HfAlO2、ZrO2、Al2O3Or HfSiO4.The formation process of the gate dielectric layer includes: atomic layer deposition
Product technique.
The material of the grid layer is metal, and in the present embodiment, the metal is tungsten.In other embodiments, described
Metal includes: Al, Cu, Ag, Au, Ni, Ti, W, WN or WSi.
Figure 19 is please referred to, forms second dielectric layer 214 on the first medium layer 211 and gate structure 213.
The material of the second dielectric layer 214 includes: silica, and the formation process of the second dielectric layer 214 includes:
Chemical vapor deposition process.
The dielectric layer includes: first medium layer 211 and the second dielectric layer 214 on first medium layer 211.
Figure 20 and Figure 21 are please referred to, Figure 20 is diagrammatic cross-section of the Figure 21 along JJ1 line, in the source and drain doping area 210
First medium layer 211 and second dielectric layer 214 in formed contact hole (not marked in figure), the bottom-exposed of the contact hole
The surface in source and drain doping area 210 out；Conductive plunger 215 is formed in the contact hole.
The bottom-exposed of the contact hole goes out the surface in source and drain doping area 210, and the source and drain doping area 210 not only position
In in fin structure 230, being also located in pseudo- fin 204, so that contact hole is along the extending direction (Y-direction) perpendicular to fin 201
On size it is larger so that the subsequent conductive plunger 215 formed in contact hole is along the extending direction (Y-direction) of fin 201
Size it is larger so that conductive plunger 215 and the contact area in source and drain doping area 210 are larger, advantageously reduce semiconductor devices
Contact resistance.
It is formed after the contact hole, is formed before conductive plunger 215, further includes: the source and drain doping in contact hole bottom
The surface in area 210 forms metal silicide layer (not marking in figure).
The forming step of the metal silicide layer includes: to form metal material layer in the contact hole；The metal
Metal silicide layer described in the annealed formation of material layer；After the annealing process, remaining metal material layer is removed.
The material of the metal silicide layer includes: silicon titanium.
The metal silicide layer is for reducing the electricity of the contact with source and drain doping area 210 of conductive plunger 215 being subsequently formed
Resistance is conducive to the electric property for improving transistor.
The forming step of the conductive plunger 215 includes: in the second dielectric layer 214 and to form material in contact hole
The bed of material；The material layer is planarized, until exposing the top surface of second dielectric layer 214, is led described in formation in contact hole
Electric plug 215.
The material of the material layer is metal, and the metal includes: tungsten.Correspondingly, the material of the conductive plunger is gold
Belong to, the metal includes tungsten.
Correspondingly, the present invention also provides a kind of semiconductor structures formed using the above method, please continue to refer to Figure 20 and
Figure 21, comprising:
Substrate 200, the substrate 200 include the second area B (see Figure 15) and the first area A for being located at the second area two sides B
(see Figure 15), the firstth area A are connect with the second area B, are had in the substrate 200 and are extended to the second area B's by the first area A
Fin structure 230, the fin structure 230 include at least fin 201；
Along perpendicular on the extending direction of the fin 201, it is located at the firstth area of 230 two sides of fin structure A substrate
Pseudo- fin 204 on 200；
Across the gate structure 213 of fin structure 230 in second area's B substrate 200；
Source and drain doping area 210 in the fin structure 230 and pseudo- fin 204 of 213 two sides of gate structure；
In the substrate 200 and source and drain doping area 210 and Jie of the side wall of gate structure 213 and top surface
Matter layer；
Contact hole in the dielectric layer, the bottom-exposed of the contact hole go out the top table in source and drain doping area 210
Face.
The number of the fin 201 are as follows: 1~40.It is more than two when the number of the fin 201 is greater than 1
Fin 201 is arranged in parallel along the extending direction perpendicular to fin 201；Spacing between adjacent fin 201 are as follows: 20 nanometers~
50 nanometers.
Edge is parallel to 200 surface of substrate and perpendicular on the extending direction of fin 201, and the size of the contact hole is 80
Nanometer~1000 nanometers.
Along perpendicular on the extending direction of fin 201, the size of pseudo- fin 204 are as follows: 5 nanometers~15 nanometers.
Pseudo- fin 204 and fin 201 are arranged in parallel along the extending direction perpendicular to fin 201；Along perpendicular to fin
On 201 extending direction, pseudo- fin 204 arrives the minimum range of fin structure 230 are as follows: 25 nanometers~100 nanometers.
Further include: the metal silicide layer positioned at contact hole bottom；Conductive plunger 215 on metal silicide layer.
The material of the metal silicide layer includes: silicon-titanium compound；The material of the conductive plunger 215 is metal, and metal includes:
Tungsten.
Although present disclosure is as above, present invention is not limited to this.Anyone skilled in the art are not departing from
It in the spirit and scope of the present invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim
Subject to limited range.
Claims (20)
1. a kind of forming method of semiconductor structure characterized by comprising
Substrate is provided, the substrate includes the secondth area and the firstth area for being located at the second area two sides, firstth area and second
Area connects, and has the fin structure that the firstth area of two sides is extended to by the secondth area in the substrate, and the fin structure includes at least
One fin；
Pseudo- fin is formed in first area's substrate of the fin structure two sides, the puppet fin and the fin are along perpendicular to fin
The extending direction in portion is arranged in parallel；
The gate structure of fin structure is developed across in second area's substrate；
It is respectively formed source and drain doping area in the fin structure of the gate structure two sides and pseudo- fin, in fin structure
The source and drain doping area is connected with the source and drain doping area being located in pseudo- fin；
The dielectric layer for covering the gate structure sidewall is formed in the substrate and source and drain doping area；
Contact hole is formed in the dielectric layer, the bottom-exposed of the contact hole goes out the top surface in source and drain doping area.
2. the forming method of semiconductor structure as described in claim 1, which is characterized in that the forming step packet of the puppet fin
It includes: forming initial pseudo- fin in the substrate of the fin structure two sides, the initial pseudo- fin is along the extension perpendicular to fin
It is arranged in parallel with fin on direction；The initial pseudo- fin in secondth area substrate is removed, is formed in firstth area substrate
The puppet fin.
3. the forming method of semiconductor structure as claimed in claim 2, which is characterized in that initial in second area's substrate of removal
The technique of pseudo- fin includes: anisotropic dry etch process；The parameter of the anisotropic dry etch process includes: oxygen
Flow be 50 standard milliliters/minute~~300 standard milliliters/minute, CH3The flow of F is 100 standard milliliters/minute~500
Standard milliliters/minute, the flow of helium are 30 standard milliliters/minute~200 standard milliliters/minute, temperature is 25 degrees Celsius~
80 degrees Celsius, the time is 5 seconds~100 seconds.
4. the forming method of semiconductor structure as described in claim 1, which is characterized in that along the extending direction perpendicular to fin
On, the minimum range of pseudo- fin to fin structure are as follows: 25 nanometers~100 nanometers.
5. the forming method of semiconductor structure as described in claim 1, which is characterized in that along the extending direction perpendicular to fin
On, the size of pseudo- fin are as follows: 5 nanometers~15 nanometers.
6. the forming method of semiconductor structure as described in claim 1, which is characterized in that along the extending direction perpendicular to fin
On, the size of the fin is 5 nanometers~15 nanometers.
7. the forming method of semiconductor structure as described in claim 1, which is characterized in that the number of the fin are as follows: 1~
40.
8. the forming method of semiconductor structure as described in claim 1, which is characterized in that the number of the fin is greater than 1
When, more than two fins are along perpendicular to arranged in parallel on the extending direction of fin；Spacing between adjacent fin are as follows: 20 nanometers
~50 nanometers.
9. the forming method of semiconductor structure as described in claim 1, which is characterized in that the formation in the source and drain doping area walks
It suddenly include: to form opening in pseudo- fin and the fin structure difference of the gate structure two sides；It is formed in the opening outer
Prolong layer；Doped ions are mixed in the epitaxial layer, form source and drain doping area.
10. the forming method of semiconductor structure as claimed in claim 9, which is characterized in that along the extension side perpendicular to fin
Upwards, the size of the opening is 80 nanometers~1000 nanometers.
11. the forming method of semiconductor structure as claimed in claim 9, which is characterized in that the forming step packet of the opening
It includes: forming graph layer on the substrate, the top surface of the graph layer exposes the top table of pseudo- fin and fin structure
Face；Using the graph layer as exposure mask, the pseudo- fin and fin structure are etched, the opening is formed；Etch the pseudo- fin and
The technique of fin structure includes: anisotropic dry etch process；The parameter of the anisotropic dry etch process includes:
CH4Flow be 8 standard milliliters/minute~500 standard milliliters/minute, CHF3Flow be the mark of 30 standard milliliters/minute~200
Quasi- ml/min, radio-frequency power be 100 watts~1300 watts, bias voltage be 80 volts~500 volts, chamber pressure be 10 millitorrs~
2000 millitorrs, time are 4 seconds~500 seconds.
12. the forming method of semiconductor structure as described in claim 1, which is characterized in that formed after the contact hole, also
It include: to form metal silicide layer in the contact hole bottom；Conductive plunger is formed on the metal silicide layer.
13. the forming method of semiconductor structure as claimed in claim 12, which is characterized in that the material of the metal silicide layer
Material includes: silicon-titanium compound；The material of the conductive plunger is metal, and metal includes: tungsten.
14. the forming method of semiconductor structure as described in claim 1, which is characterized in that also have isolation in the substrate
Layer, the top surface of the separation layer is lower than the top surface of fin, and covers the partial sidewall of fin.
15. a kind of semiconductor structure characterized by comprising
Substrate, the substrate include the secondth area and the firstth area for being located at the second area two sides, and firstth area and the secondth area connect
It connects, there is the fin structure for extending to the firstth area of two sides by the secondth area, the fin structure includes at least one in the substrate
Fin；
Pseudo- fin in firstth area of fin structure two sides substrate, the puppet fin is along the extending direction perpendicular to fin
It is upper arranged in parallel with fin；
Across the gate structure of fin structure in second area's substrate；
Source and drain doping area in the fin structure and pseudo- fin of the gate structure two sides, in fin structure described in
Source and drain doping area is connected with the source and drain doping area being located in pseudo- fin；
Dielectric layer in the substrate and source and drain doping area, the side wall of the dielectric layer covering gate structure；
Contact hole in the dielectric layer, the bottom-exposed of the contact hole go out the top surface in source and drain doping area.
16. semiconductor structure as claimed in claim 15, which is characterized in that described along perpendicular on the extending direction of fin
The size of contact hole is 80 nanometers~1000 nanometers.
17. semiconductor structure as claimed in claim 15, which is characterized in that along perpendicular on the extending direction of fin, pseudo- fin
Minimum range of the portion to fin structure are as follows: 25 nanometers~100 nanometers；Along perpendicular on the extending direction of fin, the ruler of pseudo- fin
It is very little are as follows: 5 nanometers~15 nanometers.
18. semiconductor structure as claimed in claim 15, which is characterized in that the number of the fin are as follows: 1~40.
19. semiconductor structure as claimed in claim 15, which is characterized in that the number of the fin be greater than 1 when, two with
On fin along perpendicular to arranged in parallel on the extending direction of fin；Spacing between adjacent fin are as follows: 20 nanometers~50 nanometers.
20. semiconductor structure as claimed in claim 15, which is characterized in that further include: the metallic silicon positioned at contact hole bottom
Compound layer；Plug on metal silicide layer；The material of the metal silicide layer includes: silicon-titanium compound；It is described to lead
The material of electric plug is metal, and metal includes: tungsten.
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