CN103531452A - Method for forming CMOS tube - Google Patents

Method for forming CMOS tube Download PDF

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Publication number
CN103531452A
CN103531452A CN201210226457.5A CN201210226457A CN103531452A CN 103531452 A CN103531452 A CN 103531452A CN 201210226457 A CN201210226457 A CN 201210226457A CN 103531452 A CN103531452 A CN 103531452A
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source
drain region
formation method
layer
metal silicide
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CN103531452B (en
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三重野文健
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Semiconductor Manufacturing International Shanghai Corp
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Semiconductor Manufacturing International Shanghai Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28176—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the definitive gate conductor

Abstract

A method for forming a CMOS tube comprises the following steps: providing a semiconductor substrate which comprises a NMOS area and a PMOS area which is separated from the NMOS area, wherein the NMOS area is provided with a first dummy gate structure and a first source/drain area, the PMOS area is provided with a second dummy gate structure and a second source/drain area, furthermore a first mask layer covers the surfaces of the semiconductor substrate, the second source/drain area and the second dummy gate structure of the PMOS area; using the first mask layer as the mask and forming a first metal silicide layer which covers the surface of the first source/drain area; after forming a first metal silicide layer, eliminating the first mask layer; forming an interlayer dielectric layer on the surface of the semiconductor substrate, wherein the interlayer dielectric layer is level to the surfaces of the first dummy gate structure and the second dummy gate structure; etching the interlayer dielectric layer exposing an opening of partial second source/drain area; and forming a second metal silicide layer on the second source/drain area through the opening. The formed CMOS tube has a stable performance.

Description

The formation method of CMOS pipe
Technical field
The present invention relates to technical field of manufacturing semiconductors, relate in particular to a kind of formation method of CMOS pipe.
Background technology
At present, CMOS (Complementary Metal Oxide Semiconductor) pipe (Complementary Metal-Oxide-Semiconductor, CMOS) has become the basic device in chip.Described CMOS pipe comprises: P-type mos (PMOS) and N-type metal-oxide semiconductor (MOS) (NMOS).
Along with the development of semiconductor fabrication, CMOS manages continuous scaled down, to obtain the chip that integrated level is higher.In the formation method of prior art CMOS; for improving the performance of CMOS pipe; except forming stress liner layer in the source/drain region of NMOS pipe and PMOS pipe respectively; conventionally also can be after forming the grid of NMOS pipe and PMOS pipe, source/drain region; form before conductive plunger; while is in source/drain region and the gate surface in territory, nmos area, and the source/drain region in PMOS region and gate surface formation metal silicide layer, to reduce the conductive plunger of CMOS pipe and the contact resistance between source/drain region.
Yet the performance of the CMOS pipe that prior art forms is stable not.More formation methods about CMOS pipe please refer to the United States Patent (USP) that publication number is " US6489236B1 ".
Summary of the invention
The problem that the present invention solves is to provide a kind of formation method of CMOS pipe of stable performance.
For addressing the above problem, embodiments of the invention provide a kind of formation method of CMOS pipe, comprising:
Semiconductor substrate is provided, described Semiconductor substrate comprises territory, nmos area and PMOS region that is separated by with it, wherein, the semiconductor substrate surface in territory, described nmos area is formed with the first dummy gate structure, the Semiconductor substrate that is positioned at described the first dummy gate structure both sides is formed with the first source/drain region, the semiconductor substrate surface in described PMOS region is formed with the second dummy gate structure, the Semiconductor substrate that is positioned at described the second dummy gate structure both sides is formed with the second source/drain region, and the Semiconductor substrate in described PMOS region, the second source/drain region and the second dummy gate structure surface coverage have the first mask layer,
Described the first mask layer of take is mask, forms the first metal silicide layer that covers surface, described the first source/drain region;
Form after the first metal silicide layer, remove described the first mask layer;
Formation is positioned at the interlayer dielectric layer of described semiconductor substrate surface, described interlayer dielectric layer and described the first dummy gate structure and the second dummy gate structure flush;
Interlayer dielectric layer described in etching, forms the opening that exposes surface, part described the second source/drain region;
By described opening in the second source/drain region surface forms the second metal silicide layer.
Alternatively, the material of described the first metal silicide layer is NiSi 2with one or more combinations in NiSi.
Alternatively, in described the first metal silicide layer also doped with pt atom.
Alternatively, the thickness of described the first metal silicide layer is 15-50nm.
Alternatively, the formation technique of described the first metal silicide layer is depositing operation and annealing process; Or be ion doping technique.
Alternatively, described depositing operation is sputter coating process, and the parameter area of described sputter coating process is: base pressure is 5E-7 holder ~ 5E-9 holder, sputtering pressure is 0.3-0.8 handkerchief, radio-frequency power is 30 watts-80 watts, and rf frequency is 10-15 megahertz, and direct current biasing power is 3500 watts-4500 watts.
Alternatively, when adopting depositing operation to form the first metal silicide layer, it forms step and comprises: form the first metal layer that covers surface, described the first source/drain region; The first annealing in process is carried out in described the first source/drain region and the first metal layer.
Alternatively, the process parameters range of described the first annealing process is: annealing temperature is 300 degrees Celsius-750 degrees Celsius, and annealing time is 5 minutes-60 minutes.
Alternatively, described the first annealing process is rapid thermal anneal process, and its process parameters range is: annealing temperature is 700 degrees Celsius-900 degrees Celsius, and annealing time is 10 seconds-120 seconds.
Alternatively, the material of described the first metal layer is Ni or NiPt.
Alternatively, when the material of described the first metal layer is NiPt, Pt is less than 5% at the atom percentage content of NiPt.
Alternatively, also comprise: after completing described the first annealing in process, remove described the first metal layer.
Alternatively, the Area Ratio that the surface, part the second source/drain region that described opening exposes accounts for surface, the second total source/drain region is 1:3 ~ 1:10.
Alternatively, the material of described the second metal silicide layer is NiSi 2with one or more combinations in NiSi.
Alternatively, the formation technique of described the second metal silicide layer is depositing operation and annealing process; Or be ion doping technique.
Alternatively, described depositing operation is atom layer deposition process, and the reactant of employing is: two (dimethylamino-2-methyl-2-butoxy) nickel, hydrogen and ammonia, depositing temperature is 200 degrees Celsius-400 degrees Celsius.
Alternatively, when adopting depositing operation to form described the second metal silicide layer, it forms step and comprises: surface, the second source in described opening/drain region forms the second metal level; The second annealing in process is carried out in described the second source/drain region and the second metal level.
Alternatively, the process parameters range of described the second annealing in process is: annealing temperature is 450 degrees Celsius-700 degrees Celsius, and annealing time is 20 seconds-60 seconds.
Alternatively, also comprise: after completing described the second annealing in process, remove described the second metal level.
Alternatively, also comprise: before etching interlayer dielectric layer forms opening, remove described the first dummy gate structure, and the position after removing the first dummy gate structure forms first grid structure; And remove described the second dummy gate structure, in the position of removing described the second dummy gate structure, form second grid structure.
Alternatively, also comprise: the second metal silicide layer surface in described opening forms conductive plunger.
Alternatively, the material of described conductive plunger is tungsten, copper, ruthenium, titanium nitride or tantalum nitride.
Compared with prior art, technical scheme of the present invention has the following advantages:
Because surface, the first source in territory, nmos area/drain region forms the first metal silicide layer, the step that forms the second metal silicide layer on the surface, the second source/drain region in PMOS region is separately carried out, and the second metal silicide layer is only formed on surface, part the second source/drain region, and embed in the second source/drain region, not only can reduce the second source/drain region and the contact resistance between corresponding conductive plunger with it, also improved the compression of PMOS pipe channel region, the carrier mobility of described PMOS pipe channel region is raise, finally form the CMOS pipe of stable performance.
Further, the Area Ratio that the surface, part the second source/drain region that described opening exposes accounts for surface, the second total source/drain region is 1:3 ~ 1:10, the Area Ratio on described the second metal silicide layer surface area and total surface, the second source/drain region is 1:3 ~ 1:10, contact resistance between the conductive plunger of the second source/drain region and with it correspondence is little, and the compression of PMOS pipe channel region is large, the carrier mobility of described PMOS pipe channel region raises, and the CMOS pipe performance of formation is more stable.
Accompanying drawing explanation
Fig. 1-Fig. 9 is the cross-sectional view of forming process of the CMOS pipe of the embodiment of the present invention.
Embodiment
The performance of the CMOS pipe that as described in background, prior art forms is stable not.
Through research, inventor finds, prior art is when forming CMOS pipe, the metal silicide layer of PMOS pipe and NMOS pipe forms in same step, conventionally the metal silicide layer forming not only covers the whole source/drain region of NMOS pipe, also cover the whole source/drain region of PMOS pipe, source/the drain region of PMOS pipe and the contact resistance between conductive plunger have been increased, and the compression of PMOS pipe channel region also reduces, the carrier mobility of described PMOS pipe channel region is reduced, finally affect the performance of CMOS pipe.
After further research, inventor finds, the step that forms metal silicide layer when the source/drain region of the source/drain region at NMOS pipe, PMOS pipe is separately carried out, and while only forming metal silicide layer on the surface, part source/drain region of PMOS pipe, not only can reduce the source/drain region of PMOS pipe and the contact resistance between conductive plunger, but also contribute to improve the compression of PMOS pipe channel region, and the carrier mobility of described PMOS pipe channel region is reduced, finally form the CMOS pipe of stable performance.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.
Concrete, please refer to Fig. 1-Fig. 9, Fig. 1-Fig. 9 shows the cross-sectional view of the forming process of CMOS pipe of the present invention.
Please refer to Fig. 1, Semiconductor substrate 200 is provided, described Semiconductor substrate comprises territory, nmos area I and is separated by PMOS region II with it, wherein, Semiconductor substrate 200 surfaces of described nmos area territory I are formed with the first dummy gate structure 201, the Semiconductor substrate 200 that is positioned at described the first dummy grid 201 structure both sides is formed with the first source/drain region 203, Semiconductor substrate 200 surfaces of described PMOS region II are formed with the second dummy gate structure 205, the Semiconductor substrate 200 that is positioned at described the second dummy gate structure 205 both sides is formed with the second source/drain region 207, and the Semiconductor substrate 200 of described PMOS region II, the second source/drain region 207 and the second dummy gate structure 205 surface coverage have the first mask layer 209.
Described Semiconductor substrate 200 is used to subsequent technique that workbench is provided.Described Semiconductor substrate 200 is body silicon or silicon-on-insulator (SOI), and the material of described Semiconductor substrate 200 is monocrystalline silicon, SiGe, silicon-carbon or III-V compounds of group (such as gallium arsenic, indium phosphide and gallium nitride etc.).Described Semiconductor substrate 200 comprises territory, nmos area I and PMOS region II, and both isolate 200a by shallow ditch groove structure, is respectively used to form NMOS pipe and PMOS pipe.In an embodiment of the present invention, described Semiconductor substrate 200 is silicon substrate, and in the Semiconductor substrate 200 of described nmos area territory I, doped with p-type ion, the Semiconductor substrate 200 of PMOS region II is interior doped with N-shaped ion.
Described the first dummy gate structure 201 is removed for follow-up, to form first grid structure.Described the first dummy gate structure 201 is single layer structure or multiple-level stack structure.In an embodiment of the present invention, described the first dummy gate structure 201 is multiple-level stack structure, described the first dummy gate structure 201 is for being positioned at the first pseudo-gate electrode layer (not shown) on Semiconductor substrate 200 surfaces of described nmos area territory I, and the material of described the first pseudo-gate electrode layer is polysilicon.
It should be noted that, in the formation method of the CMOS of embodiment of the present invention pipe, also comprise: the first hard mask layer 202 that covers described the first dummy gate structure 201 both sides; Be formed at the first side wall 204 of described the first dummy gate structure 201 both sides.
Wherein, the material of described the first hard mask layer 202 is silicon oxynitride, silicon nitride or silica; for forming the first dummy gate structure 201 as mask; and in subsequent technique as the mask of the first dummy gate structure 201; protect the first dummy gate structure 201 not to be destroyed in the techniques such as follow-up doping or etching; the material of described the first side wall 204 is silicon oxynitride, silicon nitride or silica; for the protection of the first dummy gate structure 201, be not destroyed, and the mask when as follow-up formation first source/drain region 203.In an embodiment of the present invention, the material of described the first hard mask layer 202 is silicon oxynitride, and the material of described the first side wall 204 is silicon nitride.
Described the first source/drain region 203 is as the source/drain electrode that forms NMOS pipe.In an embodiment of the present invention, the formation step in described the first source/drain region 203 comprises: take described the first hard mask layer 202, the first side wall 204 is mask, and the Semiconductor substrate 200 of territory, nmos area I, forms the first source/drain region opening (not shown) described in etching; To filling full the first stress liner layer (not indicating) in the opening of described the first source/drain region, for example fill SiC, for the channel region of NMOS pipe provides tension stress, increase the carrier mobility of its channel region; To Implanted n-Type ion in described the first stress liner layer.
Described the second dummy gate structure 205 is removed for follow-up, to form second grid structure.The structure and material of described the second dummy gate structure 205 is identical with described the first dummy gate structure 201, specifically please refer to the associated description of relevant the first dummy gate structure 201 in the embodiment of the present invention, does not repeat them here.
Accordingly, in the formation method of the CMOS pipe of the embodiment of the present invention, also comprise: the second hard mask layer 206 that covers described the second dummy gate structure 205 both sides; Be formed at the first side wall 208 of described the second dummy gate structure 205 both sides.The material of described the second hard mask layer 206, the second side wall 208, effect etc. please refer to the associated description of the first hard mask layer 202, the first side wall 204 in the embodiment of the present invention, do not repeat them here.
Described the second source/drain region 207 is as the source/drain electrode that forms PMOS pipe.In an embodiment of the present invention, the formation step in described the second source/drain region 207 comprises: take described the second hard mask layer 206, the second side wall 208 is mask, and the Semiconductor substrate 200 of PMOS region II, forms the second source/drain region opening (not shown) described in etching; To filling full the second stress liner layer (not indicating) in the opening of described the second source/drain region, for example fill SiGe, for the channel region of PMOS pipe provides compression, increase the carrier mobility of its channel region; In described the second stress liner layer, inject p-type ion.
Described the first mask layer 209 is for follow-up as mask, and in the first source/drain region, 203 surfaces form the first metal silicide layer.In an embodiment of the present invention, described the first source/drain region 203 is forming the rear formation in the second source/drain region 207, and described the first mask layer 209 can also be used as the mask while forming first source/drain region 203.
Please refer to Fig. 2, described the first mask layer 209 of take is mask, forms the first metal layer 211 that covers surface, described the first source/drain region 203.
The material of described the first metal layer 211 is Ni or NiPt, and the pasc reaction during for subsequent anneal in the metal of the first metal layer 211 and the first source/drain region 203, forms the first metal silicide layer.In an embodiment of the present invention, the material of described the first metal layer 211 is NiPt, and for reducing the first source/drain region 203 of follow-up formation and the contact resistance between conductive plunger, Pt is less than 5% at the atom percentage content of NiPt.
The formation technique of described the first metal layer 211 is depositing operation, sputter coating (sputtering) technique for example, under vacuum (vacuum) condition, adopting target (sputter modules) is high-purity nickel target (Ni module) or nickel platinum target (NiPt module), adopting vector gas (carrier gas) is argon gas (Ar) or helium (He), the thickness controllability of the first metal layer 211 forming is good, purity Gao， dense structure.In embodiments of the invention, the thickness that adopts sputter coating process to form the first metal layer 211 is 10-20nm, its process parameters range is: base pressure is 5E-7 holder ~ 5E-9 holder, sputtering pressure is 0.3-0.8 handkerchief, radio-frequency power is 30 watts-80 watts, rf frequency is 10-15 megahertz, and direct current biasing power is 3500 watts-4500 watts.The better quality of the first metal layer 211 that sputter forms in this process parameters range.
Please refer to Fig. 3, to described the first source/drain region 203(as shown in Figure 2) and the first metal layer 211(is as shown in Figure 2) carry out the first annealing in process, form the first metal silicide layer 213 that covers 203a surface, described the first source/drain region.
Described the first annealing in process is used for making the first source/drain region 203 and the first metal layer 211 to react, metal in described the first metal layer 211 enters 203 inside, the first source/drain region, on the surface of described the first source/drain region 203a, forms the first metal silicide layer 213.In an embodiment of the present invention, described the first annealing (1 stannealing) technological parameter (parameters) of processing is: annealing temperature is 300 degrees Celsius-750 degrees Celsius, annealing time is 5 minutes-60 minutes, the thickness of the first metal silicide layer 213 forming is 10-20nm, both effectively reduced the contact resistance between the first source/drain region 203a and corresponding conductive plunger, be beneficial to again and form the CMOS pipe that size is little, be beneficial to integrated.
It should be noted that, in other embodiments of the invention, described the first annealing in process can also be rapid thermal anneal process (Rapid Thermal Annealing, RTA), when adopting rapid thermal anneal process to described the first source/drain region 203 and the first metal layer 211 annealing, annealing temperature is 700 degrees Celsius-900 degrees Celsius, and annealing time is 10 seconds-120 seconds, has greatly saved the process time.
Because the first metal layer 211 covers whole the first source/drain region 203a surface, the first metal silicide layer 213 of formation covers whole the first source/drain region 203a surface, for the contact resistance between follow-up reduction the first source/drain region 203a and conductive plunger.In an embodiment of the present invention, adopt after above-mentioned the first annealing in process, the material of the first metal silicide layer 213 of formation is NiSi 2and NiSi, and be also formed with pt atom in described the first metal silicide layer 213, effectively reduce the contact resistance between the first source/drain region 203a and conductive plunger.
It should be noted that, in other embodiments of the invention, the material of the first metal silicide layer 213 of formation can also be NiSi 2or NiSi.
In an embodiment of the present invention, treat described the first annealing in process, formed after the first metal silicide layer 213, removed described the first metal layer 211.Owing to removing the technique of described the first metal layer 211, be well known to those skilled in the art, do not repeat them here.
It should be noted that, in other embodiments of the invention, the formation technique of described the first metal silicide layer 213 can also be: doping process.Its concrete grammar is: to described the first source/drain region 203(as shown in Figure 3) top layer doping nickel ion.Because those skilled in the art know, how to adopt doping process to form the first metal silicide layer 213, do not repeat them here.
Please refer to Fig. 4, form after the first metal silicide layer 213, remove described the first mask layer 209(as shown in Figure 3).
Remove described the first mask layer 209, be beneficial to follow-up formation interlayer dielectric layer.Because the technique of described the first mask layer 209 of described removal is well known to those skilled in the art, do not repeat them here.
Please refer to Fig. 5, form the interlayer dielectric layer 215 that is positioned at described Semiconductor substrate 200 surfaces, described interlayer dielectric layer 215 and described the first dummy gate structure 201 and the second dummy gate structure 205 flush.
Described interlayer dielectric layer 215 is for isolating the metal-oxide-semiconductor of adjacent area.The material of described interlayer dielectric layer 215 is silica, silicon nitride or silicon oxynitride.In an embodiment of the present invention, the material of described interlayer dielectric layer 215 is silica.
The formation technique of described interlayer dielectric layer 215 is depositing operation, for example physics or chemical vapor deposition method.In embodiments of the invention, the formation step of described interlayer dielectric layer 215 comprises: form the interlayer medium film (not shown) that covers described Semiconductor substrate 200, the first metal silicide layer 213, the first dummy gate structure 201, the second dummy gate structure 205 and 207 surfaces, the second source/drain region; Interlayer medium film described in chemico-mechanical polishing, until expose described the first dummy gate structure 201 and the second dummy gate structure 205.
It should be noted that, in the processing step of chemico-mechanical polishing, described the first hard mask layer 202, the second hard mask layer 206 are also removed.Described interlayer dielectric layer 215 also exposes the top of the first side wall 204 and the second side wall 206.
Please refer to Fig. 6, remove described the first dummy gate structure 201(as shown in Figure 5), and the position after removing the first dummy gate structure 201 forms first grid structure 216; And remove described the second dummy gate structure 205, in the position of removing described the second dummy gate structure 205, form second grid structure 218.
The technique of removing described the first dummy gate structure 201 and the second dummy gate structure 205 is well known to those skilled in the art, does not repeat them here.
Described first grid structure 216 comprises the first high-K gate dielectric layer (not shown) that is positioned at described Semiconductor substrate 200 surfaces and the first metal gate electrode layer (not shown) that covers described the first high-K gate dielectric layer surface; Described second grid structure 218 comprises the second high-K gate dielectric layer (not shown) that is positioned at described Semiconductor substrate 200 surfaces and the second metal gate electrode layer (not shown) that covers described the second high-K gate dielectric layer surface.Wherein, the material of described the first high-K gate dielectric layer, the second high-K gate dielectric layer is HfO 2, HfSiO, HfSiNO or ZrO 2deng, described the first metal gate electrode layer, the second metal gate electrode layer are the stacking structure of single or multiple lift, its material is one or more in aluminium (Al), copper (Cu), silver (Ag) or tungsten (W).
Please refer to Fig. 7, form after first grid structure 216 and second grid structure 218, interlayer dielectric layer 215 described in etching, forms the opening 217a that exposes 207 surfaces, described the second source/drain region of part.
Described opening 217a exposes 207 surfaces, part the second source/drain region, for the follow-up process window as forming the second metal silicide layer and conductive plunger.The formation technique of described opening 217a is etching technics, and for example anisotropic dry etch process, is well known to those skilled in the art owing to forming the technique of opening 217a, does not repeat them here.
Inventor finds, if described opening 217a exposes 207 surfaces, whole the second source/drain region, the second metal silicide layer of so follow-up formation covers 207 surfaces, whole the second source/drain region, be unfavorable for reducing the contact resistance between the second source/drain region 207 and the conductive plunger corresponding with it, and the conductive plunger cross-sectional area forming is too large; If 207 surfaces, the second source/drain region that described opening 217a exposes are too small, the conductive plunger cross-sectional area of follow-up formation is too little, be unfavorable for peripheral circuit between be connected.Through research, inventor finds, when the Area Ratio that accounts for 207 surfaces, total the second source/drain region when 207 surfaces, the second source/drain region that described opening 217a exposes is 1:3 ~ 1:10, the second metal silicide layer of follow-up formation can effectively reduce the contact resistance between the conductive plunger corresponding with it of the second source/drain region 207.
It should be noted that, in embodiments of the invention, except the interior formation opening of interlayer dielectric layer 215 217a, also in territory, described nmos area and PMOS region, form opening 217b, described opening 217b exposes 207 surfaces, part the second source/drain region, the first metal silicide layer 213 surfaces and fleet plough groove isolation structure 200a surface simultaneously, for follow-up formation the second metal silicide layer and conductive plunger, to save processing step, and reduce the technology difficulty of follow-up formation the second metal silicide layer and conductive plunger.In the embodiment of the present invention, the ratio that part the second source/drain region 207 surface areas that described opening 217b exposes account for the area on 207 surfaces, total the second source/drain region is also 1:3 ~ 1:10.
It should be noted that, in embodiments of the invention, also comprise: at the interior formation opening of described interlayer dielectric layer 215 217c, described opening 217c exposes part the first metal silicide layer 213 surfaces, for follow-up formation, connect the conductive plunger in peripheral circuit and the first source/drain region 203.
Please refer to Fig. 8, by described opening 217a, in the second source/drain region, 207 surfaces form the second metal silicide layer 219.
Described the second metal silicide layer 219 is for follow-up reduction the second source/drain region 207 and the contact resistance between corresponding conductive plunger with it.The material of described the second metal silicide layer 219 is NiSi 2with one or more in NiSi.The formation technique of described the second metal silicide layer 219 is depositing operation and annealing process; Or be ion doping technique.
When forming the technique of the second metal silicide layer 219 and be depositing operation and annealing process, for the quality of the second metal silicide layer 219 of making to form is good, described depositing operation is ald (ALD) technique.The processing step of described formation the second metal silicide layer 219 comprises: adopt second source/drain region 207 surfaces of atom layer deposition process (ALD) in described opening 217a to form the second metal level (not shown); The second annealing in process (2 is carried out in described the second source/drain region 207 and the second metal level ndannealing).Wherein, the material of described the second metal level is Ni or NiPt; For forming measured the second metal level of matter, the reactant that described atom layer deposition process adopts is: two (dimethylamino-2-methyl-2-butoxy) nickel (bia (dimethylamino-2-methyl-2-butoxo) nickel), hydrogen (H 2) and ammonia (NH 3), depositing temperature is 200 degrees Celsius-400 degrees Celsius; Described the second annealing in process (2 ndannealing) technological parameter time (parameters) scope is that annealing temperature is 450 degrees Celsius-700 degrees Celsius, annealing time is 20 seconds-60 seconds, the thickness of the second metal silicide layer 219 forming is 10-20nm, both effectively reduced the contact resistance between the second source/drain region 207 and corresponding conductive plunger, be beneficial to again and form the CMOS pipe that size is little, be beneficial to integrated.
Due to the opening 217a in interlayer dielectric layer 215, the Area Ratio that part the second Yuan/Lou 207 surfaces, district that opening 217b exposes account for 207 surfaces, total the second source/drain region is 1:3 ~ 1:10, the Area Ratio that the surface area of the second metal silicide layer 219 forming accounts for 207 surfaces, total the second source/drain region is 1:3 ~ 1:10, the second metal silicide layer 219 that described area is little is embedded in the second source/drain region 207, except reducing the second source/drain region 207 and with it the contact resistance between corresponding conductive plunger, can also introduce compression in the channel region of PMOS pipe, improve the carrier mobility of the channel region of PMOS pipe, further improve the stability of CMOS pipe.
It should be noted that, in an embodiment of the present invention, Semiconductor substrate 200 surfaces or the first metal silicide layer 213 surfaces that are also included in described opening 217b and opening 217c form the second metal level, then described the second metal level is carried out to the second annealing in process, form the second metal silicide layer 219.Through described the second annealing in process, in the first metal silicide layer 213 that opening 217b and opening 217c expose, also have metallic atom and enter, can further reduce the first source/drain region 203 and the contact resistance between corresponding conductive plunger with it.
It should be noted that, after completing described the second annealing in process, form after the second metal silicide layer 219, remove described the second metal level.Owing to removing the technique of described the second metal level, be well known to those skilled in the art, do not repeat them here.
Please refer to Fig. 9, the second metal silicide layer 219 surfaces in described opening 217a form conductive plunger 221a.
Described conductive plunger 221a is used for being electrically connected to the second source/drain region 207 and peripheral circuit.The material of described conductive plunger 221a is tungsten, copper, ruthenium, titanium nitride or tantalum nitride.The formation technique of described conductive plunger 221a is depositing operation, owing to forming material and the technique of described conductive plunger 221a, is well known to those skilled in the art, and does not repeat them here.
It should be noted that, in embodiments of the invention, also comprise: the second metal silicide layer 219 in described opening 217b and the first metal silicide layer 213 surfaces form conductive plunger 221b, for being electrically connected to the second source/drain region 207, the first source/drain region 203 and corresponding peripheral circuit; The first metal silicide layer 213 surfaces in described opening 217c form conductive plunger 221c, for being electrically connected to the first source/drain region 203 and corresponding peripheral circuit.
After above-mentioned steps completes, the completing of the CMOS pipe of the embodiment of the present invention.Because surface, the first source in territory, nmos area/drain region forms the first metal silicide layer, the step that forms the second metal silicide layer on the surface, the second source/drain region in PMOS region is separately carried out, and the second metal silicide layer is only formed on surface, part the second source/drain region, and embed in the second source/drain region, not only can reduce the second source/drain region and the contact resistance between corresponding conductive plunger with it, also improved the compression of PMOS pipe channel region, the carrier mobility of described PMOS pipe channel region is raise, finally form the CMOS pipe of stable performance.
Further, the Area Ratio that the surface, part the second source/drain region that described opening exposes accounts for surface, the second total source/drain region is 1:3 ~ 1:10, the Area Ratio on described the second metal silicide layer surface area and total surface, the second source/drain region is 1:3 ~ 1:10, contact resistance between the conductive plunger of the second source/drain region and with it correspondence is little, and the compression of PMOS pipe channel region is large, the carrier mobility of described PMOS pipe channel region raises, and the CMOS pipe performance of formation is more stable.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can utilize method and the technology contents of above-mentioned announcement to make possible change and modification to technical solution of the present invention; therefore; every content that does not depart from technical solution of the present invention; any simple modification, equivalent variations and the modification above embodiment done according to technical spirit of the present invention, all belong to the protection range of technical solution of the present invention.

Claims (22)

1. a formation method for CMOS pipe, is characterized in that, comprising:
Semiconductor substrate is provided, described Semiconductor substrate comprises territory, nmos area and PMOS region that is separated by with it, wherein, the semiconductor substrate surface in territory, described nmos area is formed with the first dummy gate structure, the Semiconductor substrate that is positioned at described the first dummy gate structure both sides is formed with the first source/drain region, the semiconductor substrate surface in described PMOS region is formed with the second dummy gate structure, the Semiconductor substrate that is positioned at described the second dummy gate structure both sides is formed with the second source/drain region, and the Semiconductor substrate in described PMOS region, the second source/drain region and the second dummy gate structure surface coverage have the first mask layer,
Described the first mask layer of take is mask, forms the first metal silicide layer that covers surface, described the first source/drain region;
Form after the first metal silicide layer, remove described the first mask layer;
Formation is positioned at the interlayer dielectric layer of described semiconductor substrate surface, described interlayer dielectric layer and described the first dummy gate structure and the second dummy gate structure flush;
Interlayer dielectric layer described in etching, forms the opening that exposes surface, part described the second source/drain region;
By described opening in the second source/drain region surface forms the second metal silicide layer.
2. the formation method of CMOS pipe as claimed in claim 1, is characterized in that, the material of described the first metal silicide layer is NiSi 2with one or more combinations in NiSi.
3. the formation method of CMOS pipe as claimed in claim 1, is characterized in that, in described the first metal silicide layer also doped with pt atom.
4. the formation method of CMOS pipe as claimed in claim 1, is characterized in that, the thickness of described the first metal silicide layer is 15-50nm.
5. the formation method of CMOS pipe as claimed in claim 1, is characterized in that, the formation technique of described the first metal silicide layer is depositing operation and annealing process; Or be ion doping technique.
6. the formation method of CMOS pipe as claimed in claim 5, it is characterized in that, described depositing operation is sputter coating process, the parameter area of described sputter coating process is: base pressure is 5E-7 holder ~ 5E-9 holder, sputtering pressure is 0.3-0.8 handkerchief, radio-frequency power is 30 watts-80 watts, and rf frequency is 10-15 megahertz, and direct current biasing power is 3500 watts-4500 watts.
7. the formation method of CMOS pipe as claimed in claim 5, is characterized in that, when adopting depositing operation to form the first metal silicide layer, it forms step and comprises: form the first metal layer that covers surface, described the first source/drain region; The first annealing in process is carried out in described the first source/drain region and the first metal layer.
8. the formation method of CMOS pipe as claimed in claim 7, is characterized in that, the process parameters range of described the first annealing process is: annealing temperature is 300 degrees Celsius-750 degrees Celsius, and annealing time is 5 minutes-60 minutes.
9. the formation method of CMOS pipe as claimed in claim 7, is characterized in that, described the first annealing process is rapid thermal anneal process, and its process parameters range is: annealing temperature is 700 degrees Celsius-900 degrees Celsius, and annealing time is 10 seconds-120 seconds.
10. the formation method of CMOS pipe as claimed in claim 7, is characterized in that, the material of described the first metal layer is Ni or NiPt.
The formation method of 11. CMOS pipes as claimed in claim 7, is characterized in that, when the material of described the first metal layer is NiPt, Pt is less than 5% at the atom percentage content of NiPt.
The formation method of 12. CMOS pipes as claimed in claim 7, is characterized in that, also comprises: after completing described the first annealing in process, remove described the first metal layer.
The formation method of 13. CMOS pipes as claimed in claim 1, is characterized in that, the Area Ratio that the surface, part the second source/drain region that described opening exposes accounts for surface, the second total source/drain region is 1:3 ~ 1:10.
The formation method of 14. CMOS pipes as claimed in claim 1, is characterized in that, the material of described the second metal silicide layer is NiSi 2with one or more combinations in NiSi.
The formation method of 15. CMOS pipes as claimed in claim 1, is characterized in that, the formation technique of described the second metal silicide layer is depositing operation and annealing process; Or be ion doping technique.
The formation method of 16. CMOS pipes as claimed in claim 15, it is characterized in that, described depositing operation is atom layer deposition process, and the reactant of employing is: two (dimethylamino-2-methyl-2-butoxy) nickel, hydrogen and ammonia, depositing temperature is 200 degrees Celsius-400 degrees Celsius.
The formation method of 17. CMOS pipes as claimed in claim 15, is characterized in that, when adopting depositing operation to form described the second metal silicide layer, it forms step and comprises: surface, the second source in described opening/drain region forms the second metal level; The second annealing in process is carried out in described the second source/drain region and the second metal level.
The formation method of 18. CMOS pipes as claimed in claim 17, is characterized in that, the process parameters range of described the second annealing in process is: annealing temperature is 450 degrees Celsius-700 degrees Celsius, and annealing time is 20 seconds-60 seconds.
The formation method of 19. CMOS pipes as claimed in claim 17, is characterized in that, also comprises: after completing described the second annealing in process, remove described the second metal level.
The formation method of 20. CMOS pipes as claimed in claim 1, is characterized in that, also comprises: before etching interlayer dielectric layer forms opening, remove described the first dummy gate structure, and the position after removing the first dummy gate structure forms first grid structure; And remove described the second dummy gate structure, in the position of removing described the second dummy gate structure, form second grid structure.
The formation method of 21. CMOS pipes as claimed in claim 1, is characterized in that, also comprises: the second metal silicide layer surface in described opening forms conductive plunger.
The formation method of 22. CMOS pipes as claimed in claim 21, is characterized in that, the material of described conductive plunger is tungsten, copper, ruthenium, titanium nitride or tantalum nitride.
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