CN105097519A - Formation method of semiconductor structure - Google Patents
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- CN105097519A CN105097519A CN201410182739.9A CN201410182739A CN105097519A CN 105097519 A CN105097519 A CN 105097519A CN 201410182739 A CN201410182739 A CN 201410182739A CN 105097519 A CN105097519 A CN 105097519A
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Abstract
A formation method of a semiconductor structure comprises the steps of providing a substrate, wherein a plurality of grooves are arranged in the substrate, the substrate between the adjacent grooves forms a fin part, and the tops of the fin parts are equipped with the mask layers; by taking the mask layers as masks, adopting an ion implantation technology to inject the medium ions in the substrate at the bottoms of the grooves; adopting an annealing process to enable the medium ions and the material of the substrate to react, and forming first dielectric layers on the bottom surfaces of the grooves; forming second dielectric layers on the surfaces of the first dielectric layers at the bottoms of the grooves, wherein the surfaces of the second dielectric layers are lower than the top surfaces of the fin parts. The formed semiconductor structure is good in morphology, and the performance of the formed semiconductor structure is improved.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly relate to a kind of formation method of semiconductor structure.
Background technology
Along with the develop rapidly of semiconductor fabrication, semiconductor device is towards higher component density, and the future development of higher integrated level.Transistor is just being widely used at present as the most basic semiconductor device, therefore along with the component density of semiconductor device and the raising of integrated level, the grid size of planar transistor is also shorter and shorter, the control ability of traditional planar transistor to channel current dies down, produce short-channel effect, produce leakage current, finally affect the electric property of semiconductor device.
In order to overcome the short-channel effect of transistor, suppress leakage current, prior art proposes fin formula field effect transistor (FinFET).Fin formula field effect transistor is a kind of common multi-gate device.
As shown in Figure 1, be a kind of structural representation of fin formula field effect transistor, comprise: Semiconductor substrate 100; Be positioned at the fin 101 on Semiconductor substrate 100 surface; Be positioned at the dielectric layer 102 on Semiconductor substrate 100 surface, the sidewall of fin 101 described in described dielectric layer 102 cover part, and dielectric layer 102 surface is lower than fin 101 top; Be positioned at dielectric layer 102 surface and the top of fin 101 and the grid structure 103 of sidewall surfaces; Be positioned at source region 104a and the drain region 104b of the fin 101 of described grid structure 103 both sides.
But, easily produce leakage current in existing fin formula field effect transistor, cause the unstable properties of fin formula field effect transistor.
Summary of the invention
The problem that the present invention solves is to provide a kind of formation method of semiconductor structure, and the fin formula field effect transistor leakage current formed reduces, performance improvement.
For solving the problem, the invention provides a kind of formation method of semiconductor structure, comprising: provide substrate, having some grooves in described substrate, the substrate between adjacent trenches forms fin, and the top of described fin has mask layer; With described mask layer for mask, adopt ion implantation technology injected media ion in the substrate of described channel bottom; Adopt annealing process that the material of described medium ionic and substrate is reacted, form first medium layer in described trench bottom surfaces; Form second dielectric layer on the first medium layer surface of described channel bottom, the surface of described second dielectric layer is lower than the top surface of described fin.
Optionally, the parameter of described ion implantation technology comprises: Doped ions is oxonium ion, and Implantation Energy is 0KeV ~ 20KeV, and implantation dosage is 1E16atom/cm
2~ 1E17atom/cm
2, implant angle perpendicular to substrate surface, be 90 °, the injection degree of depth is 0nm ~ 50nm.
Optionally, the parameter of described annealing process comprises: gas nitrogen, argon gas or helium, and temperature is 1200 DEG C ~ 1400 DEG C, and the time is 30 minutes ~ 120 minutes.
Optionally, the formation method of described second dielectric layer comprises: the first medium layer surface in groove and mask layer surface form the second medium film of filling full groove; Described in planarization, second medium film is till exposing mask layer, in groove, form second dielectric layer; Return the described second dielectric layer of etching, till top surface lower than fin of the surface of described second dielectric layer.
Optionally, the material of described second medium film is silica, and the formation process of described second medium film is fluid chemistry gas-phase deposition.
Optionally, before returning the described second dielectric layer of etching, described mask layer is removed.
Optionally, the technique removing described mask layer is wet-etching technology, and etching liquid is hydrofluoric acid solution and phosphoric acid solution, in described hydrofluoric acid solution, the volume ratio of water and hydrofluoric acid is 50:1 ~ 100:1, and the concentration of hydrofluoric acid is less than 49%, and the mass percent concentration of described phosphoric acid solution is 85%.
Optionally, also comprise: before the described second medium film of formation, form laying on the sidewall surfaces of described groove, the first medium layer surface of channel bottom and mask layer surface, described second medium film is formed at described laying surface.
Optionally, the material of described laying is silica, and the formation process of described laying is that on-the-spot steam generates annealing process.
Optionally, described time etching technics is remote plasma chemical drying method etching technics, comprising: etching gas comprises NF
3and NH
3, NF
3with NH
3flow-rate ratio be 1:20 ~ 5:1, etching temperature is 40 degrees Celsius ~ 80 degrees Celsius, pressure be 0.5 holder ~ 50 hold in the palm, power is less than 100 watts, and frequency is less than 100 KHz.
Optionally, described mask layer comprises silicon nitride layer.
Optionally, described mask layer also comprises the silicon oxide layer between described silicon nitride layer and fin portion surface.
Optionally, the formation process of described groove comprises: form mask layer at substrate surface, and described mask layer covers the substrate surface needing to form fin; With described mask layer for mask, etch described substrate, in substrate, form groove.
Optionally, the formation process of described mask layer is multiple graphical masking process.
Optionally, the quantity of described groove is more than or equal to 2, and the degree of depth of described groove is 90 nanometer ~ 130 nanometers.
Optionally, the thickness of described first medium layer is 100 dust ~ 1000 dusts, and the thickness of described second dielectric layer is 2500 dust ~ 500 dusts.
Optionally, also comprise: form at second dielectric layer surface and the sidewall of fin and top surface the grid structure being across described fin.
Optionally, described grid structure comprises: be positioned at the sidewall of second dielectric layer surface and fin and the gate dielectric layer of lower surface, be positioned at the grid layer on gate dielectric layer surface, and be positioned at the side wall of grid layer and gate dielectric layer sidewall surfaces.
Compared with prior art, technical scheme of the present invention has the following advantages:
In formation method of the present invention, by injected media ion in the substrate of channel bottom, and the material of medium ionic and substrate is reacted generate first medium layer, then the formed channel bottom of first medium layer between adjacent fin by annealing.Afterwards, second dielectric layer is formed on the first medium layer surface of described channel bottom, described second dielectric layer and first medium layer are jointly as the isolation structure between adjacent fin, therefore described isolation structure has larger thickness, the follow-up electric field be formed between the grid structure on second dielectric layer surface and substrate is reduced, make not easily to puncture between described grid structure and substrate, avoid between described grid structure and substrate and produce leakage current, then the stable performance of formed fin field effect pipe.Secondly, by ion implantation technology at channel bottom injected media ion, and form first medium layer by annealing process, then described first medium layer accurately can be controlled by described ion implantation technology perpendicular to the profile graphics of substrate surface, make the contact interface quality between described first medium layer and fin good, the profile graphics pattern of described first medium layer is accurate.Especially, bottom described first medium layer to the corner of sidewall and contact interface between described substrate and fin sidewall good, therefore described first medium layer has good electric isolution ability.Again, total height due to described fin equals the height of described fin higher than second dielectric layer surface and the thickness summation of second dielectric layer, therefore the total height of described fin can be reduced, namely formed gash depth can reduce, the depth-to-width ratio of described groove reduces, make described second dielectric layer easily be formed at channel bottom, and the second dielectric layer quality formed is better, interior solid.Therefore the electric isolution of described second dielectric layer and first medium layer is functional.
Accompanying drawing explanation
Fig. 1 is a kind of structural representation of fin formula field effect transistor;
Fig. 2 is the cross-sectional view of Fig. 1 along AA ' direction;
Fig. 3 to Figure 10 is the section knot schematic diagram of the forming process of the semiconductor structure of the embodiment of the present invention.
Embodiment
As stated in the Background Art, in existing fin formula field effect transistor, easily produce leakage current, cause the unstable properties of fin formula field effect transistor.
Find through research, please refer to Fig. 2, Fig. 2 is the cross-sectional view of Fig. 1 along AA ' direction, wherein, grid structure 103 is mutually isolated by dielectric layer 102 and Semiconductor substrate 100, in order to avoid described dielectric layer 102 is breakdown and make to produce between grid structure 103 and Semiconductor substrate 100 leakage current, described dielectric layer 102 needs to have the adequate thickness H1 meeting design requirement.Meanwhile, described fin 101 also needs to meet design requirement higher than the height H 2 on dielectric layer 102 surface, makes fin field effect pipe have enough large channel region width, stablizes with guaranteed performance.Therefore, the height H needed for described fin 101 is larger.
But along with the integrated level of integrated circuit improves, the size of semiconductor device constantly reduces, device density improves constantly, distance L between adjacent fin 101 reduces, and the height H of described fin 101 is comparatively large, causes the groove depth-to-width ratio between adjacent fin 101 larger.And the formation process of described dielectric layer 102 comprises: after Semiconductor substrate 100 surface forms fin 101, depositing operation is adopted to form deielectric-coating in Semiconductor substrate 100 and fin 101 surface; Deielectric-coating described in planarization, till exposing fin 101 top surface, forms dielectric layer; Return the described dielectric layer of etching, make the surface of described dielectric layer lower than the top surface of fin 101.
When groove depth-to-width ratio between adjacent fin 101 is larger, in groove between adjacent fin 101, the difficulty of deposition medium film improves, material for the formation of deielectric-coating not easily enters channel bottom, the deielectric-coating inside be deposited in groove is easily caused to produce space, dielectric layer 102 inside formed by described deielectric-coating is caused to have space, then formed dielectric layer 102 electric isolution performance is bad, still easily causes puncturing between grid structure 103 and Semiconductor substrate 100, produces leakage current.
In order to solve the problem, after further research, a kind of formation method of semiconductor structure is proposed.Wherein, by injected media ion in the substrate of channel bottom, and the material of medium ionic and substrate is reacted generate first medium layer, then the formed channel bottom of first medium layer between adjacent fin by annealing.Afterwards, second dielectric layer is formed on the first medium layer surface of described channel bottom, described second dielectric layer and first medium layer are jointly as the isolation structure between adjacent fin, therefore described isolation structure has larger thickness, being enough to electric isolution the latter and being formed at the grid structure on second dielectric layer surface and described substrate, can avoiding producing leakage current because there is dielectric breakdown between described grid structure and substrate.
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail specific embodiments of the invention below in conjunction with accompanying drawing.
Fig. 3 to Figure 10 is the section knot schematic diagram of the forming process of the semiconductor structure of the embodiment of the present invention.
Please refer to Fig. 3, provide substrate 200, have some grooves 201 in described substrate 200, the substrate 200 between adjacent trenches 201 forms fin 202, and the top of described fin 202 has mask layer 203.
In the present embodiment, described substrate 200 is body substrate (BulkWafer), the material of described substrate 200 is semi-conducting material, and described body substrate is silicon substrate, germanium substrate, silicon-Germanium substrate or silicon carbide substrates, can form fin 202 by etching described body substrate.Described body substrate cheap, uses described body substrate to be conducive to reducing process costs, and, directly can Simplified flowsheet by etching described body substrate formation fin 202.
In another embodiment, described substrate comprises semiconductor base and is formed at the semiconductor layer of described semiconductor substrate surface.Described semiconductor base is silicon substrate, silicon-Germanium substrate, silicon carbide substrates, silicon-on-insulator substrate, germanium substrate on insulator, glass substrate or III-V substrate, such as gallium nitride substrate or gallium arsenide substrate etc., the selection of described semiconductor base is unrestricted, can choose and be suitable for process requirements or be easy to integrated semiconductor base.The material of described semiconductor layer is silicon, germanium, carborundum or SiGe, the formation process of described semiconductor layer is selective epitaxial depositing operation, subsequently through the described semiconductor layer of etching to form fin, the material of the fin formed is unrestricted, specific process requirements can be met, and the thickness of described semiconductor layer can control, thus control the height of the fin formed.
In the present embodiment, by forming groove 201 to form described fin 202 in described substrate 200, the formation process of described groove 201 comprises: form mask layer 203 on substrate 200 surface, and described mask layer 203 covers substrate 200 surface needing to form fin 202; With described mask layer 203 for mask, etch described substrate 200, in substrate 200, form groove 201.
The quantity of described groove 201 is more than or equal to 2, and the substrate 200 between adjacent trenches 201 is as fin 202, and namely the quantity of described fin 202 is at least 1.The degree of depth of described groove 201 is 90 nanometer ~ 130 nanometers, in the substrate 200 of channel bottom 201, first medium layer is formed due to follow-up, therefore the height of follow-up formation fin 202 is the degree of depth of described groove 201 and the thickness summation of described first medium layer, therefore described groove 201 is dark without the need to being formed, and the follow-up fin 202 higher than second dielectric layer surface also can be made highly to meet technological requirement.Because the degree of depth of described groove 201 is more shallow, the depth-to-width ratio of described groove 201 is also less, is conducive to follow-up in first medium layer surface formation second dielectric layer.
In the present embodiment, described mask layer 203 comprises silicon nitride layer 203a and the silicon oxide layer 203b between described silicon nitride layer 203a and fin 202 surface.In other embodiments, the material of described mask layer can also be one or more combinations in silica, silicon nitride, silicon oxynitride, amorphous carbon.
In the present embodiment, the formation process of described mask layer 203 is multiple graphical masking process, the while that the dimension of picture of the mask layer 203 adopting described multiple graphical masking process can be formed in guarantee being accurate, the dimension of picture of formed mask layer 203 is reduced, be conducive to making formed fin 202 width and groove 201 reduced width, can when ensure institute form the stable performance of fin field effect pipe, reduction of device size, raising device integration.
Described multiple graphics metallization processes comprises autoregistration multiple graphical masking process or double exposure technique; Described autoregistration multiple graphical masking process comprises self-alignment duplex pattern (Self-alignedDoublePatterned, SaDP) technique, triple graphical (Self-alignedTriplePatterned) technique of autoregistration or graphical (Self-alignedDoubleDoublePatterned, SaDDP) technique of autoregistration quadruple; Described double exposure technique comprises LELE (Litho-Etch-Litho-Etch) technique or LLE (Litho-Litho-Etch) technique.
In one embodiment, the formation process of described mask layer 203 is self-alignment duplex pattern metallization processes, comprising: at substrate 200 surface deposition expendable film; Patterned photoresist layer is formed on described expendable film surface; With described photoresist layer for mask, etch described expendable film till exposing substrate 200 surface, form sacrifice layer, and remove photoresist layer; At substrate 200 and sacrificial layer surface deposition of mask material film; Return the described mask material film of etching till exposing sacrifice layer and substrate 200 surface, substrate 200 surface in sacrifice layer both sides forms mask layer 203; After returning etching technics, remove sacrifice layer.
Please refer to Fig. 4, with described mask layer 203 for mask, adopt injected media ion 210 in the substrate 200 of ion implantation technology bottom described groove 201.
Described medium ionic 210 can in follow-up annealing process, react with the semi-conducting material of described substrate 200, and form dielectric material, such as silica, germanium oxide, silicon nitride, germanium nitride, silicon oxynitride or germanium oxynitride etc., the doped region making to have described medium ionic 210 is follow-up can form first medium layer.Described medium ionic 210 is one or both in oxonium ion, Nitrogen ion.For the material of described substrate 200 for silicon is when described medium ionic 210 is oxonium ion, the first medium layer of follow-up formation is silica; When described medium ionic 210 is Nitrogen ion, the first medium layer of follow-up formation is silicon nitride; When described medium ionic 210 be oxonium ion and Nitrogen ion mixing time, the first medium layer of follow-up formation is silicon oxynitride.
Described ion implantation technology is used for forming doped region in the substrate 200 bottom groove 201, and described doped region can form first medium layer through follow-up annealing process.The second dielectric layer of described first medium layer and follow-up formation is jointly as the isolation structure between adjacent fin 202, the isolation structure thickness of follow-up formation can be made thicker, be conducive to reducing the follow-up electric field be formed between the grid structure on second dielectric layer surface and substrate 200, described second dielectric layer and first medium layer not easily puncture, and avoid between grid structure and substrate 200 and produce leakage current.
And the degree of depth due to described doped region and the profile graphics perpendicular to substrate 200 surface direction can be controlled by described ion implantation technology, can make that the thickness of follow-up formed first medium layer is accurate, boundary is good.And the follow-up part also constituting fin 202 of substrate 200 between adjacent first medium layer, the contact interface quality between therefore formed first medium layer and fin 202 sidewall is good, further ensures the electric isolution performance of the isolation structure of follow-up formation.
Again, first medium layer is formed with described doped region, then follow-up only need groove 201 lower surface formed second dielectric layer can form isolation structure, the degree of depth of described groove 201 is without the need to excessive, namely the depth-to-width ratio of described groove 201 is less, can ensure that the follow-up second dielectric layer be formed in groove 201 is fine and close.
The parameter of described ion implantation technology comprises: the medium ionic of doping is one or both mixing in oxonium ion, Nitrogen ion, and Implantation Energy is 0KeV ~ 20KeV, and implantation dosage is 1E16atom/cm
2~ 1E17atom/cm
2, implant angle is perpendicular to substrate surface, and in 90 °, the injection degree of depth is 0nm ~ 50nm.In the present embodiment, the medium ionic adulterated is oxonium ion.
In the present embodiment, described medium ionic 210 is to inject in substrate 200 perpendicular to the direction on substrate 200 surface, top surface due to fin 202 has mask layer 203, described mask layer 203 can stop that described medium ionic 210 enters in fin 202, therefore described medium ionic 210 can enter in the substrate 200 that channel bottom exposes, to form doped region.
Please refer to Fig. 5, adopt annealing process that described medium ionic 210 (as shown in Figure 4) is reacted with the material of substrate 200, form first medium layer 204 in described groove 201 lower surface.
Described annealing process becomes dielectric material for making the semi-conducting material of the medium ionic of ion implantation and substrate 200 react, to form first medium layer 204, the second dielectric layer of described first medium layer 204 and follow-up formation is jointly as the isolation structure between adjacent fin 202, make formed isolation structure thickness thicker, effectively can reduce leakage current.
The parameter of described annealing process comprises: gas nitrogen, argon gas or helium, and temperature is 1200 DEG C ~ 1400 DEG C, and the time is 30 minutes ~ 120 minutes.
The thickness of described first medium layer 204 is 100 dust ~ 1000 dusts, and the thickness of described first medium layer 204 can be controlled by ion implantation technology and annealing process.First medium layer 204 interior solid formed is even, and and contact interface quality between substrate 200 and fin 202 good, make the electric isolating effect of described first medium layer 204 good.
Please refer to Fig. 6, first medium layer 04 surface bottom the sidewall surfaces, groove 201 of described groove 201 and mask layer 203 surface form laying 205.
The material of described laying 205 is silica, and the formation process of described laying 205 is that on-the-spot steam generates (ISSG, In-SituSteamGeneration) annealing process.The parameter that described on-the-spot steam generates annealing process comprises: temperature is 700 DEG C ~ 1200 DEG C, and gas comprises hydrogen and oxygen, and oxygen flow is 1sccm ~ 30sccm, and hydrogen flowing quantity is 1.5sccm ~ 15sccm, and the time is 1 minute ~ 10 minutes.
Described on-the-spot steam is adopted to generate the material dense uniform of the laying 205 that annealing process is formed; and thickness is evenly easily controlled; described laying 205 and can be removed in the technique of follow-up formation second dielectric layer in the process of mask layer 203, protection fin 202 surface.When adopting described on-the-spot steam to generate annealing process formation laying 205, the material of fin 202 can not be consumed, therefore, it is possible to avoid the pattern of described fin 202 to sustain damage, ensure that the size of fin 202 is accurately homogeneous.In addition, described laying 205 can also, in the technique of follow-up formation second dielectric layer, prevent the material of second dielectric layer from spreading in fin 202, to ensure the stable performance of fin 202.
Please refer to Fig. 7, first medium layer 204 surface in groove 201 (as shown in Figure 6) and mask layer 203 surface form the second medium film 206 of filling full groove 201.
The material of described second medium film 206 is silica, and the formation process of described second medium film 206 is fluid chemistry gas-phase deposition (FCVD, FlowableChemicalVaporDeposition).The parameter of described fluid chemistry gas-phase deposition comprises: deposition gases comprises that predecessor is in silane, disilane, methyl-monosilane, dimethylsilane, trimethyl silane, tetramethylsilane, tetraethoxysilane, triethoxysilane, octamethylcy-clotetrasiloxane, tetramethyl disiloxane, tetramethyl-ring tetrasiloxane, the one of trimethylsilyl amine (TSA), dimethyl silanyl amine (DSA), can also be that other silanamines and derivatives etc. thereof are as pre-reaction material; Deposition gases also comprises the mist of nitrogenous gas and hydrogen-containing gas, such as, in nitrogen, hydrogen, ammonia one or more; Deposition gases also comprises oxygen-containing gas, NO, N
2o, NO
2, O
3, O
2, H
2o, H
2o
2in one or more; The flow of described predecessor is with 1sccm ~ 5000sccm, and the flow of nitrogen, hydrogen-containing gas or oxygen-containing gas is 1sccm ~ 1000sccm, and reaction pressure is 0.1T ~ 10T; In addition, can also pass into the inert gases such as Ar, He, Xe in deposition reaction chamber, described inert gas flow velocity is 1sccm ~ 50000sccm; In described deposition process, the temperature of described substrate 200 is less than 200 degrees Celsius, is greater than room temperature.
In described fluid chemistry gas-phase deposition, first make first medium layer 204, fin 202 and mask layer 203 surface formed containing silicon precursor be fluid state, therefore the described silicon precursor that contains is easy to flow into groove 201 inside, afterwards through the annealing process of oxygen atmosphere, the described silicon precursor that contains can be made to be solidified into silica; The time of described oxygen atmosphere annealing is 0.5h ~ 2h, and temperature is 500 degrees Celsius ~ 1200 degrees Celsius.Second medium film 206 even compact formed, functional with the second dielectric layer electric isolution that described second medium film 206 is formed.
Please refer to Fig. 8, described in planarization, second medium film 206 (as shown in Figure 7) is till exposing mask layer 203, forms second dielectric layer 206a on first medium layer 204 surface of groove 201 (as shown in Figure 6) bottom.
Described flatening process, for removing the second medium film 206 higher than mask layer 203 surface, makes the surface of described second medium film 206 smooth, smooth to ensure the second dielectric layer surface that subsequent etching is formed.In the present embodiment, described flatening process is CMP (Chemical Mechanical Polishing) process, and second dielectric layer 206a after polishing surface flushes with the surface of mask layer 203, described mask layer 203 in described glossing for the protection of the top surface of fin 202.In other embodiments, described flatening process can also be back etching technics.
Please refer to Fig. 9, after second medium film described in planarization 206 (as shown in Figure 7), remove described mask layer 203 (as shown in Figure 8).
In the present embodiment, before returning the described second dielectric layer 206a of etching, remove described mask layer 203, and, because described mask layer 203 comprises silicon nitride layer 203a and silicon oxide layer 203b, the technique of described removal mask layer 203 is for removing described silicon nitride layer 203a, and described silicon oxide layer 203b is removed when follow-up time etching second dielectric layer 206a.In other embodiments, after follow-up time etching second dielectric layer 206a, described mask layer 203 can also be removed.
The technique removing described mask layer 203 is wet-etching technology, in the present embodiment, described wet-etching technology is for removing silicon nitride layer 203a and silicon oxide layer 203b, etching liquid is hydrofluoric acid solution and phosphoric acid solution, wherein, described hydrofluoric acid solution is for removing silicon oxide layer 203b, and described phosphoric acid is for removing silicon nitride layer 203a.In described hydrofluoric acid solution, the volume ratio of water and hydrofluoric acid is 50:1 ~ 100:1, and the concentration of hydrofluoric acid is less than 49%, and the mass percent concentration of described phosphoric acid solution is 85%.Because the concentration of described hydrofluoric acid solution is lower, when etching described silicon oxide layer 203b, less to the damage of second dielectric layer 206a, then after follow-up time etching second dielectric layer 206a, the thickness more controllable precise of second dielectric layer.And; because described wet-etching technology is larger for the selectivity of silicon nitride and silica; when removing described silicon nitride layer 203a, described fin 202 top surface has silicon oxide layer 203b and protects, and avoids described fin 202 top surface and sustains damage.
Please refer to Figure 10, after the described mask layer 203 of removal, return the described second dielectric layer 206a of etching (as shown in Figure 9), till top surface lower than fin 202 of the surface of described second dielectric layer 206b.
Described time etching technics is remote plasma chemical drying method etching technics (SiCONI), comprising: etching gas comprises NF
3and NH
3, NF
3with NH
3flow-rate ratio be 1:20 ~ 5:1, etching temperature is 40 degrees Celsius ~ 80 degrees Celsius, pressure be 0.5 holder ~ 50 hold in the palm, power is less than 100 watts, and frequency is less than 100 KHz.
Described remote plasma chemical drying method etching technics is a kind of isotropic etching technics, little to the surface damage of fin 202, after passing through back etching technics, can ensure that sidewall and the top surface pattern of described fin 202 are good, it is less to damage, ensure that the characteristic size (CD, CriticalDimension) of fin 202 is accurately homogeneous with this.
After described time etching technics, the thickness of described second dielectric layer 206b is 2500 dust ~ 5000 dusts, described second dielectric layer 206b and first medium layer 204 are jointly as the isolation structure between adjacent fin 202, therefore the thickness of described isolation structure is thicker, the follow-up electric field be formed between the grid structure on second dielectric layer 206b surface and substrate 200 is reduced, described isolation structure is difficult to breakdown, because this reducing the leakage current between grid structure and substrate 200, the performance improvement of follow-up formed fin formula field effect transistor.
It should be noted that, after returning the described second dielectric layer 206a of etching, the grid structure being across described fin 202 is formed at second dielectric layer 206b surface and the sidewall of fin 202 and top surface, in the fin 202 of described grid structure both sides, form source region and drain region, thus form fin formula field effect transistor.
Described grid structure comprises: be positioned at second dielectric layer 206b surface and the sidewall of fin 202 and the gate dielectric layer of lower surface, be positioned at the grid layer on gate dielectric layer surface, and be positioned at the side wall of grid layer and gate dielectric layer sidewall surfaces.
The formation process of described grid structure comprises: form gate dielectric film at second dielectric layer 206b surface and the sidewall of fin 202 and top surface; Gate electrode film is formed on described gate dielectric film surface; Etched portions gate electrode film and gate dielectric film, until the sidewall and the top surface that expose second dielectric layer 206b surface and fin 202, form grid layer and gate dielectric layer; Side wall is formed in the sidewall surfaces of described grid layer and gate dielectric layer.
In one embodiment, the material of described gate dielectric film is silica, and the material of described gate electrode film is polysilicon, and the formation process of described gate dielectric film and grid film is chemical vapor deposition method.The material of described side wall is one or more combinations in silica, silicon nitride, silicon oxynitride, and the formation process of described side wall comprises: at described grid layer, gate dielectric layer and fin 202 surperficial formation side wall film; Return the described side wall film of etching until expose sidewall and the top surface of grid layer surface and fin 202, fin 202 sidewall in grid layer and gate dielectric layer both sides and top surface form side wall.
In another embodiment, the grid structure of required formation is high-K metal gate (HKMG) structure, then the formation process of described grid structure is rear grid technique (GateLast).First at second dielectric layer 206b surface and the sidewall of fin 202 and top surface deposition dummy grid film, the material of described dummy grid film is polysilicon; Etched portions dummy grid film, until the sidewall and the top surface that expose second dielectric layer 206b surface and fin 202, form dummy gate layer, described dummy gate layer is across sidewall and the top surface of fin 202; Second dielectric layer 206b surface in described dummy gate layer both sides and the sidewall of fin 202 and top surface form side wall; After formation side wall, at sidewall and top surface formation the 3rd dielectric layer of second dielectric layer 206b surface, fin 202, the surface of described dielectric layer flushes with the surface of dummy gate layer; Remove dummy gate layer, in the 3rd dielectric layer, form opening; High-K gate dielectric layer is formed, in the metal gate layers on high-K dielectric layer surface in described opening.
In the present embodiment, by injected media ion in the substrate of channel bottom, and the material of medium ionic and substrate is reacted generate first medium layer, then the formed channel bottom of first medium layer between adjacent fin by annealing.Afterwards, second dielectric layer is formed on the first medium layer surface of described channel bottom, described second dielectric layer and first medium layer are jointly as the isolation structure between adjacent fin, therefore described isolation structure has larger thickness, the follow-up electric field be formed between the grid structure on second dielectric layer surface and substrate is reduced, make not easily to puncture between described grid structure and substrate, avoid between described grid structure and substrate and produce leakage current, then the stable performance of formed fin field effect pipe.
Secondly, by ion implantation technology at channel bottom injected media ion, and form first medium layer by annealing process, then described first medium layer accurately can be controlled by described ion implantation technology perpendicular to the profile graphics of substrate surface, make the contact interface quality between described first medium layer and fin good, the profile graphics pattern of described first medium layer is accurate.Especially, bottom described first medium layer to the corner of sidewall and contact interface between described substrate and fin sidewall good, therefore described first medium layer has good electric isolution ability.
Again, total height due to described fin equals the height of described fin higher than second dielectric layer surface and the thickness summation of second dielectric layer, therefore the total height of described fin can be reduced, namely formed gash depth can reduce, the depth-to-width ratio of described groove reduces, make described second dielectric layer easily be formed at channel bottom, and the second dielectric layer quality formed is better, interior solid.Therefore the electric isolution of described second dielectric layer and first medium layer is functional.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (18)
1. a formation method for semiconductor structure, is characterized in that, comprising:
There is provided substrate, have some grooves in described substrate, the substrate between adjacent trenches forms fin, and the top of described fin has mask layer;
With described mask layer for mask, adopt ion implantation technology injected media ion in the substrate of described channel bottom;
Adopt annealing process that the material of described medium ionic and substrate is reacted, form first medium layer in described trench bottom surfaces;
Form second dielectric layer on the first medium layer surface of described channel bottom, the surface of described second dielectric layer is lower than the top surface of described fin.
2. the formation method of semiconductor structure as claimed in claim 1, it is characterized in that, the parameter of described ion implantation technology comprises: Doped ions is oxonium ion, and Implantation Energy is 0KeV ~ 20KeV, and implantation dosage is 1E16atom/cm
2~ 1E17atom/cm
2, implant angle perpendicular to substrate surface, be 90 °, the injection degree of depth is 0nm ~ 50nm.
3. the formation method of semiconductor structure as claimed in claim 1, it is characterized in that, the parameter of described annealing process comprises: gas nitrogen, argon gas or helium, and temperature is 1200 DEG C ~ 1400 DEG C, and the time is 30 minutes ~ 120 minutes.
4. the formation method of semiconductor structure as claimed in claim 1, it is characterized in that, the formation method of described second dielectric layer comprises: the first medium layer surface in groove and mask layer surface form the second medium film of filling full groove; Described in planarization, second medium film is till exposing mask layer, in groove, form second dielectric layer; Return the described second dielectric layer of etching, till top surface lower than fin of the surface of described second dielectric layer.
5. the formation method of semiconductor structure as claimed in claim 4, it is characterized in that, the material of described second medium film is silica, and the formation process of described second medium film is fluid chemistry gas-phase deposition.
6. the formation method of semiconductor structure as claimed in claim 4, is characterized in that, before returning the described second dielectric layer of etching, removes described mask layer.
7. the formation method of semiconductor structure as claimed in claim 6, it is characterized in that, the technique removing described mask layer is wet-etching technology, etching liquid is hydrofluoric acid solution and phosphoric acid solution, in described hydrofluoric acid solution, the volume ratio of water and hydrofluoric acid is 50:1 ~ 100:1, and the concentration of hydrofluoric acid is less than 49%, and the mass percent concentration of described phosphoric acid solution is 85%.
8. the formation method of semiconductor structure as claimed in claim 4, it is characterized in that, also comprise: before the described second medium film of formation, form laying on the sidewall surfaces of described groove, the first medium layer surface of channel bottom and mask layer surface, described second medium film is formed at described laying surface.
9. the formation method of semiconductor structure as claimed in claim 8, it is characterized in that, the material of described laying is silica, and the formation process of described laying is that on-the-spot steam generates annealing process.
10. the formation method of semiconductor structure as claimed in claim 4, it is characterized in that, described time etching technics is remote plasma chemical drying method etching technics, comprising: etching gas comprises NF
3and NH
3, NF
3with NH
3flow-rate ratio be 1:20 ~ 5:1, etching temperature is 40 degrees Celsius ~ 80 degrees Celsius, pressure be 0.5 holder ~ 50 hold in the palm, power is less than 100 watts, and frequency is less than 100 KHz.
The formation method of 11. semiconductor structures as claimed in claim 1, it is characterized in that, described mask layer comprises silicon nitride layer.
The formation method of 12. semiconductor structures as claimed in claim 11, it is characterized in that, described mask layer also comprises the silicon oxide layer between described silicon nitride layer and fin portion surface.
The formation method of 13. semiconductor structures as claimed in claim 1, it is characterized in that, the formation process of described groove comprises: form mask layer at substrate surface, and described mask layer covers the substrate surface needing to form fin; With described mask layer for mask, etch described substrate, in substrate, form groove.
The formation method of 14. semiconductor structures as claimed in claim 13, is characterized in that, the formation process of described mask layer is multiple graphical masking process.
The formation method of 15. semiconductor structures as claimed in claim 1, it is characterized in that, the quantity of described groove is more than or equal to 2, and the degree of depth of described groove is 90 nanometer ~ 130 nanometers.
The formation method of 16. semiconductor structures as claimed in claim 1, is characterized in that, the thickness of described first medium layer is 100 dust ~ 1000 dusts, and the thickness of described second dielectric layer is 2500 dust ~ 5000 dusts.
The formation method of 17. semiconductor structures as claimed in claim 1, is characterized in that, also comprise: form at second dielectric layer surface and the sidewall of fin and top surface the grid structure being across described fin.
The formation method of 18. semiconductor structures as claimed in claim 17, it is characterized in that, described grid structure comprises: be positioned at the sidewall of second dielectric layer surface and fin and the gate dielectric layer of lower surface, be positioned at the grid layer on gate dielectric layer surface, and be positioned at the side wall of grid layer and gate dielectric layer sidewall surfaces.
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