CN103545185A - Method of producing semiconductor device by pseudo-gate - Google Patents
Method of producing semiconductor device by pseudo-gate Download PDFInfo
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- CN103545185A CN103545185A CN201210243837.XA CN201210243837A CN103545185A CN 103545185 A CN103545185 A CN 103545185A CN 201210243837 A CN201210243837 A CN 201210243837A CN 103545185 A CN103545185 A CN 103545185A
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Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
Abstract
The invention provides a method of producing a semiconductor device by a pseudo-gate. The method includes the steps of providing a semiconductor substrate comprising a first area and a second area; forming a first pseudo-gate on the substrate in the first area, and forming a second pseudo-gate on the substrate in the second area; forming a source and a drain in the substrate; forming a barrier layer at the top of the second pseudo-gate; removing a polycrystalline silicon layer of the first pseudo-gate by wet etching to form a trench; filling the trench to form a metal gate. Each of the first and second pseudo-gates comprises a gate dielectric layer, a covering layer and a polycrystalline layer. The method has the advantages that the corresponding part of the pseudo-gate of polycrystalline silicon during the production process of semiconductor can be removed in a height selecting manner, the damage of the device can be avoided, and the performance of the produced semiconductor device is improved.
Description
Technical field
The present invention relates to a kind of technical field of manufacturing semiconductors, more precisely, the present invention relates to a kind of method that adopts dummy grid to manufacture semiconductor device.
Background technology
In using the process of dummy grid manufacture semiconductor device, be usually included on substrate and form dummy grid, source drain, then remove appropriate section on dummy grid and fill because removing groove that this part of dummy grid produces with a series of steps such as formation grids.In this series of step, the removal of dummy grid appropriate section is a very crucial step.Generally use dry etching removing by the formed dummy grid of polysilicon, but the Etch selectivity of dry etching is undesirable, tends to device to cause unnecessary damage, thereby the performance of the device of manufacturing is impacted.
But adopting at present dummy grid to manufacture in the technique of semiconductor device does not have method to overcome the problems referred to above.
Summary of the invention
In view of above problem, the invention provides a kind of method that adopts dummy grid to manufacture semiconductor device, comprise step:
A) provide Semiconductor substrate, described Semiconductor substrate comprises first area and second area;
B) on the substrate of described first area, form the first dummy grid, form the second dummy grid on the substrate of described second area, described the first dummy grid and the second dummy grid comprise gate dielectric, cover layer and the polysilicon layer of storehouse successively;
C) in described substrate, form source-drain electrode;
D) on formation barrier layer, the top of described the second dummy grid;
E) polysilicon layer that employing wet etching is removed described the first dummy grid is to form groove;
F) fill described groove and form metal gates.
Further, described step d) comprises:
On the polysilicon layer of described the first dummy grid, form mask layer;
On the polysilicon layer of described the second dummy grid, form described barrier layer;
Remove the mask layer on the polysilicon layer of described the first dummy grid;
Further, wherein said mask layer is photoresist layer.
Further, be wherein also included between described photoresist layer and described polysilicon layer and form BARC.
Further, wherein said barrier layer is oxide layer or nitration case.
Further, wherein said barrier layer has the thickness that is greater than 30 dusts.
Further, the method on wherein said formation barrier layer is the method for plasma or the method for Implantation.
Further, in wherein said removal mask layer step, use the gas that comprises H2 and N2.
Further, the solution using in the polysilicon layer step of wherein said wet etching the first dummy grid comprises TMAH.
Further, the solution using in the polysilicon layer step of wherein said wet etching the first dummy grid comprises KTMAH.
Further, be also included in the step that described removal mask layer step is removed natural oxidizing layer afterwards.
Further, wherein with DHF, carry out the removal of described natural oxidizing layer.
Further, the step of wherein said removal natural oxidizing layer is carried out in the identical reaction chamber of the step with described wet etching polysilicon layer.
Further, be also included in the polysilicon layer formation groove that step f) is removed the second dummy grid afterwards; Fill described groove and form metal gates.
Further, the method for the polysilicon layer of wherein said removal the second dummy grid is the method that wet etching is removed.
Further, be also included between described substrate and described dummy grid and form boundary layer.
Further, wherein use hafnium to form described gate dielectric.
Further, wherein with TiN or TaN, form described cover layer.
Further, after being also included in step b), on the sidewall of described dummy grid and substrate, form the step of offset side wall and clearance wall.
Further, be also included in the ILD that forms ILD after step c) on described substrate and described the first and second dummy grids and described in planarization to expose the step of described the first dummy grid and the second dummy grid.
In the present invention, adopt the method for dummy grid can in semi-conductive manufacture process, to the appropriate section of the dummy grid of polysilicon, carry out the removal of high selectivity in the manufacture process of semiconductor device, thereby can avoid device to cause damage, thereby the performance of the semiconductor device of raising manufacturing.
Accompanying drawing explanation
Fig. 1-8th, the device profile map of each processing step of the present invention.
Embodiment
In the following description, a large amount of concrete details have been provided to more thorough understanding of the invention is provided.Yet, it is obvious to the skilled person that the present invention can be implemented without one or more these details.In other example, for fear of obscuring with the present invention, for technical characterictics more well known in the art, be not described.
In order thoroughly to understand the present invention, will detailed step be proposed in following description, so that the employing dummy grid that explaination the present invention proposes is manufactured the method for semiconductor device.Obviously, execution of the present invention is not limited to the specific details that the technical staff of semiconductor applications has the knack of.Preferred embodiment of the present invention is described in detail as follows, yet except these are described in detail, the present invention can also have other execution modes.
Should be understood that, when using in this manual term " to comprise " and/or when " comprising ", it indicates and has described feature, integral body, step, operation, element and/or assembly, but do not get rid of, do not exist or add one or more other features, integral body, step, operation, element, assembly and/or their combination next, in connection with accompanying drawing, more intactly describing the present invention.
With reference to Fig. 1.First, provide Semiconductor substrate 200.Comprise first area and second area, described first area can be PMOS region, and described second area can be territory, nmos area.Described substrate can be at least one in following mentioned material: stacked SiGe (S-SiGeOI) and germanium on insulator SiClx (SiGeOI) etc. on stacked silicon (SSOI), insulator on silicon, silicon-on-insulator (SOI), insulator.In described substrate, can be formed with doped region and/or isolation structure, described isolation structure is that shallow trench isolation is from (STI) structure or selective oxidation silicon (LOCOS) isolation structure.In an embodiment of the present invention, described substrate can be Si substrate, and it can also be included in the boundary layer on Si, not shown.By rapid thermal oxidation process (RTO) or atom layer deposition process (ALD), form the SiO2 boundary layer with 5-10A in one embodiment.Then on this substrate, form gate dielectric 201, can select hafnium to form described gate dielectric, such as being used in hafnium that the ratio introducing the elements such as Si, Al, N, La, Ta in Hf02 and optimize each element obtains etc.The method of described formation gate dielectric can be physical gas-phase deposition or atom layer deposition process (ALD).In an embodiment of the present invention, on described SiO2 boundary layer, form HfAION gate dielectric, its thickness is 15 to 60 dusts.Afterwards, forming the cover layer 202 of stack structure on gate dielectric 201, can be the cover layer of the formed TiN of ALD or TaN.Deposit spathic silicon layer 300 on cover layer 202 afterwards.In one embodiment of the invention, use low-pressure chemical vapor phase deposition (LPCVD) technique to form polysilicon layer, its process conditions comprise: reacting gas is silane (SiH4), the range of flow of described silane is 100～200 cc/min (sccm), as 150sccm; In reaction chamber, temperature range is 700～750 degrees Celsius; Reaction chamber internal pressure is 250～350 milli millimetress of mercury (mTorr), as 300mTorr; In described reacting gas, also comprise buffer gas, described buffer gas can be helium (He) or nitrogen, and the range of flow of described helium and nitrogen is 5～20 liters/min (slm), as 8slm, 10slm or 15slm.
Then, can use photoetching process to carry out patterned process to form the dummy gate structure of storehouse to the formed boundary layer of above step, gate dielectric 201, cover layer 202 and polysilicon layer 300.
As shown in Figure 2.Can also form the step of offset side wall (offset spacer) 211.The material of offset side wall can be the insulating material such as silicon nitride, silica or silicon oxynitride.Offset side wall can improve the transistorized channel length of formation, the hot carrier's effect that reduces short-channel effect and cause due to short-channel effect.The technique that forms offset side wall can be chemical vapour deposition (CVD).The thickness of formed offset side wall may diminish to 80 dusts in one embodiment.
And the step of formation light dope source electrode/drain electrode (LDD) in the substrate of grid structure either side.The method of described formation LDD can be ion implantation technology or diffusion technology.The ionic type that LDD injects is according to the electrical decision of the semiconductor device that will form, and the device forming is nmos device, and the foreign ion mixing in LDD injection technology is a kind of or combination in phosphorus, arsenic, antimony, bismuth; If the device forming is PMOS device, the foreign ion injecting is boron.According to the concentration of required foreign ion, ion implantation technology can a step or multistep complete.
And the step that forms clearance wall (Spacer) 212 on substrate 200 and the formed offset side wall of above-mentioned steps.Can use the material of silicon nitride, carborundum, silicon oxynitride or its combination.Can on substrate, deposit the first silicon oxide layer, the first silicon nitride layer and the second silicon oxide layer, then adopt engraving method to form clearance wall, described clearance wall can have the thickness of 10-30NM.
And with ion implantation technology or diffusion technology heavy doping source electrode and drain electrode (S/D), being formed at the step in the substrate of grid gap wall either side, high-temperature annealing step, forms the step (not shown)s such as metal silicide (SAB) barrier layer.
With reference to Fig. 3.Then can also be at the surface deposition etching stopping layer of device, not shown.Etching stopping layer can be used the formation such as SiCN, SiN, SiC, SiOF, SiON.Then deposit interlayer dielectric layer (ILD) 220 on grid structure and between.Can adopt the methods such as chemical vapour deposition technique, high density plasma CVD method, method of spin coating, sputter to form, described interlayer dielectric layer can adopt the materials such as silica, silicon oxynitride, silicon nitride to form.
With reference to Fig. 4.Then interlayer dielectric layer 220 and/or etching stop layer are carried out to planarization.The limiting examples of described planarization comprises mechanical planarization method and chemico-mechanical polishing flattening method.To expose the upper surface of dummy gate structure.Use in one embodiment the method for CMP with exposed polysilicon layer 300.
With reference to Fig. 5.In the interlayer dielectric layer of the first dummy gate region of then processing in planarisation step and the first dummy gate structure exposing, form mask layer 301.In one embodiment, on the polysilicon layer exposing in PFET region and ILD, form mask layer.Can comprise any of several mask materials, include but not limited to: hard mask material and photoresist mask material.Preferably, mask layer comprises photoresist mask material.Photoresist mask material can comprise being selected from and comprises positive photoresist material, negative photoresist material and mix photoetching glue material etc.This mask layer can comprise having thickness from the about 2000 positive photoresist materials to about 5000 dusts or negative photoresist material.The bottom antireflective coating (BARC) that can also comprise in one embodiment photoresist, can form this BARC with TiN or SiN.
With reference to Fig. 6.On the polysilicon layer of the second dummy grid exposing, form barrier layer 302 after planarisation step.In one embodiment, this barrier layer is formed on the polysilicon layer of NFET region dummy grid.This barrier layer can be oxide layer or the nitration case being formed on polysilicon layer, can use the method for plasma oxidation or nitrogenize and the method for Implantation.The method of plasma oxidation is in one embodiment carried out in the system of PECVD, its radio frequency primary frequency is 13.56Hz, source of the gas is the mist of argon gas and oxygen, its ratio is 9:1, gas flow is 50sccm, and reative cell air pressure is 5.26*104Pa, and underlayer temperature is 250 degrees Celsius, radio frequency source power is 2W/cm2, and the thickness of formed oxide layer can be greater than 30 dusts.
With reference to Fig. 7.Then remove the step of mask layer 301.Its condition is included in and in reaction chamber, passes into O2.In one embodiment, also comprise the mist passing into, it comprises appropriate N2 and H2, thereby accelerates to increase ion concentration the speed of removing.
After above step completes, the thickness of the oxide layer on the polysilicon layer of the dummy gate structure that is formed at will have different thickness, and it also comprises natural oxidizing layer.Viewed oxide layer comprises the natural oxidizing layer of about 10 dusts and in the oxide layer of the diauxic growth of approximately 30 dusts in PFET region in one embodiment.
Then remove the step of natural oxidizing layer and by the method for wet etching erosion, remove the step of the polysilicon layer of the first dummy gate structure.In an embodiment of the present invention, utilize hydrofluoric acid (DHF) technique of dilution that natural oxidizing layer is eroded, the volume ratio of HF:H2O can be 1:(10-200), treatment temperature is 20-25 degree Celsius, and this technique can make the corrosion of natural oxidizing layer end at the polysilicon layer surface that oxygen content is very low.
Can utilize Tetramethylammonium hydroxide (TMAH) to remove the polysilicon layer of the first dummy grid.The tetramethyl hydrogen ammonia spirit that in an embodiment, working concentration is 22%wt removes the polysilicon layer of NFET region dummy grid.In a further embodiment, also use anisotropic etchant (KTMAH) to remove polysilicon layer, in the TMAH aqueous solution, add potassium hydroxide (KOH), wherein the mass fraction of TMAH is that the mol ratio of 10%-25%, TMAH and KOH is 2-4, and the temperature of reaction is 60-90 degree Celsius.Thereby the polysilicon layer of the first dummy grid can be removed to form groove, as shown in Figure 8.
Thereby the movement that wherein the above step of removing natural oxide and removing the polysilicon layer of the first dummy gate structure can carry out reducing device in same reaction chamber reduces the probability of damage.
Because the barrier layer forming on the above-mentioned polysilicon layer exposing at the second dummy grid has certain thickness; and wet etching erosion of the present invention is limited to the effect of its etching; so the polysilicon layer that it can protect its below, can be applied in the removal step of the first dummy grid polysilicon layer the lithographic method with high selectivity.
Then in the groove forming removing the first dummy grid polysilicon layer, filling grid material to form grid, can be to fill metal material to form metal gate.Metal gate in one embodiment can also comprise: TiN, TaN, TiN and TaN and above-mentioned combination workfunction layers; The barrier layer of TaN, TiN, TaC, TaSiN, WN, TiAl, TiAlN or above-mentioned combination; With conductive layer etc.The method that forms grid can comprise the steps such as deposition, annealing and planarization.
Then remove the second dummy grid polysilicon layer to form the step of groove and to fill the step that described groove forms grid.
Then carry out subsequent technique to complete the manufacture of semiconductor element.
For the purpose of illustration and description, provided the above description of various aspects of the present invention.It is not intended to exclusive list or limits the invention to disclosed precise forms, and significantly, can carry out numerous modifications and variations.The present invention is intended to it will be apparent to those skilled in the art that these modifications and variations are included in the scope of the present invention being defined by the following claims.
Claims (20)
1. adopt dummy grid to manufacture a method for semiconductor device, comprise step:
A) provide Semiconductor substrate, described Semiconductor substrate comprises first area and second area;
B) on the substrate of described first area, form the first dummy grid, form the second dummy grid on the substrate of described second area, described the first dummy grid and the second dummy grid comprise gate dielectric, cover layer and the polysilicon layer of storehouse successively;
C) in described substrate, form source-drain electrode;
D) on formation barrier layer, the top of described the second dummy grid;
E) polysilicon layer that employing wet etching is removed described the first dummy grid is to form groove;
F) fill described groove and form metal gates.
2. method according to claim 1, described step d) comprises:
On the polysilicon layer of described the first dummy grid, form mask layer;
On the polysilicon layer of described the second dummy grid, form described barrier layer;
Remove the mask layer on the polysilicon layer of described the first dummy grid.
3. method according to claim 2, wherein said mask layer is photoresist layer.
4. method according to claim 3, is wherein also included between described photoresist layer and described polysilicon layer and forms BARC.
5. method according to claim 1, wherein said barrier layer is oxide layer or nitration case.
6. method according to claim 1, wherein said barrier layer has the thickness that is greater than 30 dusts.
7. method according to claim 1, the method on wherein said formation barrier layer is the method for plasma or the method for Implantation.
8. according to the method described in claim 2,3 or 4, in wherein said removal mask layer step, use the gas that comprises H2 and N2.
9. method according to claim 1, the solution using in the polysilicon layer step of wherein said wet etching the first dummy grid comprises TMAH.
10. method according to claim 1, the solution using in the polysilicon layer step of wherein said wet etching the first dummy grid comprises KTMAH.
11. according to the method described in claim 2,3 or 4, is also included in the step that described removal mask layer step is removed natural oxidizing layer afterwards.
12. methods according to claim 11, wherein carry out the removal of described natural oxidizing layer with DHF.
13. methods according to claim 11, the step of wherein said removal natural oxidizing layer is carried out in the identical reaction chamber of the step with described wet etching polysilicon layer.
14. methods according to claim 1, are also included in the polysilicon layer formation groove that step f) is removed the second dummy grid afterwards; Fill described groove and form metal gates.
15. methods according to claim 14, the method for the polysilicon layer of wherein said removal the second dummy grid is the method that wet etching is removed.
16. methods according to claim 1, are also included between described substrate and described dummy grid and form boundary layer.
17. methods according to claim 1, are wherein used hafnium to form described gate dielectric.
18. methods according to claim 1, wherein form described cover layer with TiN or TaN.
19. methods according to claim 1 after being also included in step b), form the step of offset side wall and clearance wall on the sidewall of described dummy grid and substrate.
20. methods according to claim 1, are also included in the ILD that forms ILD after step c) on described substrate and described the first and second dummy grids and described in planarization to expose the step of described the first dummy grid and the second dummy grid.
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